1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
);
46 /* forward declarations */
47 int arm9tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
48 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
51 target_type_t arm9tdmi_target
=
56 .arch_state
= armv4_5_arch_state
,
59 .resume
= arm7_9_resume
,
62 .assert_reset
= arm7_9_assert_reset
,
63 .deassert_reset
= arm7_9_deassert_reset
,
64 .soft_reset_halt
= arm7_9_soft_reset_halt
,
66 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
68 .read_memory
= arm7_9_read_memory
,
69 .write_memory
= arm7_9_write_memory
,
70 .bulk_write_memory
= arm7_9_bulk_write_memory
,
72 .run_algorithm
= armv4_5_run_algorithm
,
74 .add_breakpoint
= arm7_9_add_breakpoint
,
75 .remove_breakpoint
= arm7_9_remove_breakpoint
,
76 .add_watchpoint
= arm7_9_add_watchpoint
,
77 .remove_watchpoint
= arm7_9_remove_watchpoint
,
79 .register_commands
= arm9tdmi_register_commands
,
80 .target_command
= arm9tdmi_target_command
,
81 .init_target
= arm9tdmi_init_target
,
85 int arm9tdmi_examine_debug_reason(target_t
*target
)
87 /* get pointers to arch-specific information */
88 armv4_5_common_t
*armv4_5
= target
->arch_info
;
89 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
91 /* only check the debug reason if we don't know it already */
92 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
93 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
95 scan_field_t fields
[3];
100 jtag_add_end_state(TAP_PD
);
102 fields
[0].device
= arm7_9
->jtag_info
.chain_pos
;
103 fields
[0].num_bits
= 32;
104 fields
[0].out_value
= NULL
;
105 fields
[0].out_mask
= NULL
;
106 fields
[0].in_value
= databus
;
107 fields
[0].in_check_value
= NULL
;
108 fields
[0].in_check_mask
= NULL
;
109 fields
[0].in_handler
= NULL
;
110 fields
[0].in_handler_priv
= NULL
;
112 fields
[1].device
= arm7_9
->jtag_info
.chain_pos
;
113 fields
[1].num_bits
= 3;
114 fields
[1].out_value
= NULL
;
115 fields
[1].out_mask
= NULL
;
116 fields
[1].in_value
= &debug_reason
;
117 fields
[1].in_check_value
= NULL
;
118 fields
[1].in_check_mask
= NULL
;
119 fields
[1].in_handler
= NULL
;
120 fields
[1].in_handler_priv
= NULL
;
122 fields
[2].device
= arm7_9
->jtag_info
.chain_pos
;
123 fields
[2].num_bits
= 32;
124 fields
[2].out_value
= NULL
;
125 fields
[2].out_mask
= NULL
;
126 fields
[2].in_value
= instructionbus
;
127 fields
[2].in_check_value
= NULL
;
128 fields
[2].in_check_mask
= NULL
;
129 fields
[2].in_handler
= NULL
;
130 fields
[2].in_handler_priv
= NULL
;
132 arm_jtag_scann(&arm7_9
->jtag_info
, 0x1);
133 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
);
135 jtag_add_dr_scan(3, fields
, TAP_PD
);
136 jtag_execute_queue();
138 fields
[0].in_value
= NULL
;
139 fields
[0].out_value
= databus
;
140 fields
[1].in_value
= NULL
;
141 fields
[1].out_value
= &debug_reason
;
142 fields
[2].in_value
= NULL
;
143 fields
[2].out_value
= instructionbus
;
145 jtag_add_dr_scan(3, fields
, TAP_PD
);
147 if (debug_reason
& 0x4)
148 if (debug_reason
& 0x2)
149 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
151 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
153 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
159 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
160 int arm9tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 instr
, u32 out
, u32
*in
, int sysspeed
)
162 scan_field_t fields
[3];
165 u8 sysspeed_buf
= 0x0;
168 buf_set_u32(out_buf
, 0, 32, out
);
170 buf_set_u32(instr_buf
, 0, 32, flip_u32(instr
, 32));
173 buf_set_u32(&sysspeed_buf
, 2, 1, 1);
175 jtag_add_end_state(TAP_PD
);
176 arm_jtag_scann(jtag_info
, 0x1);
177 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
179 fields
[0].device
= jtag_info
->chain_pos
;
180 fields
[0].num_bits
= 32;
181 fields
[0].out_value
= out_buf
;
182 fields
[0].out_mask
= NULL
;
183 fields
[0].in_value
= NULL
;
186 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
187 fields
[0].in_handler_priv
= in
;
191 fields
[0].in_handler
= NULL
;
192 fields
[0].in_handler_priv
= NULL
;
194 fields
[0].in_check_value
= NULL
;
195 fields
[0].in_check_mask
= NULL
;
197 fields
[1].device
= jtag_info
->chain_pos
;
198 fields
[1].num_bits
= 3;
199 fields
[1].out_value
= &sysspeed_buf
;
200 fields
[1].out_mask
= NULL
;
201 fields
[1].in_value
= NULL
;
202 fields
[1].in_check_value
= NULL
;
203 fields
[1].in_check_mask
= NULL
;
204 fields
[1].in_handler
= NULL
;
205 fields
[1].in_handler_priv
= NULL
;
207 fields
[2].device
= jtag_info
->chain_pos
;
208 fields
[2].num_bits
= 32;
209 fields
[2].out_value
= instr_buf
;
210 fields
[2].out_mask
= NULL
;
211 fields
[2].in_value
= NULL
;
212 fields
[2].in_check_value
= NULL
;
213 fields
[2].in_check_mask
= NULL
;
214 fields
[2].in_handler
= NULL
;
215 fields
[2].in_handler_priv
= NULL
;
217 jtag_add_dr_scan(3, fields
, -1);
219 jtag_add_runtest(0, -1);
221 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
223 jtag_execute_queue();
227 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr
, out
, *in
);
230 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr
, out
);
237 /* just read data (instruction and data-out = don't care) */
238 int arm9tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
240 scan_field_t fields
[3];
242 jtag_add_end_state(TAP_PD
);
243 arm_jtag_scann(jtag_info
, 0x1);
244 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
246 fields
[0].device
= jtag_info
->chain_pos
;
247 fields
[0].num_bits
= 32;
248 fields
[0].out_value
= NULL
;
249 fields
[0].out_mask
= NULL
;
250 fields
[0].in_value
= NULL
;
251 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
252 fields
[0].in_handler_priv
= in
;
253 fields
[0].in_check_value
= NULL
;
254 fields
[0].in_check_mask
= NULL
;
256 fields
[1].device
= jtag_info
->chain_pos
;
257 fields
[1].num_bits
= 3;
258 fields
[1].out_value
= NULL
;
259 fields
[1].out_mask
= NULL
;
260 fields
[1].in_value
= NULL
;
261 fields
[1].in_handler
= NULL
;
262 fields
[1].in_handler_priv
= NULL
;
263 fields
[1].in_check_value
= NULL
;
264 fields
[1].in_check_mask
= NULL
;
266 fields
[2].device
= jtag_info
->chain_pos
;
267 fields
[2].num_bits
= 32;
268 fields
[2].out_value
= NULL
;
269 fields
[2].out_mask
= NULL
;
270 fields
[2].in_value
= NULL
;
271 fields
[2].in_check_value
= NULL
;
272 fields
[2].in_check_mask
= NULL
;
273 fields
[2].in_handler
= NULL
;
274 fields
[2].in_handler_priv
= NULL
;
276 jtag_add_dr_scan(3, fields
, -1);
278 jtag_add_runtest(0, -1);
280 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
282 jtag_execute_queue();
286 DEBUG("in: 0x%8.8x", *in
);
290 ERROR("BUG: called with in == NULL");
298 /* clock the target, and read the databus
299 * the *in pointer points to a buffer where elements of 'size' bytes
300 * are stored in big (be==1) or little (be==0) endianness
302 int arm9tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
304 scan_field_t fields
[3];
306 jtag_add_end_state(TAP_PD
);
307 arm_jtag_scann(jtag_info
, 0x1);
308 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
310 fields
[0].device
= jtag_info
->chain_pos
;
311 fields
[0].num_bits
= 32;
312 fields
[0].out_value
= NULL
;
313 fields
[0].out_mask
= NULL
;
314 fields
[0].in_value
= NULL
;
318 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be32
: arm_jtag_buf_to_le32
;
321 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be16
: arm_jtag_buf_to_le16
;
324 fields
[0].in_handler
= arm_jtag_buf_to_8
;
327 fields
[0].in_handler_priv
= in
;
328 fields
[0].in_check_value
= NULL
;
329 fields
[0].in_check_mask
= NULL
;
331 fields
[1].device
= jtag_info
->chain_pos
;
332 fields
[1].num_bits
= 3;
333 fields
[1].out_value
= NULL
;
334 fields
[1].out_mask
= NULL
;
335 fields
[1].in_value
= NULL
;
336 fields
[1].in_handler
= NULL
;
337 fields
[1].in_handler_priv
= NULL
;
338 fields
[1].in_check_value
= NULL
;
339 fields
[1].in_check_mask
= NULL
;
341 fields
[2].device
= jtag_info
->chain_pos
;
342 fields
[2].num_bits
= 32;
343 fields
[2].out_value
= NULL
;
344 fields
[2].out_mask
= NULL
;
345 fields
[2].in_value
= NULL
;
346 fields
[2].in_check_value
= NULL
;
347 fields
[2].in_check_mask
= NULL
;
348 fields
[2].in_handler
= NULL
;
349 fields
[2].in_handler_priv
= NULL
;
351 jtag_add_dr_scan(3, fields
, -1);
353 jtag_add_runtest(0, -1);
355 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
357 jtag_execute_queue();
361 DEBUG("in: 0x%8.8x", *in
);
365 ERROR("BUG: called with in == NULL");
373 void arm9tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
375 /* get pointers to arch-specific information */
376 armv4_5_common_t
*armv4_5
= target
->arch_info
;
377 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
378 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
380 /* save r0 before using it and put system in ARM state
381 * to allow common handling of ARM and THUMB debugging */
383 /* fetch STR r0, [r0] */
384 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
385 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
386 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
387 /* STR r0, [r0] in Memory */
388 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, r0
, 0);
390 /* MOV r0, r15 fetched, STR in Decode */
391 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), 0, NULL
, 0);
392 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
393 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
394 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
395 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
396 /* nothing fetched, STR r0, [r0] in Memory */
397 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, pc
, 0);
399 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
400 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
402 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
404 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
405 /* LDR in Memory (to account for interlock) */
406 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
409 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), 0, NULL
, 0);
410 /* NOP fetched, BX in Decode, MOV in Execute */
411 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
412 /* NOP fetched, BX in Execute (1) */
413 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
415 jtag_execute_queue();
417 /* fix program counter:
418 * MOV r0, r15 was the 5th instruction (+8)
419 * reading PC in Thumb state gives address of instruction + 4
424 void arm9tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
427 /* get pointers to arch-specific information */
428 armv4_5_common_t
*armv4_5
= target
->arch_info
;
429 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
430 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
432 /* STMIA r0-15, [r0] at debug speed
433 * register values will start to appear on 4th DCLK
435 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
437 /* fetch NOP, STM in DECODE stage */
438 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
439 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
440 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
442 for (i
= 0; i
<= 15; i
++)
445 /* nothing fetched, STM in MEMORY (i'th cycle) */
446 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
451 void arm9tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
454 /* get pointers to arch-specific information */
455 armv4_5_common_t
*armv4_5
= target
->arch_info
;
456 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
457 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
458 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
459 u32
*buf_u32
= buffer
;
460 u16
*buf_u16
= buffer
;
463 /* STMIA r0-15, [r0] at debug speed
464 * register values will start to appear on 4th DCLK
466 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
468 /* fetch NOP, STM in DECODE stage */
469 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
470 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
471 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
473 for (i
= 0; i
<= 15; i
++)
476 /* nothing fetched, STM in MEMORY (i'th cycle) */
480 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
483 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
486 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
493 void arm9tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
495 /* get pointers to arch-specific information */
496 armv4_5_common_t
*armv4_5
= target
->arch_info
;
497 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
498 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
501 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
502 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
503 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
504 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
505 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
508 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
509 /* fetch NOP, STR in DECODE stage */
510 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
511 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
512 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
513 /* nothing fetched, STR in MEMORY */
514 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
518 void arm9tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
520 /* get pointers to arch-specific information */
521 armv4_5_common_t
*armv4_5
= target
->arch_info
;
522 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
523 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
525 DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
528 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
529 /* MSR2 fetched, MSR1 in DECODE */
530 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
531 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
532 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
533 /* nothing fetched, MSR1 in EXECUTE (2) */
534 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
535 /* nothing fetched, MSR1 in EXECUTE (3) */
536 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
537 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
538 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
539 /* nothing fetched, MSR2 in EXECUTE (2) */
540 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
541 /* nothing fetched, MSR2 in EXECUTE (3) */
542 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
543 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
544 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
545 /* nothing fetched, MSR3 in EXECUTE (2) */
546 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
547 /* nothing fetched, MSR3 in EXECUTE (3) */
548 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
549 /* NOP fetched, MSR4 in EXECUTE (1) */
550 /* last MSR writes flags, which takes only one cycle */
551 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
554 void arm9tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
556 /* get pointers to arch-specific information */
557 armv4_5_common_t
*armv4_5
= target
->arch_info
;
558 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
559 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
561 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
564 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
565 /* NOP fetched, MSR in DECODE */
566 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
567 /* NOP fetched, MSR in EXECUTE (1) */
568 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
570 /* rot == 4 writes flags, which takes only one cycle */
573 /* nothing fetched, MSR in EXECUTE (2) */
574 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
575 /* nothing fetched, MSR in EXECUTE (3) */
576 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
580 void arm9tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
583 /* get pointers to arch-specific information */
584 armv4_5_common_t
*armv4_5
= target
->arch_info
;
585 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
586 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
588 /* LDMIA r0-15, [r0] at debug speed
589 * register values will start to appear on 4th DCLK
591 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
593 /* fetch NOP, LDM in DECODE stage */
594 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
595 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
596 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
598 for (i
= 0; i
<= 15; i
++)
601 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
602 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
604 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
608 void arm9tdmi_load_word_regs(target_t
*target
, u32 mask
)
610 /* get pointers to arch-specific information */
611 armv4_5_common_t
*armv4_5
= target
->arch_info
;
612 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
613 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
615 /* put system-speed load-multiple into the pipeline */
616 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), 0, NULL
, 0);
617 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
621 void arm9tdmi_load_hword_reg(target_t
*target
, int num
)
623 /* get pointers to arch-specific information */
624 armv4_5_common_t
*armv4_5
= target
->arch_info
;
625 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
626 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
628 /* put system-speed load half-word into the pipeline */
629 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), 0, NULL
, 0);
630 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
633 void arm9tdmi_load_byte_reg(target_t
*target
, int num
)
635 /* get pointers to arch-specific information */
636 armv4_5_common_t
*armv4_5
= target
->arch_info
;
637 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
638 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
640 /* put system-speed load byte into the pipeline */
641 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), 0, NULL
, 0);
642 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
646 void arm9tdmi_store_word_regs(target_t
*target
, u32 mask
)
648 /* get pointers to arch-specific information */
649 armv4_5_common_t
*armv4_5
= target
->arch_info
;
650 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
651 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
653 /* put system-speed store-multiple into the pipeline */
654 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), 0, NULL
, 0);
655 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
659 void arm9tdmi_store_hword_reg(target_t
*target
, int num
)
661 /* get pointers to arch-specific information */
662 armv4_5_common_t
*armv4_5
= target
->arch_info
;
663 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
664 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
666 /* put system-speed store half-word into the pipeline */
667 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), 0, NULL
, 0);
668 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
672 void arm9tdmi_store_byte_reg(target_t
*target
, int num
)
674 /* get pointers to arch-specific information */
675 armv4_5_common_t
*armv4_5
= target
->arch_info
;
676 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
677 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
679 /* put system-speed store byte into the pipeline */
680 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), 0, NULL
, 0);
681 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
685 void arm9tdmi_write_pc(target_t
*target
, u32 pc
)
687 /* get pointers to arch-specific information */
688 armv4_5_common_t
*armv4_5
= target
->arch_info
;
689 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
690 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
692 /* LDMIA r0-15, [r0] at debug speed
693 * register values will start to appear on 4th DCLK
695 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
697 /* fetch NOP, LDM in DECODE stage */
698 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
699 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
700 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
701 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
702 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
703 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
704 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
705 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
706 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
707 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
708 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
712 void arm9tdmi_branch_resume(target_t
*target
)
714 /* get pointers to arch-specific information */
715 armv4_5_common_t
*armv4_5
= target
->arch_info
;
716 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
717 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
719 arm9tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffc, 0), 0, NULL
, 0);
720 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
724 void arm9tdmi_branch_resume_thumb(target_t
*target
)
728 /* get pointers to arch-specific information */
729 armv4_5_common_t
*armv4_5
= target
->arch_info
;
730 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
731 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
732 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
734 /* LDMIA r0-15, [r0] at debug speed
735 * register values will start to appear on 4th DCLK
737 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL
, 0);
739 /* fetch NOP, LDM in DECODE stage */
740 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
741 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
742 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
743 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
744 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
745 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
746 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
748 /* Branch and eXchange */
749 arm9tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), 0, NULL
, 0);
751 embeddedice_read_reg(dbg_stat
);
753 /* fetch NOP, BX in DECODE stage */
754 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
756 embeddedice_read_reg(dbg_stat
);
758 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
759 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
761 /* target is now in Thumb state */
762 embeddedice_read_reg(dbg_stat
);
764 /* load r0 value, MOV_IM in Decode*/
765 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
766 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
767 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
768 /* fetch NOP, LDR in Execute */
769 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
770 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
771 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
772 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
773 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
775 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
776 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
778 embeddedice_read_reg(dbg_stat
);
780 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f7), 0, NULL
, 1);
781 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
785 void arm9tdmi_enable_single_step(target_t
*target
)
787 /* get pointers to arch-specific information */
788 armv4_5_common_t
*armv4_5
= target
->arch_info
;
789 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
790 arm9tdmi_common_t
*arm9
= arm7_9
->arch_info
;
792 if (arm7_9
->has_single_step
)
794 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 1);
795 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
799 arm7_9_enable_eice_step(target
);
803 void arm9tdmi_disable_single_step(target_t
*target
)
805 /* get pointers to arch-specific information */
806 armv4_5_common_t
*armv4_5
= target
->arch_info
;
807 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
808 arm9tdmi_common_t
*arm9
= arm7_9
->arch_info
;
810 if (arm7_9
->has_single_step
)
812 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 0);
813 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
817 arm7_9_disable_eice_step(target
);
821 void arm9tdmi_build_reg_cache(target_t
*target
)
823 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
824 /* get pointers to arch-specific information */
825 armv4_5_common_t
*armv4_5
= target
->arch_info
;
826 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
827 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
829 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
830 armv4_5
->core_cache
= (*cache_p
);
832 /* one extra register (vector catch) */
833 (*cache_p
)->next
= embeddedice_build_reg_cache(target
, arm7_9
);
834 arm7_9
->eice_cache
= (*cache_p
)->next
;
838 (*cache_p
)->next
->next
= etm_build_reg_cache(target
, jtag_info
, 0);
839 arm7_9
->etm_cache
= (*cache_p
)->next
->next
;
843 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
846 arm9tdmi_build_reg_cache(target
);
858 int arm9tdmi_init_arch_info(target_t
*target
, arm9tdmi_common_t
*arm9tdmi
, int chain_pos
, char *variant
)
860 armv4_5_common_t
*armv4_5
;
861 arm7_9_common_t
*arm7_9
;
863 arm7_9
= &arm9tdmi
->arm7_9_common
;
864 armv4_5
= &arm7_9
->armv4_5_common
;
866 /* prepare JTAG information for the new target */
867 arm7_9
->jtag_info
.chain_pos
= chain_pos
;
868 arm7_9
->jtag_info
.scann_size
= 5;
870 /* register arch-specific functions */
871 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
872 arm7_9
->change_to_arm
= arm9tdmi_change_to_arm
;
873 arm7_9
->read_core_regs
= arm9tdmi_read_core_regs
;
874 arm7_9
->read_core_regs_target_buffer
= arm9tdmi_read_core_regs_target_buffer
;
875 arm7_9
->read_xpsr
= arm9tdmi_read_xpsr
;
877 arm7_9
->write_xpsr
= arm9tdmi_write_xpsr
;
878 arm7_9
->write_xpsr_im8
= arm9tdmi_write_xpsr_im8
;
879 arm7_9
->write_core_regs
= arm9tdmi_write_core_regs
;
881 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
882 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
883 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
885 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
886 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
887 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
889 arm7_9
->write_pc
= arm9tdmi_write_pc
;
890 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
891 arm7_9
->branch_resume_thumb
= arm9tdmi_branch_resume_thumb
;
893 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
894 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
896 arm7_9
->pre_debug_entry
= NULL
;
897 arm7_9
->post_debug_entry
= NULL
;
899 arm7_9
->pre_restore_context
= NULL
;
900 arm7_9
->post_restore_context
= NULL
;
902 /* initialize arch-specific breakpoint handling */
903 buf_set_u32((u8
*)(&arm7_9
->arm_bkpt
), 0, 32, 0xdeeedeee);
904 buf_set_u32((u8
*)(&arm7_9
->thumb_bkpt
), 0, 16, 0xdeee);
906 arm7_9
->sw_bkpts_use_wp
= 1;
907 arm7_9
->sw_bkpts_enabled
= 0;
908 arm7_9
->dbgreq_adjust_pc
= 3;
909 arm7_9
->arch_info
= arm9tdmi
;
911 arm9tdmi
->common_magic
= ARM9TDMI_COMMON_MAGIC
;
912 arm9tdmi
->arch_info
= NULL
;
916 arm9tdmi
->variant
= strdup(variant
);
920 arm9tdmi
->variant
= strdup("");
923 arm7_9_init_arch_info(target
, arm7_9
);
925 /* override use of DBGRQ, this is safe on ARM9TDMI */
926 arm7_9
->use_dbgrq
= 1;
928 /* all ARM9s have the vector catch register */
929 arm7_9
->has_vector_catch
= 1;
934 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
935 int arm9tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
938 char *variant
= NULL
;
939 arm9tdmi_common_t
*arm9tdmi
= malloc(sizeof(arm9tdmi_common_t
));
943 ERROR("'target arm9tdmi' requires at least one additional argument");
947 chain_pos
= strtoul(args
[3], NULL
, 0);
952 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
957 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
)
961 retval
= arm7_9_register_commands(cmd_ctx
);
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