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- Set up ICE registers after TRST
[openocd.git] / src / target / arm9tdmi.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm9tdmi.h"
25
26 #include "arm7_9_common.h"
27 #include "register.h"
28 #include "target.h"
29 #include "armv4_5.h"
30 #include "embeddedice.h"
31 #include "etm.h"
32 #include "etb.h"
33 #include "log.h"
34 #include "jtag.h"
35 #include "arm_jtag.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 #if 0
41 #define _DEBUG_INSTRUCTION_EXECUTION_
42 #endif
43
44 /* cli handling */
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm9tdmi_quit();
52
53 target_type_t arm9tdmi_target =
54 {
55 .name = "arm9tdmi",
56
57 .poll = arm7_9_poll,
58 .arch_state = armv4_5_arch_state,
59
60 .target_request_data = arm7_9_target_request_data,
61
62 .halt = arm7_9_halt,
63 .resume = arm7_9_resume,
64 .step = arm7_9_step,
65
66 .assert_reset = arm7_9_assert_reset,
67 .deassert_reset = arm7_9_deassert_reset,
68 .soft_reset_halt = arm7_9_soft_reset_halt,
69
70 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
71
72 .read_memory = arm7_9_read_memory,
73 .write_memory = arm7_9_write_memory,
74 .bulk_write_memory = arm7_9_bulk_write_memory,
75 .checksum_memory = arm7_9_checksum_memory,
76
77 .run_algorithm = armv4_5_run_algorithm,
78
79 .add_breakpoint = arm7_9_add_breakpoint,
80 .remove_breakpoint = arm7_9_remove_breakpoint,
81 .add_watchpoint = arm7_9_add_watchpoint,
82 .remove_watchpoint = arm7_9_remove_watchpoint,
83
84 .register_commands = arm9tdmi_register_commands,
85 .target_command = arm9tdmi_target_command,
86 .init_target = arm9tdmi_init_target,
87 .examine = arm9tdmi_examine,
88 .quit = arm9tdmi_quit
89 };
90
91 arm9tdmi_vector_t arm9tdmi_vectors[] =
92 {
93 {"reset", ARM9TDMI_RESET_VECTOR},
94 {"undef", ARM9TDMI_UNDEF_VECTOR},
95 {"swi", ARM9TDMI_SWI_VECTOR},
96 {"pabt", ARM9TDMI_PABT_VECTOR},
97 {"dabt", ARM9TDMI_DABT_VECTOR},
98 {"reserved", ARM9TDMI_RESERVED_VECTOR},
99 {"irq", ARM9TDMI_IRQ_VECTOR},
100 {"fiq", ARM9TDMI_FIQ_VECTOR},
101 {0, 0},
102 };
103
104 int arm9tdmi_examine_debug_reason(target_t *target)
105 {
106 /* get pointers to arch-specific information */
107 armv4_5_common_t *armv4_5 = target->arch_info;
108 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
109
110 /* only check the debug reason if we don't know it already */
111 if ((target->debug_reason != DBG_REASON_DBGRQ)
112 && (target->debug_reason != DBG_REASON_SINGLESTEP))
113 {
114 scan_field_t fields[3];
115 u8 databus[4];
116 u8 instructionbus[4];
117 u8 debug_reason;
118
119 jtag_add_end_state(TAP_PD);
120
121 fields[0].device = arm7_9->jtag_info.chain_pos;
122 fields[0].num_bits = 32;
123 fields[0].out_value = NULL;
124 fields[0].out_mask = NULL;
125 fields[0].in_value = databus;
126 fields[0].in_check_value = NULL;
127 fields[0].in_check_mask = NULL;
128 fields[0].in_handler = NULL;
129 fields[0].in_handler_priv = NULL;
130
131 fields[1].device = arm7_9->jtag_info.chain_pos;
132 fields[1].num_bits = 3;
133 fields[1].out_value = NULL;
134 fields[1].out_mask = NULL;
135 fields[1].in_value = &debug_reason;
136 fields[1].in_check_value = NULL;
137 fields[1].in_check_mask = NULL;
138 fields[1].in_handler = NULL;
139 fields[1].in_handler_priv = NULL;
140
141 fields[2].device = arm7_9->jtag_info.chain_pos;
142 fields[2].num_bits = 32;
143 fields[2].out_value = NULL;
144 fields[2].out_mask = NULL;
145 fields[2].in_value = instructionbus;
146 fields[2].in_check_value = NULL;
147 fields[2].in_check_mask = NULL;
148 fields[2].in_handler = NULL;
149 fields[2].in_handler_priv = NULL;
150
151 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
152 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
153
154 jtag_add_dr_scan(3, fields, TAP_PD);
155 jtag_execute_queue();
156
157 fields[0].in_value = NULL;
158 fields[0].out_value = databus;
159 fields[1].in_value = NULL;
160 fields[1].out_value = &debug_reason;
161 fields[2].in_value = NULL;
162 fields[2].out_value = instructionbus;
163
164 jtag_add_dr_scan(3, fields, TAP_PD);
165
166 if (debug_reason & 0x4)
167 if (debug_reason & 0x2)
168 target->debug_reason = DBG_REASON_WPTANDBKPT;
169 else
170 target->debug_reason = DBG_REASON_WATCHPOINT;
171 else
172 target->debug_reason = DBG_REASON_BREAKPOINT;
173 }
174
175 return ERROR_OK;
176 }
177
178 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
179 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
180 {
181 scan_field_t fields[3];
182 u8 out_buf[4];
183 u8 instr_buf[4];
184 u8 sysspeed_buf = 0x0;
185
186 /* prepare buffer */
187 buf_set_u32(out_buf, 0, 32, out);
188
189 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
190
191 if (sysspeed)
192 buf_set_u32(&sysspeed_buf, 2, 1, 1);
193
194 jtag_add_end_state(TAP_PD);
195 arm_jtag_scann(jtag_info, 0x1);
196
197 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
198
199 fields[0].device = jtag_info->chain_pos;
200 fields[0].num_bits = 32;
201 fields[0].out_value = out_buf;
202 fields[0].out_mask = NULL;
203 fields[0].in_value = NULL;
204 if (in)
205 {
206 fields[0].in_handler = arm_jtag_buf_to_u32;
207 fields[0].in_handler_priv = in;
208 }
209 else
210 {
211 fields[0].in_handler = NULL;
212 fields[0].in_handler_priv = NULL;
213 }
214 fields[0].in_check_value = NULL;
215 fields[0].in_check_mask = NULL;
216
217 fields[1].device = jtag_info->chain_pos;
218 fields[1].num_bits = 3;
219 fields[1].out_value = &sysspeed_buf;
220 fields[1].out_mask = NULL;
221 fields[1].in_value = NULL;
222 fields[1].in_check_value = NULL;
223 fields[1].in_check_mask = NULL;
224 fields[1].in_handler = NULL;
225 fields[1].in_handler_priv = NULL;
226
227 fields[2].device = jtag_info->chain_pos;
228 fields[2].num_bits = 32;
229 fields[2].out_value = instr_buf;
230 fields[2].out_mask = NULL;
231 fields[2].in_value = NULL;
232 fields[2].in_check_value = NULL;
233 fields[2].in_check_mask = NULL;
234 fields[2].in_handler = NULL;
235 fields[2].in_handler_priv = NULL;
236
237 jtag_add_dr_scan(3, fields, -1);
238
239 jtag_add_runtest(0, -1);
240
241 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
242 {
243 jtag_execute_queue();
244
245 if (in)
246 {
247 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
248 }
249 else
250 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
251 }
252 #endif
253
254 return ERROR_OK;
255 }
256
257 /* just read data (instruction and data-out = don't care) */
258 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
259 {
260 scan_field_t fields[3];
261
262 jtag_add_end_state(TAP_PD);
263 arm_jtag_scann(jtag_info, 0x1);
264
265 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
266
267 fields[0].device = jtag_info->chain_pos;
268 fields[0].num_bits = 32;
269 fields[0].out_value = NULL;
270 fields[0].out_mask = NULL;
271 fields[0].in_value = NULL;
272 fields[0].in_handler = arm_jtag_buf_to_u32;
273 fields[0].in_handler_priv = in;
274 fields[0].in_check_value = NULL;
275 fields[0].in_check_mask = NULL;
276
277 fields[1].device = jtag_info->chain_pos;
278 fields[1].num_bits = 3;
279 fields[1].out_value = NULL;
280 fields[1].out_mask = NULL;
281 fields[1].in_value = NULL;
282 fields[1].in_handler = NULL;
283 fields[1].in_handler_priv = NULL;
284 fields[1].in_check_value = NULL;
285 fields[1].in_check_mask = NULL;
286
287 fields[2].device = jtag_info->chain_pos;
288 fields[2].num_bits = 32;
289 fields[2].out_value = NULL;
290 fields[2].out_mask = NULL;
291 fields[2].in_value = NULL;
292 fields[2].in_check_value = NULL;
293 fields[2].in_check_mask = NULL;
294 fields[2].in_handler = NULL;
295 fields[2].in_handler_priv = NULL;
296
297 jtag_add_dr_scan(3, fields, -1);
298
299 jtag_add_runtest(0, -1);
300
301 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
302 {
303 jtag_execute_queue();
304
305 if (in)
306 {
307 LOG_DEBUG("in: 0x%8.8x", *in);
308 }
309 else
310 {
311 LOG_ERROR("BUG: called with in == NULL");
312 }
313 }
314 #endif
315
316 return ERROR_OK;
317 }
318
319 /* clock the target, and read the databus
320 * the *in pointer points to a buffer where elements of 'size' bytes
321 * are stored in big (be==1) or little (be==0) endianness
322 */
323 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
324 {
325 scan_field_t fields[3];
326
327 jtag_add_end_state(TAP_PD);
328 arm_jtag_scann(jtag_info, 0x1);
329
330 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
331
332 fields[0].device = jtag_info->chain_pos;
333 fields[0].num_bits = 32;
334 fields[0].out_value = NULL;
335 fields[0].out_mask = NULL;
336 fields[0].in_value = NULL;
337 switch (size)
338 {
339 case 4:
340 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
341 break;
342 case 2:
343 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
344 break;
345 case 1:
346 fields[0].in_handler = arm_jtag_buf_to_8;
347 break;
348 }
349 fields[0].in_handler_priv = in;
350 fields[0].in_check_value = NULL;
351 fields[0].in_check_mask = NULL;
352
353 fields[1].device = jtag_info->chain_pos;
354 fields[1].num_bits = 3;
355 fields[1].out_value = NULL;
356 fields[1].out_mask = NULL;
357 fields[1].in_value = NULL;
358 fields[1].in_handler = NULL;
359 fields[1].in_handler_priv = NULL;
360 fields[1].in_check_value = NULL;
361 fields[1].in_check_mask = NULL;
362
363 fields[2].device = jtag_info->chain_pos;
364 fields[2].num_bits = 32;
365 fields[2].out_value = NULL;
366 fields[2].out_mask = NULL;
367 fields[2].in_value = NULL;
368 fields[2].in_check_value = NULL;
369 fields[2].in_check_mask = NULL;
370 fields[2].in_handler = NULL;
371 fields[2].in_handler_priv = NULL;
372
373 jtag_add_dr_scan(3, fields, -1);
374
375 jtag_add_runtest(0, -1);
376
377 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
378 {
379 jtag_execute_queue();
380
381 if (in)
382 {
383 LOG_DEBUG("in: 0x%8.8x", *in);
384 }
385 else
386 {
387 LOG_ERROR("BUG: called with in == NULL");
388 }
389 }
390 #endif
391
392 return ERROR_OK;
393 }
394
395 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
396 {
397 /* get pointers to arch-specific information */
398 armv4_5_common_t *armv4_5 = target->arch_info;
399 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
400 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
401
402 /* save r0 before using it and put system in ARM state
403 * to allow common handling of ARM and THUMB debugging */
404
405 /* fetch STR r0, [r0] */
406 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
407 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
408 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
409 /* STR r0, [r0] in Memory */
410 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
411
412 /* MOV r0, r15 fetched, STR in Decode */
413 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
414 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
415 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
417 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
418 /* nothing fetched, STR r0, [r0] in Memory */
419 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
420
421 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
422 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
423 /* LDR in Decode */
424 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
425 /* LDR in Execute */
426 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
427 /* LDR in Memory (to account for interlock) */
428 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
429
430 /* fetch BX */
431 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
432 /* NOP fetched, BX in Decode, MOV in Execute */
433 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
434 /* NOP fetched, BX in Execute (1) */
435 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
436
437 jtag_execute_queue();
438
439 /* fix program counter:
440 * MOV r0, r15 was the 5th instruction (+8)
441 * reading PC in Thumb state gives address of instruction + 4
442 */
443 *pc -= 0xc;
444 }
445
446 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
447 {
448 int i;
449 /* get pointers to arch-specific information */
450 armv4_5_common_t *armv4_5 = target->arch_info;
451 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
452 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
453
454 /* STMIA r0-15, [r0] at debug speed
455 * register values will start to appear on 4th DCLK
456 */
457 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
458
459 /* fetch NOP, STM in DECODE stage */
460 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
461 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
462 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
463
464 for (i = 0; i <= 15; i++)
465 {
466 if (mask & (1 << i))
467 /* nothing fetched, STM in MEMORY (i'th cycle) */
468 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
469 }
470
471 }
472
473 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
474 {
475 int i;
476 /* get pointers to arch-specific information */
477 armv4_5_common_t *armv4_5 = target->arch_info;
478 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
479 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
480 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
481 u32 *buf_u32 = buffer;
482 u16 *buf_u16 = buffer;
483 u8 *buf_u8 = buffer;
484
485 /* STMIA r0-15, [r0] at debug speed
486 * register values will start to appear on 4th DCLK
487 */
488 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
489
490 /* fetch NOP, STM in DECODE stage */
491 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
492 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
493 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
494
495 for (i = 0; i <= 15; i++)
496 {
497 if (mask & (1 << i))
498 /* nothing fetched, STM in MEMORY (i'th cycle) */
499 switch (size)
500 {
501 case 4:
502 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
503 break;
504 case 2:
505 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
506 break;
507 case 1:
508 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
509 break;
510 }
511 }
512
513 }
514
515 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
516 {
517 /* get pointers to arch-specific information */
518 armv4_5_common_t *armv4_5 = target->arch_info;
519 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
520 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
521
522 /* MRS r0, cpsr */
523 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
524 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
525 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
526 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
527 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
528
529 /* STR r0, [r15] */
530 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
531 /* fetch NOP, STR in DECODE stage */
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
533 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
534 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
535 /* nothing fetched, STR in MEMORY */
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
537
538 }
539
540 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
541 {
542 /* get pointers to arch-specific information */
543 armv4_5_common_t *armv4_5 = target->arch_info;
544 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
545 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
546
547 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
548
549 /* MSR1 fetched */
550 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
551 /* MSR2 fetched, MSR1 in DECODE */
552 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
553 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
554 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
555 /* nothing fetched, MSR1 in EXECUTE (2) */
556 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
557 /* nothing fetched, MSR1 in EXECUTE (3) */
558 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
559 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
560 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
561 /* nothing fetched, MSR2 in EXECUTE (2) */
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
563 /* nothing fetched, MSR2 in EXECUTE (3) */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
565 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
567 /* nothing fetched, MSR3 in EXECUTE (2) */
568 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
569 /* nothing fetched, MSR3 in EXECUTE (3) */
570 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
571 /* NOP fetched, MSR4 in EXECUTE (1) */
572 /* last MSR writes flags, which takes only one cycle */
573 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
574 }
575
576 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
577 {
578 /* get pointers to arch-specific information */
579 armv4_5_common_t *armv4_5 = target->arch_info;
580 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
581 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
582
583 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
584
585 /* MSR fetched */
586 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
587 /* NOP fetched, MSR in DECODE */
588 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
589 /* NOP fetched, MSR in EXECUTE (1) */
590 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
591
592 /* rot == 4 writes flags, which takes only one cycle */
593 if (rot != 4)
594 {
595 /* nothing fetched, MSR in EXECUTE (2) */
596 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
597 /* nothing fetched, MSR in EXECUTE (3) */
598 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
599 }
600 }
601
602 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
603 {
604 int i;
605 /* get pointers to arch-specific information */
606 armv4_5_common_t *armv4_5 = target->arch_info;
607 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
608 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
609
610 /* LDMIA r0-15, [r0] at debug speed
611 * register values will start to appear on 4th DCLK
612 */
613 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
614
615 /* fetch NOP, LDM in DECODE stage */
616 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
617 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
618 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
619
620 for (i = 0; i <= 15; i++)
621 {
622 if (mask & (1 << i))
623 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
624 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
625 }
626 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
627
628 }
629
630 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
631 {
632 /* get pointers to arch-specific information */
633 armv4_5_common_t *armv4_5 = target->arch_info;
634 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
635 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
636
637 /* put system-speed load-multiple into the pipeline */
638 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
639 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
640
641 }
642
643 void arm9tdmi_load_hword_reg(target_t *target, int num)
644 {
645 /* get pointers to arch-specific information */
646 armv4_5_common_t *armv4_5 = target->arch_info;
647 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
648 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
649
650 /* put system-speed load half-word into the pipeline */
651 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
652 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
653 }
654
655 void arm9tdmi_load_byte_reg(target_t *target, int num)
656 {
657 /* get pointers to arch-specific information */
658 armv4_5_common_t *armv4_5 = target->arch_info;
659 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
660 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
661
662 /* put system-speed load byte into the pipeline */
663 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
664 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
665
666 }
667
668 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
669 {
670 /* get pointers to arch-specific information */
671 armv4_5_common_t *armv4_5 = target->arch_info;
672 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
673 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
674
675 /* put system-speed store-multiple into the pipeline */
676 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
677 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
678
679 }
680
681 void arm9tdmi_store_hword_reg(target_t *target, int num)
682 {
683 /* get pointers to arch-specific information */
684 armv4_5_common_t *armv4_5 = target->arch_info;
685 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
686 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
687
688 /* put system-speed store half-word into the pipeline */
689 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
690 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
691
692 }
693
694 void arm9tdmi_store_byte_reg(target_t *target, int num)
695 {
696 /* get pointers to arch-specific information */
697 armv4_5_common_t *armv4_5 = target->arch_info;
698 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
699 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
700
701 /* put system-speed store byte into the pipeline */
702 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
703 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
704
705 }
706
707 void arm9tdmi_write_pc(target_t *target, u32 pc)
708 {
709 /* get pointers to arch-specific information */
710 armv4_5_common_t *armv4_5 = target->arch_info;
711 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
712 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
713
714 /* LDMIA r0-15, [r0] at debug speed
715 * register values will start to appear on 4th DCLK
716 */
717 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
718
719 /* fetch NOP, LDM in DECODE stage */
720 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
721 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
722 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
723 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
724 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
725 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
726 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
727 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
728 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
729 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
731
732 }
733
734 void arm9tdmi_branch_resume(target_t *target)
735 {
736 /* get pointers to arch-specific information */
737 armv4_5_common_t *armv4_5 = target->arch_info;
738 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
739 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
740
741 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
742 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
743
744 }
745
746 void arm9tdmi_branch_resume_thumb(target_t *target)
747 {
748 LOG_DEBUG("-");
749
750 /* get pointers to arch-specific information */
751 armv4_5_common_t *armv4_5 = target->arch_info;
752 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
753 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
754 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
755
756 /* LDMIA r0-15, [r0] at debug speed
757 * register values will start to appear on 4th DCLK
758 */
759 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
760
761 /* fetch NOP, LDM in DECODE stage */
762 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
763 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
764 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
765 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
767 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
769
770 /* Branch and eXchange */
771 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
772
773 embeddedice_read_reg(dbg_stat);
774
775 /* fetch NOP, BX in DECODE stage */
776 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
777
778 embeddedice_read_reg(dbg_stat);
779
780 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
781 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
782
783 /* target is now in Thumb state */
784 embeddedice_read_reg(dbg_stat);
785
786 /* load r0 value, MOV_IM in Decode*/
787 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
788 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
789 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
790 /* fetch NOP, LDR in Execute */
791 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
792 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
793 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
794 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
795 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
796
797 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
798 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
799
800 embeddedice_read_reg(dbg_stat);
801
802 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
803 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
804
805 }
806
807 void arm9tdmi_enable_single_step(target_t *target)
808 {
809 /* get pointers to arch-specific information */
810 armv4_5_common_t *armv4_5 = target->arch_info;
811 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
812
813 if (arm7_9->has_single_step)
814 {
815 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
816 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
817 }
818 else
819 {
820 arm7_9_enable_eice_step(target);
821 }
822 }
823
824 void arm9tdmi_disable_single_step(target_t *target)
825 {
826 /* get pointers to arch-specific information */
827 armv4_5_common_t *armv4_5 = target->arch_info;
828 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
829
830 if (arm7_9->has_single_step)
831 {
832 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
833 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
834 }
835 else
836 {
837 arm7_9_disable_eice_step(target);
838 }
839 }
840
841 void arm9tdmi_build_reg_cache(target_t *target)
842 {
843 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
844 /* get pointers to arch-specific information */
845 armv4_5_common_t *armv4_5 = target->arch_info;
846
847 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
848 armv4_5->core_cache = (*cache_p);
849 }
850
851
852 int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target)
853 {
854 /* get pointers to arch-specific information */
855 int retval;
856 armv4_5_common_t *armv4_5 = target->arch_info;
857 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
858 if (!target->type->examined)
859 {
860 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
861 reg_cache_t *t;
862 /* one extra register (vector catch) */
863 t=embeddedice_build_reg_cache(target, arm7_9);
864 if (t==NULL)
865 return ERROR_FAIL;
866 (*cache_p) = t;
867 arm7_9->eice_cache = (*cache_p);
868
869 if (arm7_9->etm_ctx)
870 {
871 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
872 (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
873 arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
874 }
875 target->type->examined = 1;
876 }
877 if ((retval=embeddedice_setup(target))!=ERROR_OK)
878 return retval;
879 if (arm7_9->etm_ctx)
880 {
881 if ((retval=etm_setup(target))!=ERROR_OK)
882 return retval;
883 }
884 return ERROR_OK;
885 }
886
887 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
888 {
889
890 arm9tdmi_build_reg_cache(target);
891
892 return ERROR_OK;
893
894 }
895
896 int arm9tdmi_quit()
897 {
898
899 return ERROR_OK;
900 }
901
902 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
903 {
904 armv4_5_common_t *armv4_5;
905 arm7_9_common_t *arm7_9;
906
907 arm7_9 = &arm9tdmi->arm7_9_common;
908 armv4_5 = &arm7_9->armv4_5_common;
909
910 /* prepare JTAG information for the new target */
911 arm7_9->jtag_info.chain_pos = chain_pos;
912 arm7_9->jtag_info.scann_size = 5;
913
914 /* register arch-specific functions */
915 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
916 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
917 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
918 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
919 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
920
921 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
922 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
923 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
924
925 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
926 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
927 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
928
929 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
930 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
931 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
932
933 arm7_9->write_pc = arm9tdmi_write_pc;
934 arm7_9->branch_resume = arm9tdmi_branch_resume;
935 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
936
937 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
938 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
939
940 arm7_9->pre_debug_entry = NULL;
941 arm7_9->post_debug_entry = NULL;
942
943 arm7_9->pre_restore_context = NULL;
944 arm7_9->post_restore_context = NULL;
945
946 /* initialize arch-specific breakpoint handling */
947 arm7_9->arm_bkpt = 0xdeeedeee;
948 arm7_9->thumb_bkpt = 0xdeee;
949
950 arm7_9->sw_bkpts_use_wp = 1;
951 arm7_9->sw_bkpts_enabled = 0;
952 arm7_9->dbgreq_adjust_pc = 3;
953 arm7_9->arch_info = arm9tdmi;
954
955 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
956 arm9tdmi->arch_info = NULL;
957
958 if (variant)
959 {
960 arm9tdmi->variant = strdup(variant);
961 }
962 else
963 {
964 arm9tdmi->variant = strdup("");
965 }
966
967 arm7_9_init_arch_info(target, arm7_9);
968
969 /* override use of DBGRQ, this is safe on ARM9TDMI */
970 arm7_9->use_dbgrq = 1;
971
972 /* all ARM9s have the vector catch register */
973 arm7_9->has_vector_catch = 1;
974
975 return ERROR_OK;
976 }
977
978 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
979 {
980 armv4_5_common_t *armv4_5 = target->arch_info;
981 arm7_9_common_t *arm7_9;
982 arm9tdmi_common_t *arm9tdmi;
983
984 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
985 {
986 return -1;
987 }
988
989 arm7_9 = armv4_5->arch_info;
990 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
991 {
992 return -1;
993 }
994
995 arm9tdmi = arm7_9->arch_info;
996 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
997 {
998 return -1;
999 }
1000
1001 *armv4_5_p = armv4_5;
1002 *arm7_9_p = arm7_9;
1003 *arm9tdmi_p = arm9tdmi;
1004
1005 return ERROR_OK;
1006 }
1007
1008
1009 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
1010 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1011 {
1012 int chain_pos;
1013 char *variant = NULL;
1014 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
1015 memset(arm9tdmi, 0, sizeof(*arm9tdmi));
1016
1017 if (argc < 4)
1018 {
1019 LOG_ERROR("'target arm9tdmi' requires at least one additional argument");
1020 exit(-1);
1021 }
1022
1023 chain_pos = strtoul(args[3], NULL, 0);
1024
1025 if (argc >= 5)
1026 variant = args[4];
1027
1028 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1029
1030 return ERROR_OK;
1031 }
1032
1033 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1034 {
1035 int retval;
1036
1037 command_t *arm9tdmi_cmd;
1038
1039
1040 retval = arm7_9_register_commands(cmd_ctx);
1041
1042 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1043
1044 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1045
1046
1047 return ERROR_OK;
1048
1049 }
1050
1051 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1052 {
1053 target_t *target = get_current_target(cmd_ctx);
1054 armv4_5_common_t *armv4_5;
1055 arm7_9_common_t *arm7_9;
1056 arm9tdmi_common_t *arm9tdmi;
1057 reg_t *vector_catch;
1058 u32 vector_catch_value;
1059 int i, j;
1060
1061 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1062 {
1063 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1064 return ERROR_OK;
1065 }
1066
1067 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1068
1069 /* read the vector catch register if necessary */
1070 if (!vector_catch->valid)
1071 embeddedice_read_reg(vector_catch);
1072
1073 /* get the current setting */
1074 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1075
1076 if (argc > 0)
1077 {
1078 vector_catch_value = 0x0;
1079 if (strcmp(args[0], "all") == 0)
1080 {
1081 vector_catch_value = 0xdf;
1082 }
1083 else if (strcmp(args[0], "none") == 0)
1084 {
1085 /* do nothing */
1086 }
1087 else
1088 {
1089 for (i = 0; i < argc; i++)
1090 {
1091 /* go through list of vectors */
1092 for(j = 0; arm9tdmi_vectors[j].name; j++)
1093 {
1094 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1095 {
1096 vector_catch_value |= arm9tdmi_vectors[j].value;
1097 break;
1098 }
1099 }
1100
1101 /* complain if vector wasn't found */
1102 if (!arm9tdmi_vectors[j].name)
1103 {
1104 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1105
1106 /* reread current setting */
1107 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1108
1109 break;
1110 }
1111 }
1112 }
1113
1114 /* store new settings */
1115 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1116 embeddedice_store_reg(vector_catch);
1117 }
1118
1119 /* output current settings (skip RESERVED vector) */
1120 for (i = 0; i < 8; i++)
1121 {
1122 if (i != 5)
1123 {
1124 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1125 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1126 }
1127 }
1128
1129 return ERROR_OK;
1130 }
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