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2006290237eda467361c12a66bc1253a65135e94
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
81
82 /*
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
85 */
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
87 {
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
89 }
90
91 /***************************************************************************
92 * *
93 * DP and MEM-AP register access through APACC and DPACC *
94 * *
95 ***************************************************************************/
96
97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
98 {
99 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
100 ap->csw_default;
101
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
106 return retval;
107 ap->csw_value = csw;
108 }
109 return ERROR_OK;
110 }
111
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
113 {
114 if (tar != ap->tar_value ||
115 (ap->csw_value & CSW_ADDRINC_MASK)) {
116 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
117 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
118 if (retval != ERROR_OK)
119 return retval;
120 ap->tar_value = tar;
121 }
122 return ERROR_OK;
123 }
124
125 /**
126 * Queue transactions setting up transfer parameters for the
127 * currently selected MEM-AP.
128 *
129 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
130 * initiate data reads or writes using memory or peripheral addresses.
131 * If the CSW is configured for it, the TAR may be automatically
132 * incremented after each transfer.
133 *
134 * @param ap The MEM-AP.
135 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
136 * matches the cached value, the register is not changed.
137 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
138 * matches the cached address, the register is not changed.
139 *
140 * @return ERROR_OK if the transaction was properly queued, else a fault code.
141 */
142 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
143 {
144 int retval;
145 retval = mem_ap_setup_csw(ap, csw);
146 if (retval != ERROR_OK)
147 return retval;
148 retval = mem_ap_setup_tar(ap, tar);
149 if (retval != ERROR_OK)
150 return retval;
151 return ERROR_OK;
152 }
153
154 /**
155 * Asynchronous (queued) read of a word from memory or a system register.
156 *
157 * @param ap The MEM-AP to access.
158 * @param address Address of the 32-bit word to read; it must be
159 * readable by the currently selected MEM-AP.
160 * @param value points to where the word will be stored when the
161 * transaction queue is flushed (assuming no errors).
162 *
163 * @return ERROR_OK for success. Otherwise a fault code.
164 */
165 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
166 uint32_t *value)
167 {
168 int retval;
169
170 /* Use banked addressing (REG_BDx) to avoid some link traffic
171 * (updating TAR) when reading several consecutive addresses.
172 */
173 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
174 address & 0xFFFFFFF0);
175 if (retval != ERROR_OK)
176 return retval;
177
178 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
179 }
180
181 /**
182 * Synchronous read of a word from memory or a system register.
183 * As a side effect, this flushes any queued transactions.
184 *
185 * @param ap The MEM-AP to access.
186 * @param address Address of the 32-bit word to read; it must be
187 * readable by the currently selected MEM-AP.
188 * @param value points to where the result will be stored.
189 *
190 * @return ERROR_OK for success; *value holds the result.
191 * Otherwise a fault code.
192 */
193 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
194 uint32_t *value)
195 {
196 int retval;
197
198 retval = mem_ap_read_u32(ap, address, value);
199 if (retval != ERROR_OK)
200 return retval;
201
202 return dap_run(ap->dap);
203 }
204
205 /**
206 * Asynchronous (queued) write of a word to memory or a system register.
207 *
208 * @param ap The MEM-AP to access.
209 * @param address Address to be written; it must be writable by
210 * the currently selected MEM-AP.
211 * @param value Word that will be written to the address when transaction
212 * queue is flushed (assuming no errors).
213 *
214 * @return ERROR_OK for success. Otherwise a fault code.
215 */
216 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
217 uint32_t value)
218 {
219 int retval;
220
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when writing several consecutive addresses.
223 */
224 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
225 address & 0xFFFFFFF0);
226 if (retval != ERROR_OK)
227 return retval;
228
229 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
230 value);
231 }
232
233 /**
234 * Synchronous write of a word to memory or a system register.
235 * As a side effect, this flushes any queued transactions.
236 *
237 * @param ap The MEM-AP to access.
238 * @param address Address to be written; it must be writable by
239 * the currently selected MEM-AP.
240 * @param value Word that will be written.
241 *
242 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
243 */
244 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
245 uint32_t value)
246 {
247 int retval = mem_ap_write_u32(ap, address, value);
248
249 if (retval != ERROR_OK)
250 return retval;
251
252 return dap_run(ap->dap);
253 }
254
255 /**
256 * Synchronous write of a block of memory, using a specific access size.
257 *
258 * @param ap The MEM-AP to access.
259 * @param buffer The data buffer to write. No particular alignment is assumed.
260 * @param size Which access size to use, in bytes. 1, 2 or 4.
261 * @param count The number of writes to do (in size units, not bytes).
262 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
263 * @param addrinc Whether the target address should be increased for each write or not. This
264 * should normally be true, except when writing to e.g. a FIFO.
265 * @return ERROR_OK on success, otherwise an error code.
266 */
267 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
268 uint32_t address, bool addrinc)
269 {
270 struct adiv5_dap *dap = ap->dap;
271 size_t nbytes = size * count;
272 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
273 uint32_t csw_size;
274 uint32_t addr_xor;
275 int retval;
276
277 /* TI BE-32 Quirks mode:
278 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
279 * size write address bytes written in order
280 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
281 * 2 TAR ^ 2 (val >> 8), (val)
282 * 1 TAR ^ 3 (val)
283 * For example, if you attempt to write a single byte to address 0, the processor
284 * will actually write a byte to address 3.
285 *
286 * To make writes of size < 4 work as expected, we xor a value with the address before
287 * setting the TAP, and we set the TAP after every transfer rather then relying on
288 * address increment. */
289
290 if (size == 4) {
291 csw_size = CSW_32BIT;
292 addr_xor = 0;
293 } else if (size == 2) {
294 csw_size = CSW_16BIT;
295 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
296 } else if (size == 1) {
297 csw_size = CSW_8BIT;
298 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
299 } else {
300 return ERROR_TARGET_UNALIGNED_ACCESS;
301 }
302
303 if (ap->unaligned_access_bad && (address % size != 0))
304 return ERROR_TARGET_UNALIGNED_ACCESS;
305
306 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
307 if (retval != ERROR_OK)
308 return retval;
309
310 while (nbytes > 0) {
311 uint32_t this_size = size;
312
313 /* Select packed transfer if possible */
314 if (addrinc && ap->packed_transfers && nbytes >= 4
315 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
316 this_size = 4;
317 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
318 } else {
319 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
320 }
321
322 if (retval != ERROR_OK)
323 break;
324
325 /* How many source bytes each transfer will consume, and their location in the DRW,
326 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
327 uint32_t outvalue = 0;
328 if (dap->ti_be_32_quirks) {
329 switch (this_size) {
330 case 4:
331 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
332 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
333 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
334 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
335 break;
336 case 2:
337 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
338 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
339 break;
340 case 1:
341 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
342 break;
343 }
344 } else {
345 switch (this_size) {
346 case 4:
347 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
348 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
349 /* fallthrough */
350 case 2:
351 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
352 /* fallthrough */
353 case 1:
354 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
355 }
356 }
357
358 nbytes -= this_size;
359
360 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
361 if (retval != ERROR_OK)
362 break;
363
364 /* Rewrite TAR if it wrapped or we're xoring addresses */
365 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
366 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
367 if (retval != ERROR_OK)
368 break;
369 }
370 }
371
372 /* REVISIT: Might want to have a queued version of this function that does not run. */
373 if (retval == ERROR_OK)
374 retval = dap_run(dap);
375
376 if (retval != ERROR_OK) {
377 uint32_t tar;
378 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
379 && dap_run(dap) == ERROR_OK)
380 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
381 else
382 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
383 }
384
385 return retval;
386 }
387
388 /**
389 * Synchronous read of a block of memory, using a specific access size.
390 *
391 * @param ap The MEM-AP to access.
392 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
393 * @param size Which access size to use, in bytes. 1, 2 or 4.
394 * @param count The number of reads to do (in size units, not bytes).
395 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
396 * @param addrinc Whether the target address should be increased after each read or not. This
397 * should normally be true, except when reading from e.g. a FIFO.
398 * @return ERROR_OK on success, otherwise an error code.
399 */
400 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
401 uint32_t adr, bool addrinc)
402 {
403 struct adiv5_dap *dap = ap->dap;
404 size_t nbytes = size * count;
405 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
406 uint32_t csw_size;
407 uint32_t address = adr;
408 int retval;
409
410 /* TI BE-32 Quirks mode:
411 * Reads on big-endian TMS570 behave strangely differently than writes.
412 * They read from the physical address requested, but with DRW byte-reversed.
413 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
414 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
415 * so avoid them. */
416
417 if (size == 4)
418 csw_size = CSW_32BIT;
419 else if (size == 2)
420 csw_size = CSW_16BIT;
421 else if (size == 1)
422 csw_size = CSW_8BIT;
423 else
424 return ERROR_TARGET_UNALIGNED_ACCESS;
425
426 if (ap->unaligned_access_bad && (adr % size != 0))
427 return ERROR_TARGET_UNALIGNED_ACCESS;
428
429 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
430 * over-allocation if packed transfers are going to be used, but determining the real need at
431 * this point would be messy. */
432 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
433 uint32_t *read_ptr = read_buf;
434 if (read_buf == NULL) {
435 LOG_ERROR("Failed to allocate read buffer");
436 return ERROR_FAIL;
437 }
438
439 retval = mem_ap_setup_tar(ap, address);
440 if (retval != ERROR_OK) {
441 free(read_buf);
442 return retval;
443 }
444
445 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
446 * useful bytes it contains, and their location in the word, depends on the type of transfer
447 * and alignment. */
448 while (nbytes > 0) {
449 uint32_t this_size = size;
450
451 /* Select packed transfer if possible */
452 if (addrinc && ap->packed_transfers && nbytes >= 4
453 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
454 this_size = 4;
455 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
456 } else {
457 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
458 }
459 if (retval != ERROR_OK)
460 break;
461
462 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
463 if (retval != ERROR_OK)
464 break;
465
466 nbytes -= this_size;
467 address += this_size;
468
469 /* Rewrite TAR if it wrapped */
470 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
471 retval = mem_ap_setup_tar(ap, address);
472 if (retval != ERROR_OK)
473 break;
474 }
475 }
476
477 if (retval == ERROR_OK)
478 retval = dap_run(dap);
479
480 /* Restore state */
481 address = adr;
482 nbytes = size * count;
483 read_ptr = read_buf;
484
485 /* If something failed, read TAR to find out how much data was successfully read, so we can
486 * at least give the caller what we have. */
487 if (retval != ERROR_OK) {
488 uint32_t tar;
489 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
490 && dap_run(dap) == ERROR_OK) {
491 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
492 if (nbytes > tar - address)
493 nbytes = tar - address;
494 } else {
495 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
496 nbytes = 0;
497 }
498 }
499
500 /* Replay loop to populate caller's buffer from the correct word and byte lane */
501 while (nbytes > 0) {
502 uint32_t this_size = size;
503
504 if (addrinc && ap->packed_transfers && nbytes >= 4
505 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
506 this_size = 4;
507 }
508
509 if (dap->ti_be_32_quirks) {
510 switch (this_size) {
511 case 4:
512 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
513 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
514 /* fallthrough */
515 case 2:
516 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
517 /* fallthrough */
518 case 1:
519 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
520 }
521 } else {
522 switch (this_size) {
523 case 4:
524 *buffer++ = *read_ptr >> 8 * (address++ & 3);
525 *buffer++ = *read_ptr >> 8 * (address++ & 3);
526 /* fallthrough */
527 case 2:
528 *buffer++ = *read_ptr >> 8 * (address++ & 3);
529 /* fallthrough */
530 case 1:
531 *buffer++ = *read_ptr >> 8 * (address++ & 3);
532 }
533 }
534
535 read_ptr++;
536 nbytes -= this_size;
537 }
538
539 free(read_buf);
540 return retval;
541 }
542
543 int mem_ap_read_buf(struct adiv5_ap *ap,
544 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
545 {
546 return mem_ap_read(ap, buffer, size, count, address, true);
547 }
548
549 int mem_ap_write_buf(struct adiv5_ap *ap,
550 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
551 {
552 return mem_ap_write(ap, buffer, size, count, address, true);
553 }
554
555 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
556 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
557 {
558 return mem_ap_read(ap, buffer, size, count, address, false);
559 }
560
561 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
562 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
563 {
564 return mem_ap_write(ap, buffer, size, count, address, false);
565 }
566
567 /*--------------------------------------------------------------------------*/
568
569
570 #define DAP_POWER_DOMAIN_TIMEOUT (10)
571
572 /* FIXME don't import ... just initialize as
573 * part of DAP transport setup
574 */
575 extern const struct dap_ops jtag_dp_ops;
576
577 /*--------------------------------------------------------------------------*/
578
579 /**
580 * Create a new DAP
581 */
582 struct adiv5_dap *dap_init(void)
583 {
584 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
585 int i;
586 /* Set up with safe defaults */
587 for (i = 0; i <= 255; i++) {
588 dap->ap[i].dap = dap;
589 dap->ap[i].ap_num = i;
590 /* memaccess_tck max is 255 */
591 dap->ap[i].memaccess_tck = 255;
592 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
593 dap->ap[i].tar_autoincr_block = (1<<10);
594 }
595 INIT_LIST_HEAD(&dap->cmd_journal);
596 return dap;
597 }
598
599 /**
600 * Initialize a DAP. This sets up the power domains, prepares the DP
601 * for further use and activates overrun checking.
602 *
603 * @param dap The DAP being initialized.
604 */
605 int dap_dp_init(struct adiv5_dap *dap)
606 {
607 int retval;
608
609 LOG_DEBUG(" ");
610 /* JTAG-DP or SWJ-DP, in JTAG mode
611 * ... for SWD mode this is patched as part
612 * of link switchover
613 * FIXME: This should already be setup by the respective transport specific DAP creation.
614 */
615 if (!dap->ops)
616 dap->ops = &jtag_dp_ops;
617
618 dap->select = DP_SELECT_INVALID;
619 dap->last_read = NULL;
620
621 for (size_t i = 0; i < 30; i++) {
622 /* DP initialization */
623
624 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
625 if (retval == ERROR_OK)
626 break;
627 }
628
629 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
630 if (retval != ERROR_OK)
631 return retval;
632
633 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
634 if (retval != ERROR_OK)
635 return retval;
636
637 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
638 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
639 if (retval != ERROR_OK)
640 return retval;
641
642 /* Check that we have debug power domains activated */
643 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
644 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
645 CDBGPWRUPACK, CDBGPWRUPACK,
646 DAP_POWER_DOMAIN_TIMEOUT);
647 if (retval != ERROR_OK)
648 return retval;
649
650 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
651 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
652 CSYSPWRUPACK, CSYSPWRUPACK,
653 DAP_POWER_DOMAIN_TIMEOUT);
654 if (retval != ERROR_OK)
655 return retval;
656
657 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
658 if (retval != ERROR_OK)
659 return retval;
660
661 /* With debug power on we can activate OVERRUN checking */
662 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
663 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
664 if (retval != ERROR_OK)
665 return retval;
666 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
667 if (retval != ERROR_OK)
668 return retval;
669
670 retval = dap_run(dap);
671 if (retval != ERROR_OK)
672 return retval;
673
674 return retval;
675 }
676
677 /**
678 * Initialize a DAP. This sets up the power domains, prepares the DP
679 * for further use, and arranges to use AP #0 for all AP operations
680 * until dap_ap-select() changes that policy.
681 *
682 * @param ap The MEM-AP being initialized.
683 */
684 int mem_ap_init(struct adiv5_ap *ap)
685 {
686 /* check that we support packed transfers */
687 uint32_t csw, cfg;
688 int retval;
689 struct adiv5_dap *dap = ap->dap;
690
691 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
692 if (retval != ERROR_OK)
693 return retval;
694
695 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
696 if (retval != ERROR_OK)
697 return retval;
698
699 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
700 if (retval != ERROR_OK)
701 return retval;
702
703 retval = dap_run(dap);
704 if (retval != ERROR_OK)
705 return retval;
706
707 if (csw & CSW_ADDRINC_PACKED)
708 ap->packed_transfers = true;
709 else
710 ap->packed_transfers = false;
711
712 /* Packed transfers on TI BE-32 processors do not work correctly in
713 * many cases. */
714 if (dap->ti_be_32_quirks)
715 ap->packed_transfers = false;
716
717 LOG_DEBUG("MEM_AP Packed Transfers: %s",
718 ap->packed_transfers ? "enabled" : "disabled");
719
720 /* The ARM ADI spec leaves implementation-defined whether unaligned
721 * memory accesses work, only work partially, or cause a sticky error.
722 * On TI BE-32 processors, reads seem to return garbage in some bytes
723 * and unaligned writes seem to cause a sticky error.
724 * TODO: it would be nice to have a way to detect whether unaligned
725 * operations are supported on other processors. */
726 ap->unaligned_access_bad = dap->ti_be_32_quirks;
727
728 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
729 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
730
731 return ERROR_OK;
732 }
733
734 /* CID interpretation -- see ARM IHI 0029B section 3
735 * and ARM IHI 0031A table 13-3.
736 */
737 static const char *class_description[16] = {
738 "Reserved", "ROM table", "Reserved", "Reserved",
739 "Reserved", "Reserved", "Reserved", "Reserved",
740 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
741 "Reserved", "OptimoDE DESS",
742 "Generic IP component", "PrimeCell or System component"
743 };
744
745 static bool is_dap_cid_ok(uint32_t cid)
746 {
747 return (cid & 0xffff0fff) == 0xb105000d;
748 }
749
750 /*
751 * This function checks the ID for each access port to find the requested Access Port type
752 */
753 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
754 {
755 int ap_num;
756
757 /* Maximum AP number is 255 since the SELECT register is 8 bits */
758 for (ap_num = 0; ap_num <= 255; ap_num++) {
759
760 /* read the IDR register of the Access Port */
761 uint32_t id_val = 0;
762
763 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
764 if (retval != ERROR_OK)
765 return retval;
766
767 retval = dap_run(dap);
768
769 /* IDR bits:
770 * 31-28 : Revision
771 * 27-24 : JEDEC bank (0x4 for ARM)
772 * 23-17 : JEDEC code (0x3B for ARM)
773 * 16-13 : Class (0b1000=Mem-AP)
774 * 12-8 : Reserved
775 * 7-4 : AP Variant (non-zero for JTAG-AP)
776 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
777 */
778
779 /* Reading register for a non-existant AP should not cause an error,
780 * but just to be sure, try to continue searching if an error does happen.
781 */
782 if ((retval == ERROR_OK) && /* Register read success */
783 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
784 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
785
786 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
787 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
788 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
789 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
790 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
791 ap_num, id_val);
792
793 *ap_out = &dap->ap[ap_num];
794 return ERROR_OK;
795 }
796 }
797
798 LOG_DEBUG("No %s found",
799 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
800 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
801 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
802 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
803 return ERROR_FAIL;
804 }
805
806 int dap_get_debugbase(struct adiv5_ap *ap,
807 uint32_t *dbgbase, uint32_t *apid)
808 {
809 struct adiv5_dap *dap = ap->dap;
810 int retval;
811
812 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
813 if (retval != ERROR_OK)
814 return retval;
815 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
816 if (retval != ERROR_OK)
817 return retval;
818 retval = dap_run(dap);
819 if (retval != ERROR_OK)
820 return retval;
821
822 return ERROR_OK;
823 }
824
825 int dap_lookup_cs_component(struct adiv5_ap *ap,
826 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
827 {
828 uint32_t romentry, entry_offset = 0, component_base, devtype;
829 int retval;
830
831 *addr = 0;
832
833 do {
834 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
835 entry_offset, &romentry);
836 if (retval != ERROR_OK)
837 return retval;
838
839 component_base = (dbgbase & 0xFFFFF000)
840 + (romentry & 0xFFFFF000);
841
842 if (romentry & 0x1) {
843 uint32_t c_cid1;
844 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
845 if (retval != ERROR_OK) {
846 LOG_ERROR("Can't read component with base address 0x%" PRIx32
847 ", the corresponding core might be turned off", component_base);
848 return retval;
849 }
850 if (((c_cid1 >> 4) & 0x0f) == 1) {
851 retval = dap_lookup_cs_component(ap, component_base,
852 type, addr, idx);
853 if (retval == ERROR_OK)
854 break;
855 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
856 return retval;
857 }
858
859 retval = mem_ap_read_atomic_u32(ap,
860 (component_base & 0xfffff000) | 0xfcc,
861 &devtype);
862 if (retval != ERROR_OK)
863 return retval;
864 if ((devtype & 0xff) == type) {
865 if (!*idx) {
866 *addr = component_base;
867 break;
868 } else
869 (*idx)--;
870 }
871 }
872 entry_offset += 4;
873 } while (romentry > 0);
874
875 if (!*addr)
876 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
877
878 return ERROR_OK;
879 }
880
881 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
882 {
883 assert((component_base & 0xFFF) == 0);
884 assert(ap != NULL && cid != NULL && pid != NULL);
885
886 uint32_t cid0, cid1, cid2, cid3;
887 uint32_t pid0, pid1, pid2, pid3, pid4;
888 int retval;
889
890 /* IDs are in last 4K section */
891 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
892 if (retval != ERROR_OK)
893 return retval;
894 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
895 if (retval != ERROR_OK)
896 return retval;
897 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
898 if (retval != ERROR_OK)
899 return retval;
900 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
901 if (retval != ERROR_OK)
902 return retval;
903 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
904 if (retval != ERROR_OK)
905 return retval;
906 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
907 if (retval != ERROR_OK)
908 return retval;
909 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
910 if (retval != ERROR_OK)
911 return retval;
912 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
913 if (retval != ERROR_OK)
914 return retval;
915 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
916 if (retval != ERROR_OK)
917 return retval;
918
919 retval = dap_run(ap->dap);
920 if (retval != ERROR_OK)
921 return retval;
922
923 *cid = (cid3 & 0xff) << 24
924 | (cid2 & 0xff) << 16
925 | (cid1 & 0xff) << 8
926 | (cid0 & 0xff);
927 *pid = (uint64_t)(pid4 & 0xff) << 32
928 | (pid3 & 0xff) << 24
929 | (pid2 & 0xff) << 16
930 | (pid1 & 0xff) << 8
931 | (pid0 & 0xff);
932
933 return ERROR_OK;
934 }
935
936 /* The designer identity code is encoded as:
937 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
938 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
939 * a legacy ASCII Identity Code.
940 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
941 * JEP106 is a standard available from jedec.org
942 */
943
944 /* Part number interpretations are from Cortex
945 * core specs, the CoreSight components TRM
946 * (ARM DDI 0314H), CoreSight System Design
947 * Guide (ARM DGI 0012D) and ETM specs; also
948 * from chip observation (e.g. TI SDTI).
949 */
950
951 /* The legacy code only used the part number field to identify CoreSight peripherals.
952 * This meant that the same part number from two different manufacturers looked the same.
953 * It is desirable for all future additions to identify with both part number and JEP106.
954 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
955 */
956
957 #define ANY_ID 0x1000
958
959 #define ARM_ID 0x4BB
960
961 static const struct {
962 uint16_t designer_id;
963 uint16_t part_num;
964 const char *type;
965 const char *full;
966 } dap_partnums[] = {
967 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
968 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
969 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
970 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
971 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
972 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
973 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
974 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
975 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
976 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
977 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
978 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
979 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
980 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
981 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
982 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
983 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
984 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
985 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
986 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
987 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
988 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
989 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
990 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
991 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
992 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
993 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
994 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
995 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
996 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
997 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
998 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
999 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1000 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1001 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1002 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1003 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1004 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1005 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1006 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1007 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1008 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1009 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1010 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1011 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1012 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1013 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1014 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1015 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1016 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1017 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1018 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1019 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1020 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1021 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1022 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1023 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1024 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1025 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1026 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1027 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1028 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1029 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1030 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1031 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1032 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1033 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1034 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1035 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1036 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1037 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1038 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1039 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1040 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1041 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1042 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1043 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1044 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1045 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1046 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1047 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1048 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1049 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1050 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1051 /* legacy comment: 0x113: what? */
1052 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1053 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1054 };
1055
1056 static int dap_rom_display(struct command_context *cmd_ctx,
1057 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1058 {
1059 int retval;
1060 uint64_t pid;
1061 uint32_t cid;
1062 char tabs[16] = "";
1063
1064 if (depth > 16) {
1065 command_print(cmd_ctx, "\tTables too deep");
1066 return ERROR_FAIL;
1067 }
1068
1069 if (depth)
1070 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1071
1072 uint32_t base_addr = dbgbase & 0xFFFFF000;
1073 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1074
1075 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1076 if (retval != ERROR_OK) {
1077 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1078 return ERROR_OK; /* Don't abort recursion */
1079 }
1080
1081 if (!is_dap_cid_ok(cid)) {
1082 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1083 return ERROR_OK; /* Don't abort recursion */
1084 }
1085
1086 /* component may take multiple 4K pages */
1087 uint32_t size = (pid >> 36) & 0xf;
1088 if (size > 0)
1089 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1090
1091 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1092
1093 uint8_t class = (cid >> 12) & 0xf;
1094 uint16_t part_num = pid & 0xfff;
1095 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1096
1097 if (designer_id & 0x80) {
1098 /* JEP106 code */
1099 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1100 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1101 } else {
1102 /* Legacy ASCII ID, clear invalid bits */
1103 designer_id &= 0x7f;
1104 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1105 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1106 }
1107
1108 /* default values to be overwritten upon finding a match */
1109 const char *type = "Unrecognized";
1110 const char *full = "";
1111
1112 /* search dap_partnums[] array for a match */
1113 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1114
1115 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1116 continue;
1117
1118 if (dap_partnums[entry].part_num != part_num)
1119 continue;
1120
1121 type = dap_partnums[entry].type;
1122 full = dap_partnums[entry].full;
1123 break;
1124 }
1125
1126 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1127 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1128
1129 if (class == 1) { /* ROM Table */
1130 uint32_t memtype;
1131 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1132 if (retval != ERROR_OK)
1133 return retval;
1134
1135 if (memtype & 0x01)
1136 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1137 else
1138 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1139
1140 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1141 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1142 uint32_t romentry;
1143 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1144 if (retval != ERROR_OK)
1145 return retval;
1146 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1147 tabs, entry_offset, romentry);
1148 if (romentry & 0x01) {
1149 /* Recurse */
1150 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1151 if (retval != ERROR_OK)
1152 return retval;
1153 } else if (romentry != 0) {
1154 command_print(cmd_ctx, "\t\tComponent not present");
1155 } else {
1156 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1157 break;
1158 }
1159 }
1160 } else if (class == 9) { /* CoreSight component */
1161 const char *major = "Reserved", *subtype = "Reserved";
1162
1163 uint32_t devtype;
1164 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1165 if (retval != ERROR_OK)
1166 return retval;
1167 unsigned minor = (devtype >> 4) & 0x0f;
1168 switch (devtype & 0x0f) {
1169 case 0:
1170 major = "Miscellaneous";
1171 switch (minor) {
1172 case 0:
1173 subtype = "other";
1174 break;
1175 case 4:
1176 subtype = "Validation component";
1177 break;
1178 }
1179 break;
1180 case 1:
1181 major = "Trace Sink";
1182 switch (minor) {
1183 case 0:
1184 subtype = "other";
1185 break;
1186 case 1:
1187 subtype = "Port";
1188 break;
1189 case 2:
1190 subtype = "Buffer";
1191 break;
1192 case 3:
1193 subtype = "Router";
1194 break;
1195 }
1196 break;
1197 case 2:
1198 major = "Trace Link";
1199 switch (minor) {
1200 case 0:
1201 subtype = "other";
1202 break;
1203 case 1:
1204 subtype = "Funnel, router";
1205 break;
1206 case 2:
1207 subtype = "Filter";
1208 break;
1209 case 3:
1210 subtype = "FIFO, buffer";
1211 break;
1212 }
1213 break;
1214 case 3:
1215 major = "Trace Source";
1216 switch (minor) {
1217 case 0:
1218 subtype = "other";
1219 break;
1220 case 1:
1221 subtype = "Processor";
1222 break;
1223 case 2:
1224 subtype = "DSP";
1225 break;
1226 case 3:
1227 subtype = "Engine/Coprocessor";
1228 break;
1229 case 4:
1230 subtype = "Bus";
1231 break;
1232 case 6:
1233 subtype = "Software";
1234 break;
1235 }
1236 break;
1237 case 4:
1238 major = "Debug Control";
1239 switch (minor) {
1240 case 0:
1241 subtype = "other";
1242 break;
1243 case 1:
1244 subtype = "Trigger Matrix";
1245 break;
1246 case 2:
1247 subtype = "Debug Auth";
1248 break;
1249 case 3:
1250 subtype = "Power Requestor";
1251 break;
1252 }
1253 break;
1254 case 5:
1255 major = "Debug Logic";
1256 switch (minor) {
1257 case 0:
1258 subtype = "other";
1259 break;
1260 case 1:
1261 subtype = "Processor";
1262 break;
1263 case 2:
1264 subtype = "DSP";
1265 break;
1266 case 3:
1267 subtype = "Engine/Coprocessor";
1268 break;
1269 case 4:
1270 subtype = "Bus";
1271 break;
1272 case 5:
1273 subtype = "Memory";
1274 break;
1275 }
1276 break;
1277 case 6:
1278 major = "Perfomance Monitor";
1279 switch (minor) {
1280 case 0:
1281 subtype = "other";
1282 break;
1283 case 1:
1284 subtype = "Processor";
1285 break;
1286 case 2:
1287 subtype = "DSP";
1288 break;
1289 case 3:
1290 subtype = "Engine/Coprocessor";
1291 break;
1292 case 4:
1293 subtype = "Bus";
1294 break;
1295 case 5:
1296 subtype = "Memory";
1297 break;
1298 }
1299 break;
1300 }
1301 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1302 (uint8_t)(devtype & 0xff),
1303 major, subtype);
1304 /* REVISIT also show 0xfc8 DevId */
1305 }
1306
1307 return ERROR_OK;
1308 }
1309
1310 static int dap_info_command(struct command_context *cmd_ctx,
1311 struct adiv5_ap *ap)
1312 {
1313 int retval;
1314 uint32_t dbgbase, apid;
1315 uint8_t mem_ap;
1316
1317 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1318 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1319 if (retval != ERROR_OK)
1320 return retval;
1321
1322 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1323 if (apid == 0) {
1324 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1325 return ERROR_FAIL;
1326 }
1327
1328 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1329 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1330 command_print(cmd_ctx, "\tType is JTAG-AP");
1331 break;
1332 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1333 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1334 break;
1335 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1336 command_print(cmd_ctx, "\tType is MEM-AP APB");
1337 break;
1338 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1339 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1340 break;
1341 default:
1342 command_print(cmd_ctx, "\tUnknown AP type");
1343 break;
1344 }
1345
1346 /* NOTE: a MEM-AP may have a single CoreSight component that's
1347 * not a ROM table ... or have no such components at all.
1348 */
1349 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1350 if (mem_ap) {
1351 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1352
1353 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1354 command_print(cmd_ctx, "\tNo ROM table present");
1355 } else {
1356 if (dbgbase & 0x01)
1357 command_print(cmd_ctx, "\tValid ROM table present");
1358 else
1359 command_print(cmd_ctx, "\tROM table in legacy format");
1360
1361 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1362 }
1363 }
1364
1365 return ERROR_OK;
1366 }
1367
1368 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1369 {
1370 struct adiv5_private_config *pc;
1371 const char *arg;
1372 jim_wide ap_num;
1373 int e;
1374
1375 /* check if argv[0] is for us */
1376 arg = Jim_GetString(goi->argv[0], NULL);
1377 if (strcmp(arg, "-ap-num"))
1378 return JIM_CONTINUE;
1379
1380 e = Jim_GetOpt_String(goi, &arg, NULL);
1381 if (e != JIM_OK)
1382 return e;
1383
1384 if (goi->argc == 0) {
1385 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ...");
1386 return JIM_ERR;
1387 }
1388
1389 e = Jim_GetOpt_Wide(goi, &ap_num);
1390 if (e != JIM_OK)
1391 return e;
1392
1393 if (target->private_config == NULL) {
1394 pc = calloc(1, sizeof(struct adiv5_private_config));
1395 target->private_config = pc;
1396 pc->ap_num = ap_num;
1397 }
1398
1399
1400 return JIM_OK;
1401 }
1402
1403 COMMAND_HANDLER(handle_dap_info_command)
1404 {
1405 struct target *target = get_current_target(CMD_CTX);
1406 struct arm *arm = target_to_arm(target);
1407 struct adiv5_dap *dap = arm->dap;
1408 uint32_t apsel;
1409
1410 switch (CMD_ARGC) {
1411 case 0:
1412 apsel = dap->apsel;
1413 break;
1414 case 1:
1415 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1416 if (apsel >= 256)
1417 return ERROR_COMMAND_SYNTAX_ERROR;
1418 break;
1419 default:
1420 return ERROR_COMMAND_SYNTAX_ERROR;
1421 }
1422
1423 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1424 }
1425
1426 COMMAND_HANDLER(dap_baseaddr_command)
1427 {
1428 struct target *target = get_current_target(CMD_CTX);
1429 struct arm *arm = target_to_arm(target);
1430 struct adiv5_dap *dap = arm->dap;
1431
1432 uint32_t apsel, baseaddr;
1433 int retval;
1434
1435 switch (CMD_ARGC) {
1436 case 0:
1437 apsel = dap->apsel;
1438 break;
1439 case 1:
1440 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1441 /* AP address is in bits 31:24 of DP_SELECT */
1442 if (apsel >= 256)
1443 return ERROR_COMMAND_SYNTAX_ERROR;
1444 break;
1445 default:
1446 return ERROR_COMMAND_SYNTAX_ERROR;
1447 }
1448
1449 /* NOTE: assumes we're talking to a MEM-AP, which
1450 * has a base address. There are other kinds of AP,
1451 * though they're not common for now. This should
1452 * use the ID register to verify it's a MEM-AP.
1453 */
1454 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1455 if (retval != ERROR_OK)
1456 return retval;
1457 retval = dap_run(dap);
1458 if (retval != ERROR_OK)
1459 return retval;
1460
1461 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1462
1463 return retval;
1464 }
1465
1466 COMMAND_HANDLER(dap_memaccess_command)
1467 {
1468 struct target *target = get_current_target(CMD_CTX);
1469 struct arm *arm = target_to_arm(target);
1470 struct adiv5_dap *dap = arm->dap;
1471
1472 uint32_t memaccess_tck;
1473
1474 switch (CMD_ARGC) {
1475 case 0:
1476 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1477 break;
1478 case 1:
1479 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1480 break;
1481 default:
1482 return ERROR_COMMAND_SYNTAX_ERROR;
1483 }
1484 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1485
1486 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1487 dap->ap[dap->apsel].memaccess_tck);
1488
1489 return ERROR_OK;
1490 }
1491
1492 COMMAND_HANDLER(dap_apsel_command)
1493 {
1494 struct target *target = get_current_target(CMD_CTX);
1495 struct arm *arm = target_to_arm(target);
1496 struct adiv5_dap *dap = arm->dap;
1497
1498 uint32_t apsel, apid;
1499 int retval;
1500
1501 switch (CMD_ARGC) {
1502 case 0:
1503 apsel = dap->apsel;
1504 break;
1505 case 1:
1506 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1507 /* AP address is in bits 31:24 of DP_SELECT */
1508 if (apsel >= 256)
1509 return ERROR_COMMAND_SYNTAX_ERROR;
1510 break;
1511 default:
1512 return ERROR_COMMAND_SYNTAX_ERROR;
1513 }
1514
1515 dap->apsel = apsel;
1516
1517 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1518 if (retval != ERROR_OK)
1519 return retval;
1520 retval = dap_run(dap);
1521 if (retval != ERROR_OK)
1522 return retval;
1523
1524 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1525 apsel, apid);
1526
1527 return retval;
1528 }
1529
1530 COMMAND_HANDLER(dap_apcsw_command)
1531 {
1532 struct target *target = get_current_target(CMD_CTX);
1533 struct arm *arm = target_to_arm(target);
1534 struct adiv5_dap *dap = arm->dap;
1535
1536 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1537
1538 switch (CMD_ARGC) {
1539 case 0:
1540 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1541 (dap->apsel), apcsw);
1542 break;
1543 case 1:
1544 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1545 /* AP address is in bits 31:24 of DP_SELECT */
1546 if (sprot > 1)
1547 return ERROR_COMMAND_SYNTAX_ERROR;
1548 if (sprot)
1549 apcsw |= CSW_SPROT;
1550 else
1551 apcsw &= ~CSW_SPROT;
1552 break;
1553 default:
1554 return ERROR_COMMAND_SYNTAX_ERROR;
1555 }
1556 dap->ap[dap->apsel].csw_default = apcsw;
1557
1558 return 0;
1559 }
1560
1561
1562
1563 COMMAND_HANDLER(dap_apid_command)
1564 {
1565 struct target *target = get_current_target(CMD_CTX);
1566 struct arm *arm = target_to_arm(target);
1567 struct adiv5_dap *dap = arm->dap;
1568
1569 uint32_t apsel, apid;
1570 int retval;
1571
1572 switch (CMD_ARGC) {
1573 case 0:
1574 apsel = dap->apsel;
1575 break;
1576 case 1:
1577 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1578 /* AP address is in bits 31:24 of DP_SELECT */
1579 if (apsel >= 256)
1580 return ERROR_COMMAND_SYNTAX_ERROR;
1581 break;
1582 default:
1583 return ERROR_COMMAND_SYNTAX_ERROR;
1584 }
1585
1586 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1587 if (retval != ERROR_OK)
1588 return retval;
1589 retval = dap_run(dap);
1590 if (retval != ERROR_OK)
1591 return retval;
1592
1593 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1594
1595 return retval;
1596 }
1597
1598 COMMAND_HANDLER(dap_apreg_command)
1599 {
1600 struct target *target = get_current_target(CMD_CTX);
1601 struct arm *arm = target_to_arm(target);
1602 struct adiv5_dap *dap = arm->dap;
1603
1604 uint32_t apsel, reg, value;
1605 int retval;
1606
1607 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1608 return ERROR_COMMAND_SYNTAX_ERROR;
1609
1610 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1611 /* AP address is in bits 31:24 of DP_SELECT */
1612 if (apsel >= 256)
1613 return ERROR_COMMAND_SYNTAX_ERROR;
1614
1615 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1616 if (reg >= 256 || (reg & 3))
1617 return ERROR_COMMAND_SYNTAX_ERROR;
1618
1619 if (CMD_ARGC == 3) {
1620 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1621 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1622 } else {
1623 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1624 }
1625 if (retval == ERROR_OK)
1626 retval = dap_run(dap);
1627
1628 if (retval != ERROR_OK)
1629 return retval;
1630
1631 if (CMD_ARGC == 2)
1632 command_print(CMD_CTX, "0x%08" PRIx32, value);
1633
1634 return retval;
1635 }
1636
1637 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1638 {
1639 struct target *target = get_current_target(CMD_CTX);
1640 struct arm *arm = target_to_arm(target);
1641 struct adiv5_dap *dap = arm->dap;
1642
1643 uint32_t enable = dap->ti_be_32_quirks;
1644
1645 switch (CMD_ARGC) {
1646 case 0:
1647 break;
1648 case 1:
1649 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1650 if (enable > 1)
1651 return ERROR_COMMAND_SYNTAX_ERROR;
1652 break;
1653 default:
1654 return ERROR_COMMAND_SYNTAX_ERROR;
1655 }
1656 dap->ti_be_32_quirks = enable;
1657 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1658 enable ? "enabled" : "disabled");
1659
1660 return 0;
1661 }
1662
1663 static const struct command_registration dap_commands[] = {
1664 {
1665 .name = "info",
1666 .handler = handle_dap_info_command,
1667 .mode = COMMAND_EXEC,
1668 .help = "display ROM table for MEM-AP "
1669 "(default currently selected AP)",
1670 .usage = "[ap_num]",
1671 },
1672 {
1673 .name = "apsel",
1674 .handler = dap_apsel_command,
1675 .mode = COMMAND_EXEC,
1676 .help = "Set the currently selected AP (default 0) "
1677 "and display the result",
1678 .usage = "[ap_num]",
1679 },
1680 {
1681 .name = "apcsw",
1682 .handler = dap_apcsw_command,
1683 .mode = COMMAND_EXEC,
1684 .help = "Set csw access bit ",
1685 .usage = "[sprot]",
1686 },
1687
1688 {
1689 .name = "apid",
1690 .handler = dap_apid_command,
1691 .mode = COMMAND_EXEC,
1692 .help = "return ID register from AP "
1693 "(default currently selected AP)",
1694 .usage = "[ap_num]",
1695 },
1696 {
1697 .name = "apreg",
1698 .handler = dap_apreg_command,
1699 .mode = COMMAND_EXEC,
1700 .help = "read/write a register from AP "
1701 "(reg is byte address of a word register, like 0 4 8...)",
1702 .usage = "ap_num reg [value]",
1703 },
1704 {
1705 .name = "baseaddr",
1706 .handler = dap_baseaddr_command,
1707 .mode = COMMAND_EXEC,
1708 .help = "return debug base address from MEM-AP "
1709 "(default currently selected AP)",
1710 .usage = "[ap_num]",
1711 },
1712 {
1713 .name = "memaccess",
1714 .handler = dap_memaccess_command,
1715 .mode = COMMAND_EXEC,
1716 .help = "set/get number of extra tck for MEM-AP memory "
1717 "bus access [0-255]",
1718 .usage = "[cycles]",
1719 },
1720 {
1721 .name = "ti_be_32_quirks",
1722 .handler = dap_ti_be_32_quirks_command,
1723 .mode = COMMAND_CONFIG,
1724 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1725 .usage = "[enable]",
1726 },
1727 COMMAND_REGISTRATION_DONE
1728 };
1729
1730 const struct command_registration dap_command_handlers[] = {
1731 {
1732 .name = "dap",
1733 .mode = COMMAND_EXEC,
1734 .help = "DAP command group",
1735 .usage = "",
1736 .chain = dap_commands,
1737 },
1738 COMMAND_REGISTRATION_DONE
1739 };
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