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[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "jtag/interface.h"
73 #include "arm.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
76
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
78
79 /*
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 */
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 {
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
86 }
87
88 /***************************************************************************
89 * *
90 * DP and MEM-AP register access through APACC and DPACC *
91 * *
92 ***************************************************************************/
93
94 /**
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
98 *
99 * @param dap The DAP
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
102 */
103 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
104 {
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
106
107 if (new_ap != dap->ap_current) {
108 dap->ap_current = new_ap;
109 /* Switching AP invalidates cached values.
110 * Values MUST BE UPDATED BEFORE AP ACCESS.
111 */
112 dap->ap_bank_value = -1;
113 dap->ap_csw_value = -1;
114 dap->ap_tar_value = -1;
115 }
116 }
117
118 /**
119 * Queue transactions setting up transfer parameters for the
120 * currently selected MEM-AP.
121 *
122 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
123 * initiate data reads or writes using memory or peripheral addresses.
124 * If the CSW is configured for it, the TAR may be automatically
125 * incremented after each transfer.
126 *
127 * @todo Rename to reflect it being specifically a MEM-AP function.
128 *
129 * @param dap The DAP connected to the MEM-AP.
130 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
131 * matches the cached value, the register is not changed.
132 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
133 * matches the cached address, the register is not changed.
134 *
135 * @return ERROR_OK if the transaction was properly queued, else a fault code.
136 */
137 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
138 {
139 int retval;
140
141 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
142 if (csw != dap->ap_csw_value) {
143 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
144 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
145 if (retval != ERROR_OK)
146 return retval;
147 dap->ap_csw_value = csw;
148 }
149 if (tar != dap->ap_tar_value) {
150 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
151 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
152 if (retval != ERROR_OK)
153 return retval;
154 dap->ap_tar_value = tar;
155 }
156 /* Disable TAR cache when autoincrementing */
157 if (csw & CSW_ADDRINC_MASK)
158 dap->ap_tar_value = -1;
159 return ERROR_OK;
160 }
161
162 /**
163 * Asynchronous (queued) read of a word from memory or a system register.
164 *
165 * @param dap The DAP connected to the MEM-AP performing the read.
166 * @param address Address of the 32-bit word to read; it must be
167 * readable by the currently selected MEM-AP.
168 * @param value points to where the word will be stored when the
169 * transaction queue is flushed (assuming no errors).
170 *
171 * @return ERROR_OK for success. Otherwise a fault code.
172 */
173 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
174 uint32_t *value)
175 {
176 int retval;
177
178 /* Use banked addressing (REG_BDx) to avoid some link traffic
179 * (updating TAR) when reading several consecutive addresses.
180 */
181 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
182 address & 0xFFFFFFF0);
183 if (retval != ERROR_OK)
184 return retval;
185
186 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
187 }
188
189 /**
190 * Synchronous read of a word from memory or a system register.
191 * As a side effect, this flushes any queued transactions.
192 *
193 * @param dap The DAP connected to the MEM-AP performing the read.
194 * @param address Address of the 32-bit word to read; it must be
195 * readable by the currently selected MEM-AP.
196 * @param value points to where the result will be stored.
197 *
198 * @return ERROR_OK for success; *value holds the result.
199 * Otherwise a fault code.
200 */
201 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
202 uint32_t *value)
203 {
204 int retval;
205
206 retval = mem_ap_read_u32(dap, address, value);
207 if (retval != ERROR_OK)
208 return retval;
209
210 return dap_run(dap);
211 }
212
213 /**
214 * Asynchronous (queued) write of a word to memory or a system register.
215 *
216 * @param dap The DAP connected to the MEM-AP.
217 * @param address Address to be written; it must be writable by
218 * the currently selected MEM-AP.
219 * @param value Word that will be written to the address when transaction
220 * queue is flushed (assuming no errors).
221 *
222 * @return ERROR_OK for success. Otherwise a fault code.
223 */
224 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
225 uint32_t value)
226 {
227 int retval;
228
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when writing several consecutive addresses.
231 */
232 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
233 address & 0xFFFFFFF0);
234 if (retval != ERROR_OK)
235 return retval;
236
237 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
238 value);
239 }
240
241 /**
242 * Synchronous write of a word to memory or a system register.
243 * As a side effect, this flushes any queued transactions.
244 *
245 * @param dap The DAP connected to the MEM-AP.
246 * @param address Address to be written; it must be writable by
247 * the currently selected MEM-AP.
248 * @param value Word that will be written.
249 *
250 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
251 */
252 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
253 uint32_t value)
254 {
255 int retval = mem_ap_write_u32(dap, address, value);
256
257 if (retval != ERROR_OK)
258 return retval;
259
260 return dap_run(dap);
261 }
262
263 /*****************************************************************************
264 * *
265 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address, bool addr_incr) *
266 * *
267 * Write a buffer in target order (little endian) *
268 * *
269 *****************************************************************************/
270 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr)
271 {
272 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
273 uint32_t adr = address;
274 const uint8_t *pBuffer = buffer;
275 uint32_t incr_flag = CSW_ADDRINC_OFF;
276
277 count >>= 2;
278 wcount = count;
279
280 /* if we have an unaligned access - reorder data */
281 if (adr & 0x3u) {
282 for (writecount = 0; writecount < count; writecount++) {
283 int i;
284 uint32_t outvalue;
285 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
286
287 for (i = 0; i < 4; i++) {
288 *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue;
289 outvalue >>= 8;
290 adr++;
291 }
292 pBuffer += sizeof(uint32_t);
293 }
294 }
295
296 while (wcount > 0) {
297 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
298 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
299 if (wcount < blocksize)
300 blocksize = wcount;
301
302 /* handle unaligned data at 4k boundary */
303 if (blocksize == 0)
304 blocksize = 1;
305
306 if (addr_incr)
307 incr_flag = CSW_ADDRINC_SINGLE;
308
309 retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag, address);
310 if (retval != ERROR_OK)
311 return retval;
312
313 for (writecount = 0; writecount < blocksize; writecount++) {
314 uint32_t tmp;
315 tmp = buf_get_u32(buffer + 4 * writecount, 0, 32);
316 retval = dap_queue_ap_write(dap, AP_REG_DRW, tmp);
317 if (retval != ERROR_OK)
318 break;
319 }
320
321 retval = dap_run(dap);
322 if (retval == ERROR_OK) {
323 wcount = wcount - blocksize;
324 if (addr_incr)
325 address = address + 4 * blocksize;
326 buffer = buffer + 4 * blocksize;
327 } else
328 errorcount++;
329
330 if (errorcount > 1) {
331 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
332 return retval;
333 }
334 }
335
336 return retval;
337 }
338
339 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
340 const uint8_t *buffer, int count, uint32_t address)
341 {
342 int retval = ERROR_OK;
343 int wcount, blocksize, writecount, i;
344
345 wcount = count >> 1;
346
347 while (wcount > 0) {
348 int nbytes;
349
350 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
351 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
352
353 if (wcount < blocksize)
354 blocksize = wcount;
355
356 /* handle unaligned data at 4k boundary */
357 if (blocksize == 0)
358 blocksize = 1;
359
360 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
361 if (retval != ERROR_OK)
362 return retval;
363 writecount = blocksize;
364
365 do {
366 nbytes = MIN((writecount << 1), 4);
367
368 if (nbytes < 4) {
369 retval = mem_ap_write_buf_u16(dap, buffer,
370 nbytes, address);
371 if (retval != ERROR_OK) {
372 LOG_WARNING("Block write error address "
373 "0x%" PRIx32 ", count 0x%x",
374 address, count);
375 return retval;
376 }
377
378 address += nbytes >> 1;
379 } else {
380 uint32_t outvalue;
381 memcpy(&outvalue, buffer, sizeof(uint32_t));
382
383 for (i = 0; i < nbytes; i++) {
384 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
385 outvalue >>= 8;
386 address++;
387 }
388
389 memcpy(&outvalue, buffer, sizeof(uint32_t));
390 retval = dap_queue_ap_write(dap,
391 AP_REG_DRW, outvalue);
392 if (retval != ERROR_OK)
393 break;
394
395 retval = dap_run(dap);
396 if (retval != ERROR_OK) {
397 LOG_WARNING("Block write error address "
398 "0x%" PRIx32 ", count 0x%x",
399 address, count);
400 return retval;
401 }
402 }
403
404 buffer += nbytes >> 1;
405 writecount -= nbytes >> 1;
406
407 } while (writecount);
408 wcount -= blocksize;
409 }
410
411 return retval;
412 }
413
414 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
415 {
416 int retval = ERROR_OK;
417
418 if (count >= 4)
419 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
420
421 while (count > 0) {
422 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
423 if (retval != ERROR_OK)
424 return retval;
425 uint16_t svalue;
426 memcpy(&svalue, buffer, sizeof(uint16_t));
427 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
428 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
429 if (retval != ERROR_OK)
430 break;
431
432 retval = dap_run(dap);
433 if (retval != ERROR_OK)
434 break;
435
436 count -= 2;
437 address += 2;
438 buffer += 2;
439 }
440
441 return retval;
442 }
443
444 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
445 const uint8_t *buffer, int count, uint32_t address)
446 {
447 int retval = ERROR_OK;
448 int wcount, blocksize, writecount, i;
449
450 wcount = count;
451
452 while (wcount > 0) {
453 int nbytes;
454
455 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
456 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
457
458 if (wcount < blocksize)
459 blocksize = wcount;
460
461 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
462 if (retval != ERROR_OK)
463 return retval;
464 writecount = blocksize;
465
466 do {
467 nbytes = MIN(writecount, 4);
468
469 if (nbytes < 4) {
470 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
471 if (retval != ERROR_OK) {
472 LOG_WARNING("Block write error address "
473 "0x%" PRIx32 ", count 0x%x",
474 address, count);
475 return retval;
476 }
477
478 address += nbytes;
479 } else {
480 uint32_t outvalue;
481 memcpy(&outvalue, buffer, sizeof(uint32_t));
482
483 for (i = 0; i < nbytes; i++) {
484 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
485 outvalue >>= 8;
486 address++;
487 }
488
489 memcpy(&outvalue, buffer, sizeof(uint32_t));
490 retval = dap_queue_ap_write(dap,
491 AP_REG_DRW, outvalue);
492 if (retval != ERROR_OK)
493 break;
494
495 retval = dap_run(dap);
496 if (retval != ERROR_OK) {
497 LOG_WARNING("Block write error address "
498 "0x%" PRIx32 ", count 0x%x",
499 address, count);
500 return retval;
501 }
502 }
503
504 buffer += nbytes;
505 writecount -= nbytes;
506
507 } while (writecount);
508 wcount -= blocksize;
509 }
510
511 return retval;
512 }
513
514 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
515 {
516 int retval = ERROR_OK;
517
518 if (count >= 4)
519 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
520
521 while (count > 0) {
522 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
523 if (retval != ERROR_OK)
524 return retval;
525 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
526 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
527 if (retval != ERROR_OK)
528 break;
529
530 retval = dap_run(dap);
531 if (retval != ERROR_OK)
532 break;
533
534 count--;
535 address++;
536 buffer++;
537 }
538
539 return retval;
540 }
541
542 /**
543 * Synchronously read a block of 32-bit words into a buffer
544 * @param dap The DAP connected to the MEM-AP.
545 * @param buffer where the words will be stored (in host byte order).
546 * @param count How many words to read.
547 * @param address Memory address from which to read words; all the
548 * @param addr_incr if true, increment the source address for each u32
549 * words must be readable by the currently selected MEM-AP.
550 */
551 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
552 int count, uint32_t address, bool addr_incr)
553 {
554 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
555 uint32_t adr = address;
556 uint8_t *pBuffer = buffer;
557 uint32_t incr_flag = CSW_ADDRINC_OFF;
558
559 count >>= 2;
560 wcount = count;
561
562 while (wcount > 0) {
563 /* Adjust to read blocks within boundaries aligned to the
564 * TAR autoincrement size (at least 2^10). Autoincrement
565 * mode avoids an extra per-word roundtrip to update TAR.
566 */
567 blocksize = max_tar_block_size(dap->tar_autoincr_block,
568 address);
569 if (wcount < blocksize)
570 blocksize = wcount;
571
572 /* handle unaligned data at 4k boundary */
573 if (blocksize == 0)
574 blocksize = 1;
575
576 if (addr_incr)
577 incr_flag = CSW_ADDRINC_SINGLE;
578
579 retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag,
580 address);
581 if (retval != ERROR_OK)
582 return retval;
583
584 retval = dap_queue_ap_read_block(dap, AP_REG_DRW, blocksize, buffer);
585
586 retval = dap_run(dap);
587 if (retval != ERROR_OK) {
588 errorcount++;
589 if (errorcount <= 1) {
590 /* try again */
591 continue;
592 }
593 LOG_WARNING("Block read error address 0x%" PRIx32, address);
594 return retval;
595 }
596 wcount = wcount - blocksize;
597 if (addr_incr)
598 address += 4 * blocksize;
599 buffer += 4 * blocksize;
600 }
601
602 /* if we have an unaligned access - reorder data */
603 if (adr & 0x3u) {
604 for (readcount = 0; readcount < count; readcount++) {
605 int i;
606 uint32_t data;
607 memcpy(&data, pBuffer, sizeof(uint32_t));
608
609 for (i = 0; i < 4; i++) {
610 *((uint8_t *)pBuffer) =
611 (data >> 8 * (adr & 0x3));
612 pBuffer++;
613 adr++;
614 }
615 }
616 }
617
618 return retval;
619 }
620
621 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
622 uint8_t *buffer, int count, uint32_t address)
623 {
624 uint32_t invalue;
625 int retval = ERROR_OK;
626 int wcount, blocksize, readcount, i;
627
628 wcount = count >> 1;
629
630 while (wcount > 0) {
631 int nbytes;
632
633 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
634 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
635 if (wcount < blocksize)
636 blocksize = wcount;
637
638 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
639 if (retval != ERROR_OK)
640 return retval;
641
642 /* handle unaligned data at 4k boundary */
643 if (blocksize == 0)
644 blocksize = 1;
645 readcount = blocksize;
646
647 do {
648 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
649 if (retval != ERROR_OK)
650 return retval;
651 retval = dap_run(dap);
652 if (retval != ERROR_OK) {
653 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
654 return retval;
655 }
656
657 nbytes = MIN((readcount << 1), 4);
658
659 for (i = 0; i < nbytes; i++) {
660 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
661 buffer++;
662 address++;
663 }
664
665 readcount -= (nbytes >> 1);
666 } while (readcount);
667 wcount -= blocksize;
668 }
669
670 return retval;
671 }
672
673 /**
674 * Synchronously read a block of 16-bit halfwords into a buffer
675 * @param dap The DAP connected to the MEM-AP.
676 * @param buffer where the halfwords will be stored (in host byte order).
677 * @param count How many halfwords to read.
678 * @param address Memory address from which to read words; all the
679 * words must be readable by the currently selected MEM-AP.
680 */
681 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
682 int count, uint32_t address)
683 {
684 uint32_t invalue, i;
685 int retval = ERROR_OK;
686
687 if (count >= 4)
688 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
689
690 while (count > 0) {
691 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
692 if (retval != ERROR_OK)
693 return retval;
694 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
695 if (retval != ERROR_OK)
696 break;
697
698 retval = dap_run(dap);
699 if (retval != ERROR_OK)
700 break;
701
702 if (address & 0x1) {
703 for (i = 0; i < 2; i++) {
704 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
705 buffer++;
706 address++;
707 }
708 } else {
709 uint16_t svalue = (invalue >> 8 * (address & 0x3));
710 memcpy(buffer, &svalue, sizeof(uint16_t));
711 address += 2;
712 buffer += 2;
713 }
714 count -= 2;
715 }
716
717 return retval;
718 }
719
720 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
721 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
722 *
723 * The solution is to arrange for a large out/in scan in this loop and
724 * and convert data afterwards.
725 */
726 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
727 uint8_t *buffer, int count, uint32_t address)
728 {
729 uint32_t invalue;
730 int retval = ERROR_OK;
731 int wcount, blocksize, readcount, i;
732
733 wcount = count;
734
735 while (wcount > 0) {
736 int nbytes;
737
738 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
739 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
740
741 if (wcount < blocksize)
742 blocksize = wcount;
743
744 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
745 if (retval != ERROR_OK)
746 return retval;
747 readcount = blocksize;
748
749 do {
750 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
751 if (retval != ERROR_OK)
752 return retval;
753 retval = dap_run(dap);
754 if (retval != ERROR_OK) {
755 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
756 return retval;
757 }
758
759 nbytes = MIN(readcount, 4);
760
761 for (i = 0; i < nbytes; i++) {
762 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
763 buffer++;
764 address++;
765 }
766
767 readcount -= nbytes;
768 } while (readcount);
769 wcount -= blocksize;
770 }
771
772 return retval;
773 }
774
775 /**
776 * Synchronously read a block of bytes into a buffer
777 * @param dap The DAP connected to the MEM-AP.
778 * @param buffer where the bytes will be stored.
779 * @param count How many bytes to read.
780 * @param address Memory address from which to read data; all the
781 * data must be readable by the currently selected MEM-AP.
782 */
783 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
784 int count, uint32_t address)
785 {
786 uint32_t invalue;
787 int retval = ERROR_OK;
788
789 if (count >= 4)
790 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
791
792 while (count > 0) {
793 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
794 if (retval != ERROR_OK)
795 return retval;
796 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
797 if (retval != ERROR_OK)
798 return retval;
799 retval = dap_run(dap);
800 if (retval != ERROR_OK)
801 break;
802
803 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
804 count--;
805 address++;
806 buffer++;
807 }
808
809 return retval;
810 }
811
812 /*--------------------------------------------------------------------*/
813 /* Wrapping function with selection of AP */
814 /*--------------------------------------------------------------------*/
815 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
816 uint32_t address, uint32_t *value)
817 {
818 dap_ap_select(swjdp, ap);
819 return mem_ap_read_u32(swjdp, address, value);
820 }
821
822 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
823 uint32_t address, uint32_t value)
824 {
825 dap_ap_select(swjdp, ap);
826 return mem_ap_write_u32(swjdp, address, value);
827 }
828
829 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
830 uint32_t address, uint32_t *value)
831 {
832 dap_ap_select(swjdp, ap);
833 return mem_ap_read_atomic_u32(swjdp, address, value);
834 }
835
836 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
837 uint32_t address, uint32_t value)
838 {
839 dap_ap_select(swjdp, ap);
840 return mem_ap_write_atomic_u32(swjdp, address, value);
841 }
842
843 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
844 uint8_t *buffer, int count, uint32_t address)
845 {
846 dap_ap_select(swjdp, ap);
847 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
848 }
849
850 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
851 uint8_t *buffer, int count, uint32_t address)
852 {
853 dap_ap_select(swjdp, ap);
854 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
855 }
856
857 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
858 uint8_t *buffer, int count, uint32_t address)
859 {
860 dap_ap_select(swjdp, ap);
861 return mem_ap_read_buf_u32(swjdp, buffer, count, address, false);
862 }
863
864 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
865 uint8_t *buffer, int count, uint32_t address)
866 {
867 dap_ap_select(swjdp, ap);
868 return mem_ap_read_buf_u32(swjdp, buffer, count, address, true);
869 }
870
871 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
872 const uint8_t *buffer, int count, uint32_t address)
873 {
874 dap_ap_select(swjdp, ap);
875 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
876 }
877
878 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
879 const uint8_t *buffer, int count, uint32_t address)
880 {
881 dap_ap_select(swjdp, ap);
882 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
883 }
884
885 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
886 const uint8_t *buffer, int count, uint32_t address)
887 {
888 dap_ap_select(swjdp, ap);
889 return mem_ap_write_buf_u32(swjdp, buffer, count, address, true);
890 }
891
892 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
893 const uint8_t *buffer, int count, uint32_t address)
894 {
895 dap_ap_select(swjdp, ap);
896 return mem_ap_write_buf_u32(swjdp, buffer, count, address, false);
897 }
898
899 #define MDM_REG_STAT 0x00
900 #define MDM_REG_CTRL 0x04
901 #define MDM_REG_ID 0xfc
902
903 #define MDM_STAT_FMEACK (1<<0)
904 #define MDM_STAT_FREADY (1<<1)
905 #define MDM_STAT_SYSSEC (1<<2)
906 #define MDM_STAT_SYSRES (1<<3)
907 #define MDM_STAT_FMEEN (1<<5)
908 #define MDM_STAT_BACKDOOREN (1<<6)
909 #define MDM_STAT_LPEN (1<<7)
910 #define MDM_STAT_VLPEN (1<<8)
911 #define MDM_STAT_LLSMODEXIT (1<<9)
912 #define MDM_STAT_VLLSXMODEXIT (1<<10)
913 #define MDM_STAT_CORE_HALTED (1<<16)
914 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
915 #define MDM_STAT_CORESLEEPING (1<<18)
916
917 #define MEM_CTRL_FMEIP (1<<0)
918 #define MEM_CTRL_DBG_DIS (1<<1)
919 #define MEM_CTRL_DBG_REQ (1<<2)
920 #define MEM_CTRL_SYS_RES_REQ (1<<3)
921 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
922 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
923 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
924 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
925
926 /**
927 *
928 */
929 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
930 {
931 uint32_t val;
932 int retval;
933 enum reset_types jtag_reset_config = jtag_get_reset_config();
934
935 dap_ap_select(dap, 1);
936
937 /* first check mdm-ap id register */
938 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
939 if (retval != ERROR_OK)
940 return retval;
941 dap_run(dap);
942
943 if (val != 0x001C0000) {
944 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val);
945 dap_ap_select(dap, 0);
946 return ERROR_FAIL;
947 }
948
949 /* read and parse status register
950 * it's important that the device is out of
951 * reset here
952 */
953 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
954 if (retval != ERROR_OK)
955 return retval;
956 dap_run(dap);
957
958 LOG_DEBUG("MDM_REG_STAT %08X", val);
959
960 if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) {
961 LOG_DEBUG("MDMAP: system is secured, masserase needed");
962
963 if (!(val & MDM_STAT_FMEEN))
964 LOG_DEBUG("MDMAP: masserase is disabled");
965 else {
966 /* we need to assert reset */
967 if (jtag_reset_config & RESET_HAS_SRST) {
968 /* default to asserting srst */
969 adapter_assert_reset();
970 } else {
971 LOG_DEBUG("SRST not configured");
972 dap_ap_select(dap, 0);
973 return ERROR_FAIL;
974 }
975
976 while (1) {
977 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
978 if (retval != ERROR_OK)
979 return retval;
980 dap_run(dap);
981 /* read status register and wait for ready */
982 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
983 if (retval != ERROR_OK)
984 return retval;
985 dap_run(dap);
986 LOG_DEBUG("MDM_REG_STAT %08X", val);
987
988 if ((val & 1))
989 break;
990 }
991
992 while (1) {
993 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
994 if (retval != ERROR_OK)
995 return retval;
996 dap_run(dap);
997 /* read status register */
998 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
999 if (retval != ERROR_OK)
1000 return retval;
1001 dap_run(dap);
1002 LOG_DEBUG("MDM_REG_STAT %08X", val);
1003 /* read control register and wait for ready */
1004 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1005 if (retval != ERROR_OK)
1006 return retval;
1007 dap_run(dap);
1008 LOG_DEBUG("MDM_REG_CTRL %08X", val);
1009
1010 if (val == 0x00)
1011 break;
1012 }
1013 }
1014 }
1015
1016 dap_ap_select(dap, 0);
1017
1018 return ERROR_OK;
1019 }
1020
1021 /** */
1022 struct dap_syssec_filter {
1023 /** */
1024 uint32_t idcode;
1025 /** */
1026 int (*dap_init)(struct adiv5_dap *dap);
1027 };
1028
1029 /** */
1030 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1031 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1032 };
1033
1034 /**
1035 *
1036 */
1037 int dap_syssec(struct adiv5_dap *dap)
1038 {
1039 unsigned int i;
1040 struct jtag_tap *tap;
1041
1042 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
1043 tap = dap->jtag_info->tap;
1044
1045 while (tap != NULL) {
1046 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
1047 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode);
1048 dap_syssec_filter_data[i].dap_init(dap);
1049 }
1050 tap = tap->next_tap;
1051 }
1052 }
1053
1054 return ERROR_OK;
1055 }
1056
1057 /*--------------------------------------------------------------------------*/
1058
1059
1060 /* FIXME don't import ... just initialize as
1061 * part of DAP transport setup
1062 */
1063 extern const struct dap_ops jtag_dp_ops;
1064
1065 /*--------------------------------------------------------------------------*/
1066
1067 /**
1068 * Initialize a DAP. This sets up the power domains, prepares the DP
1069 * for further use, and arranges to use AP #0 for all AP operations
1070 * until dap_ap-select() changes that policy.
1071 *
1072 * @param dap The DAP being initialized.
1073 *
1074 * @todo Rename this. We also need an initialization scheme which account
1075 * for SWD transports not just JTAG; that will need to address differences
1076 * in layering. (JTAG is useful without any debug target; but not SWD.)
1077 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1078 */
1079 int ahbap_debugport_init(struct adiv5_dap *dap)
1080 {
1081 uint32_t ctrlstat;
1082 int cnt = 0;
1083 int retval;
1084
1085 LOG_DEBUG(" ");
1086
1087 /* JTAG-DP or SWJ-DP, in JTAG mode
1088 * ... for SWD mode this is patched as part
1089 * of link switchover
1090 */
1091 if (!dap->ops)
1092 dap->ops = &jtag_dp_ops;
1093
1094 /* Default MEM-AP setup.
1095 *
1096 * REVISIT AP #0 may be an inappropriate default for this.
1097 * Should we probe, or take a hint from the caller?
1098 * Presumably we can ignore the possibility of multiple APs.
1099 */
1100 dap->ap_current = !0;
1101 dap_ap_select(dap, 0);
1102
1103 /* DP initialization */
1104
1105 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1106 if (retval != ERROR_OK)
1107 return retval;
1108
1109 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1110 if (retval != ERROR_OK)
1111 return retval;
1112
1113 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1114 if (retval != ERROR_OK)
1115 return retval;
1116
1117 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1118 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1119 if (retval != ERROR_OK)
1120 return retval;
1121
1122 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1123 if (retval != ERROR_OK)
1124 return retval;
1125 retval = dap_run(dap);
1126 if (retval != ERROR_OK)
1127 return retval;
1128
1129 /* Check that we have debug power domains activated */
1130 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
1131 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1132 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1133 if (retval != ERROR_OK)
1134 return retval;
1135 retval = dap_run(dap);
1136 if (retval != ERROR_OK)
1137 return retval;
1138 alive_sleep(10);
1139 }
1140
1141 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
1142 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1143 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1144 if (retval != ERROR_OK)
1145 return retval;
1146 retval = dap_run(dap);
1147 if (retval != ERROR_OK)
1148 return retval;
1149 alive_sleep(10);
1150 }
1151
1152 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1153 if (retval != ERROR_OK)
1154 return retval;
1155 /* With debug power on we can activate OVERRUN checking */
1156 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1157 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1158 if (retval != ERROR_OK)
1159 return retval;
1160 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1161 if (retval != ERROR_OK)
1162 return retval;
1163
1164 dap_syssec(dap);
1165
1166 return ERROR_OK;
1167 }
1168
1169 /* CID interpretation -- see ARM IHI 0029B section 3
1170 * and ARM IHI 0031A table 13-3.
1171 */
1172 static const char *class_description[16] = {
1173 "Reserved", "ROM table", "Reserved", "Reserved",
1174 "Reserved", "Reserved", "Reserved", "Reserved",
1175 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1176 "Reserved", "OptimoDE DESS",
1177 "Generic IP component", "PrimeCell or System component"
1178 };
1179
1180 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1181 {
1182 return cid3 == 0xb1 && cid2 == 0x05
1183 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1184 }
1185
1186 /*
1187 * This function checks the ID for each access port to find the requested Access Port type
1188 */
1189 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
1190 {
1191 int ap;
1192
1193 /* Maximum AP number is 255 since the SELECT register is 8 bits */
1194 for (ap = 0; ap <= 255; ap++) {
1195
1196 /* read the IDR register of the Access Port */
1197 uint32_t id_val = 0;
1198 dap_ap_select(dap, ap);
1199
1200 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
1201 if (retval != ERROR_OK)
1202 return retval;
1203
1204 retval = dap_run(dap);
1205
1206 /* IDR bits:
1207 * 31-28 : Revision
1208 * 27-24 : JEDEC bank (0x4 for ARM)
1209 * 23-17 : JEDEC code (0x3B for ARM)
1210 * 16 : Mem-AP
1211 * 15-8 : Reserved
1212 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
1213 */
1214
1215 /* Reading register for a non-existant AP should not cause an error,
1216 * but just to be sure, try to continue searching if an error does happen.
1217 */
1218 if ((retval == ERROR_OK) && /* Register read success */
1219 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
1220 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
1221
1222 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08X)",
1223 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
1224 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
1225 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
1226 ap, id_val);
1227
1228 *ap_num_out = ap;
1229 return ERROR_OK;
1230 }
1231 }
1232
1233 LOG_DEBUG("No %s found",
1234 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
1235 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
1236 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
1237 return ERROR_FAIL;
1238 }
1239
1240 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1241 uint32_t *out_dbgbase, uint32_t *out_apid)
1242 {
1243 uint32_t ap_old;
1244 int retval;
1245 uint32_t dbgbase, apid;
1246
1247 /* AP address is in bits 31:24 of DP_SELECT */
1248 if (ap >= 256)
1249 return ERROR_COMMAND_SYNTAX_ERROR;
1250
1251 ap_old = dap->ap_current;
1252 dap_ap_select(dap, ap);
1253
1254 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1255 if (retval != ERROR_OK)
1256 return retval;
1257 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1258 if (retval != ERROR_OK)
1259 return retval;
1260 retval = dap_run(dap);
1261 if (retval != ERROR_OK)
1262 return retval;
1263
1264 /* Excavate the device ID code */
1265 struct jtag_tap *tap = dap->jtag_info->tap;
1266 while (tap != NULL) {
1267 if (tap->hasidcode)
1268 break;
1269 tap = tap->next_tap;
1270 }
1271 if (tap == NULL || !tap->hasidcode)
1272 return ERROR_OK;
1273
1274 dap_ap_select(dap, ap_old);
1275
1276 /* The asignment happens only here to prevent modification of these
1277 * values before they are certain. */
1278 *out_dbgbase = dbgbase;
1279 *out_apid = apid;
1280
1281 return ERROR_OK;
1282 }
1283
1284 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1285 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1286 {
1287 uint32_t ap_old;
1288 uint32_t romentry, entry_offset = 0, component_base, devtype;
1289 int retval = ERROR_FAIL;
1290
1291 if (ap >= 256)
1292 return ERROR_COMMAND_SYNTAX_ERROR;
1293
1294 ap_old = dap->ap_current;
1295 dap_ap_select(dap, ap);
1296
1297 do {
1298 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1299 entry_offset, &romentry);
1300 if (retval != ERROR_OK)
1301 return retval;
1302
1303 component_base = (dbgbase & 0xFFFFF000)
1304 + (romentry & 0xFFFFF000);
1305
1306 if (romentry & 0x1) {
1307 retval = mem_ap_read_atomic_u32(dap,
1308 (component_base & 0xfffff000) | 0xfcc,
1309 &devtype);
1310 if (retval != ERROR_OK)
1311 return retval;
1312 if ((devtype & 0xff) == type) {
1313 *addr = component_base;
1314 retval = ERROR_OK;
1315 break;
1316 }
1317 }
1318 entry_offset += 4;
1319 } while (romentry > 0);
1320
1321 dap_ap_select(dap, ap_old);
1322
1323 return retval;
1324 }
1325
1326 static int dap_info_command(struct command_context *cmd_ctx,
1327 struct adiv5_dap *dap, int ap)
1328 {
1329 int retval;
1330 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1331 int romtable_present = 0;
1332 uint8_t mem_ap;
1333 uint32_t ap_old;
1334
1335 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1336 if (retval != ERROR_OK)
1337 return retval;
1338
1339 ap_old = dap->ap_current;
1340 dap_ap_select(dap, ap);
1341
1342 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1343 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1344 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1345 if (apid) {
1346 switch (apid&0x0F) {
1347 case 0:
1348 command_print(cmd_ctx, "\tType is JTAG-AP");
1349 break;
1350 case 1:
1351 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1352 break;
1353 case 2:
1354 command_print(cmd_ctx, "\tType is MEM-AP APB");
1355 break;
1356 default:
1357 command_print(cmd_ctx, "\tUnknown AP type");
1358 break;
1359 }
1360
1361 /* NOTE: a MEM-AP may have a single CoreSight component that's
1362 * not a ROM table ... or have no such components at all.
1363 */
1364 if (mem_ap)
1365 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1366 } else
1367 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1368
1369 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1370 if (romtable_present) {
1371 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1372 uint16_t entry_offset;
1373
1374 /* bit 16 of apid indicates a memory access port */
1375 if (dbgbase & 0x02)
1376 command_print(cmd_ctx, "\tValid ROM table present");
1377 else
1378 command_print(cmd_ctx, "\tROM table in legacy format");
1379
1380 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1381 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1382 if (retval != ERROR_OK)
1383 return retval;
1384 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1385 if (retval != ERROR_OK)
1386 return retval;
1387 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1388 if (retval != ERROR_OK)
1389 return retval;
1390 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1391 if (retval != ERROR_OK)
1392 return retval;
1393 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1394 if (retval != ERROR_OK)
1395 return retval;
1396 retval = dap_run(dap);
1397 if (retval != ERROR_OK)
1398 return retval;
1399
1400 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1401 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1402 ", CID2 0x%2.2x"
1403 ", CID1 0x%2.2x"
1404 ", CID0 0x%2.2x",
1405 (unsigned) cid3, (unsigned)cid2,
1406 (unsigned) cid1, (unsigned) cid0);
1407 if (memtype & 0x01)
1408 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1409 else
1410 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1411 "Dedicated debug bus.");
1412
1413 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1414 entry_offset = 0;
1415 do {
1416 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1417 if (retval != ERROR_OK)
1418 return retval;
1419 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1420 if (romentry & 0x01) {
1421 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1422 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1423 uint32_t component_base;
1424 unsigned part_num;
1425 char *type, *full;
1426
1427 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1428
1429 /* IDs are in last 4K section */
1430 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1431 if (retval != ERROR_OK)
1432 return retval;
1433 c_pid0 &= 0xff;
1434 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1435 if (retval != ERROR_OK)
1436 return retval;
1437 c_pid1 &= 0xff;
1438 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1439 if (retval != ERROR_OK)
1440 return retval;
1441 c_pid2 &= 0xff;
1442 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1443 if (retval != ERROR_OK)
1444 return retval;
1445 c_pid3 &= 0xff;
1446 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1447 if (retval != ERROR_OK)
1448 return retval;
1449 c_pid4 &= 0xff;
1450
1451 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1452 if (retval != ERROR_OK)
1453 return retval;
1454 c_cid0 &= 0xff;
1455 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1456 if (retval != ERROR_OK)
1457 return retval;
1458 c_cid1 &= 0xff;
1459 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1460 if (retval != ERROR_OK)
1461 return retval;
1462 c_cid2 &= 0xff;
1463 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1464 if (retval != ERROR_OK)
1465 return retval;
1466 c_cid3 &= 0xff;
1467
1468 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1469 "start address 0x%" PRIx32, component_base,
1470 /* component may take multiple 4K pages */
1471 component_base - 0x1000*(c_pid4 >> 4));
1472 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1473 (int) (c_cid1 >> 4) & 0xf,
1474 /* See ARM IHI 0029B Table 3-3 */
1475 class_description[(c_cid1 >> 4) & 0xf]);
1476
1477 /* CoreSight component? */
1478 if (((c_cid1 >> 4) & 0x0f) == 9) {
1479 uint32_t devtype;
1480 unsigned minor;
1481 char *major = "Reserved", *subtype = "Reserved";
1482
1483 retval = mem_ap_read_atomic_u32(dap,
1484 (component_base & 0xfffff000) | 0xfcc,
1485 &devtype);
1486 if (retval != ERROR_OK)
1487 return retval;
1488 minor = (devtype >> 4) & 0x0f;
1489 switch (devtype & 0x0f) {
1490 case 0:
1491 major = "Miscellaneous";
1492 switch (minor) {
1493 case 0:
1494 subtype = "other";
1495 break;
1496 case 4:
1497 subtype = "Validation component";
1498 break;
1499 }
1500 break;
1501 case 1:
1502 major = "Trace Sink";
1503 switch (minor) {
1504 case 0:
1505 subtype = "other";
1506 break;
1507 case 1:
1508 subtype = "Port";
1509 break;
1510 case 2:
1511 subtype = "Buffer";
1512 break;
1513 }
1514 break;
1515 case 2:
1516 major = "Trace Link";
1517 switch (minor) {
1518 case 0:
1519 subtype = "other";
1520 break;
1521 case 1:
1522 subtype = "Funnel, router";
1523 break;
1524 case 2:
1525 subtype = "Filter";
1526 break;
1527 case 3:
1528 subtype = "FIFO, buffer";
1529 break;
1530 }
1531 break;
1532 case 3:
1533 major = "Trace Source";
1534 switch (minor) {
1535 case 0:
1536 subtype = "other";
1537 break;
1538 case 1:
1539 subtype = "Processor";
1540 break;
1541 case 2:
1542 subtype = "DSP";
1543 break;
1544 case 3:
1545 subtype = "Engine/Coprocessor";
1546 break;
1547 case 4:
1548 subtype = "Bus";
1549 break;
1550 }
1551 break;
1552 case 4:
1553 major = "Debug Control";
1554 switch (minor) {
1555 case 0:
1556 subtype = "other";
1557 break;
1558 case 1:
1559 subtype = "Trigger Matrix";
1560 break;
1561 case 2:
1562 subtype = "Debug Auth";
1563 break;
1564 }
1565 break;
1566 case 5:
1567 major = "Debug Logic";
1568 switch (minor) {
1569 case 0:
1570 subtype = "other";
1571 break;
1572 case 1:
1573 subtype = "Processor";
1574 break;
1575 case 2:
1576 subtype = "DSP";
1577 break;
1578 case 3:
1579 subtype = "Engine/Coprocessor";
1580 break;
1581 }
1582 break;
1583 }
1584 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1585 (unsigned) (devtype & 0xff),
1586 major, subtype);
1587 /* REVISIT also show 0xfc8 DevId */
1588 }
1589
1590 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1591 command_print(cmd_ctx,
1592 "\t\tCID3 0%2.2x"
1593 ", CID2 0%2.2x"
1594 ", CID1 0%2.2x"
1595 ", CID0 0%2.2x",
1596 (int) c_cid3,
1597 (int) c_cid2,
1598 (int)c_cid1,
1599 (int)c_cid0);
1600 command_print(cmd_ctx,
1601 "\t\tPeripheral ID[4..0] = hex "
1602 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1603 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1604 (int) c_pid1, (int) c_pid0);
1605
1606 /* Part number interpretations are from Cortex
1607 * core specs, the CoreSight components TRM
1608 * (ARM DDI 0314H), CoreSight System Design
1609 * Guide (ARM DGI 0012D) and ETM specs; also
1610 * from chip observation (e.g. TI SDTI).
1611 */
1612 part_num = (c_pid0 & 0xff);
1613 part_num |= (c_pid1 & 0x0f) << 8;
1614 switch (part_num) {
1615 case 0x000:
1616 type = "Cortex-M3 NVIC";
1617 full = "(Interrupt Controller)";
1618 break;
1619 case 0x001:
1620 type = "Cortex-M3 ITM";
1621 full = "(Instrumentation Trace Module)";
1622 break;
1623 case 0x002:
1624 type = "Cortex-M3 DWT";
1625 full = "(Data Watchpoint and Trace)";
1626 break;
1627 case 0x003:
1628 type = "Cortex-M3 FBP";
1629 full = "(Flash Patch and Breakpoint)";
1630 break;
1631 case 0x00c:
1632 type = "Cortex-M4 SCS";
1633 full = "(System Control Space)";
1634 break;
1635 case 0x00d:
1636 type = "CoreSight ETM11";
1637 full = "(Embedded Trace)";
1638 break;
1639 /* case 0x113: what? */
1640 case 0x120: /* from OMAP3 memmap */
1641 type = "TI SDTI";
1642 full = "(System Debug Trace Interface)";
1643 break;
1644 case 0x343: /* from OMAP3 memmap */
1645 type = "TI DAPCTL";
1646 full = "";
1647 break;
1648 case 0x906:
1649 type = "Coresight CTI";
1650 full = "(Cross Trigger)";
1651 break;
1652 case 0x907:
1653 type = "Coresight ETB";
1654 full = "(Trace Buffer)";
1655 break;
1656 case 0x908:
1657 type = "Coresight CSTF";
1658 full = "(Trace Funnel)";
1659 break;
1660 case 0x910:
1661 type = "CoreSight ETM9";
1662 full = "(Embedded Trace)";
1663 break;
1664 case 0x912:
1665 type = "Coresight TPIU";
1666 full = "(Trace Port Interface Unit)";
1667 break;
1668 case 0x921:
1669 type = "Cortex-A8 ETM";
1670 full = "(Embedded Trace)";
1671 break;
1672 case 0x922:
1673 type = "Cortex-A8 CTI";
1674 full = "(Cross Trigger)";
1675 break;
1676 case 0x923:
1677 type = "Cortex-M3 TPIU";
1678 full = "(Trace Port Interface Unit)";
1679 break;
1680 case 0x924:
1681 type = "Cortex-M3 ETM";
1682 full = "(Embedded Trace)";
1683 break;
1684 case 0x925:
1685 type = "Cortex-M4 ETM";
1686 full = "(Embedded Trace)";
1687 break;
1688 case 0x930:
1689 type = "Cortex-R4 ETM";
1690 full = "(Embedded Trace)";
1691 break;
1692 case 0x9a1:
1693 type = "Cortex-M4 TPUI";
1694 full = "(Trace Port Interface Unit)";
1695 break;
1696 case 0xc08:
1697 type = "Cortex-A8 Debug";
1698 full = "(Debug Unit)";
1699 break;
1700 default:
1701 type = "-*- unrecognized -*-";
1702 full = "";
1703 break;
1704 }
1705 command_print(cmd_ctx, "\t\tPart is %s %s",
1706 type, full);
1707 } else {
1708 if (romentry)
1709 command_print(cmd_ctx, "\t\tComponent not present");
1710 else
1711 command_print(cmd_ctx, "\t\tEnd of ROM table");
1712 }
1713 entry_offset += 4;
1714 } while (romentry > 0);
1715 } else
1716 command_print(cmd_ctx, "\tNo ROM table present");
1717 dap_ap_select(dap, ap_old);
1718
1719 return ERROR_OK;
1720 }
1721
1722 COMMAND_HANDLER(handle_dap_info_command)
1723 {
1724 struct target *target = get_current_target(CMD_CTX);
1725 struct arm *arm = target_to_arm(target);
1726 struct adiv5_dap *dap = arm->dap;
1727 uint32_t apsel;
1728
1729 switch (CMD_ARGC) {
1730 case 0:
1731 apsel = dap->apsel;
1732 break;
1733 case 1:
1734 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1735 break;
1736 default:
1737 return ERROR_COMMAND_SYNTAX_ERROR;
1738 }
1739
1740 return dap_info_command(CMD_CTX, dap, apsel);
1741 }
1742
1743 COMMAND_HANDLER(dap_baseaddr_command)
1744 {
1745 struct target *target = get_current_target(CMD_CTX);
1746 struct arm *arm = target_to_arm(target);
1747 struct adiv5_dap *dap = arm->dap;
1748
1749 uint32_t apsel, baseaddr;
1750 int retval;
1751
1752 switch (CMD_ARGC) {
1753 case 0:
1754 apsel = dap->apsel;
1755 break;
1756 case 1:
1757 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1758 /* AP address is in bits 31:24 of DP_SELECT */
1759 if (apsel >= 256)
1760 return ERROR_COMMAND_SYNTAX_ERROR;
1761 break;
1762 default:
1763 return ERROR_COMMAND_SYNTAX_ERROR;
1764 }
1765
1766 dap_ap_select(dap, apsel);
1767
1768 /* NOTE: assumes we're talking to a MEM-AP, which
1769 * has a base address. There are other kinds of AP,
1770 * though they're not common for now. This should
1771 * use the ID register to verify it's a MEM-AP.
1772 */
1773 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1774 if (retval != ERROR_OK)
1775 return retval;
1776 retval = dap_run(dap);
1777 if (retval != ERROR_OK)
1778 return retval;
1779
1780 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1781
1782 return retval;
1783 }
1784
1785 COMMAND_HANDLER(dap_memaccess_command)
1786 {
1787 struct target *target = get_current_target(CMD_CTX);
1788 struct arm *arm = target_to_arm(target);
1789 struct adiv5_dap *dap = arm->dap;
1790
1791 uint32_t memaccess_tck;
1792
1793 switch (CMD_ARGC) {
1794 case 0:
1795 memaccess_tck = dap->memaccess_tck;
1796 break;
1797 case 1:
1798 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1799 break;
1800 default:
1801 return ERROR_COMMAND_SYNTAX_ERROR;
1802 }
1803 dap->memaccess_tck = memaccess_tck;
1804
1805 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1806 dap->memaccess_tck);
1807
1808 return ERROR_OK;
1809 }
1810
1811 COMMAND_HANDLER(dap_apsel_command)
1812 {
1813 struct target *target = get_current_target(CMD_CTX);
1814 struct arm *arm = target_to_arm(target);
1815 struct adiv5_dap *dap = arm->dap;
1816
1817 uint32_t apsel, apid;
1818 int retval;
1819
1820 switch (CMD_ARGC) {
1821 case 0:
1822 apsel = 0;
1823 break;
1824 case 1:
1825 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1826 /* AP address is in bits 31:24 of DP_SELECT */
1827 if (apsel >= 256)
1828 return ERROR_COMMAND_SYNTAX_ERROR;
1829 break;
1830 default:
1831 return ERROR_COMMAND_SYNTAX_ERROR;
1832 }
1833
1834 dap->apsel = apsel;
1835 dap_ap_select(dap, apsel);
1836
1837 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1838 if (retval != ERROR_OK)
1839 return retval;
1840 retval = dap_run(dap);
1841 if (retval != ERROR_OK)
1842 return retval;
1843
1844 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1845 apsel, apid);
1846
1847 return retval;
1848 }
1849
1850 COMMAND_HANDLER(dap_apid_command)
1851 {
1852 struct target *target = get_current_target(CMD_CTX);
1853 struct arm *arm = target_to_arm(target);
1854 struct adiv5_dap *dap = arm->dap;
1855
1856 uint32_t apsel, apid;
1857 int retval;
1858
1859 switch (CMD_ARGC) {
1860 case 0:
1861 apsel = dap->apsel;
1862 break;
1863 case 1:
1864 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1865 /* AP address is in bits 31:24 of DP_SELECT */
1866 if (apsel >= 256)
1867 return ERROR_COMMAND_SYNTAX_ERROR;
1868 break;
1869 default:
1870 return ERROR_COMMAND_SYNTAX_ERROR;
1871 }
1872
1873 dap_ap_select(dap, apsel);
1874
1875 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1876 if (retval != ERROR_OK)
1877 return retval;
1878 retval = dap_run(dap);
1879 if (retval != ERROR_OK)
1880 return retval;
1881
1882 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1883
1884 return retval;
1885 }
1886
1887 static const struct command_registration dap_commands[] = {
1888 {
1889 .name = "info",
1890 .handler = handle_dap_info_command,
1891 .mode = COMMAND_EXEC,
1892 .help = "display ROM table for MEM-AP "
1893 "(default currently selected AP)",
1894 .usage = "[ap_num]",
1895 },
1896 {
1897 .name = "apsel",
1898 .handler = dap_apsel_command,
1899 .mode = COMMAND_EXEC,
1900 .help = "Set the currently selected AP (default 0) "
1901 "and display the result",
1902 .usage = "[ap_num]",
1903 },
1904 {
1905 .name = "apid",
1906 .handler = dap_apid_command,
1907 .mode = COMMAND_EXEC,
1908 .help = "return ID register from AP "
1909 "(default currently selected AP)",
1910 .usage = "[ap_num]",
1911 },
1912 {
1913 .name = "baseaddr",
1914 .handler = dap_baseaddr_command,
1915 .mode = COMMAND_EXEC,
1916 .help = "return debug base address from MEM-AP "
1917 "(default currently selected AP)",
1918 .usage = "[ap_num]",
1919 },
1920 {
1921 .name = "memaccess",
1922 .handler = dap_memaccess_command,
1923 .mode = COMMAND_EXEC,
1924 .help = "set/get number of extra tck for MEM-AP memory "
1925 "bus access [0-255]",
1926 .usage = "[cycles]",
1927 },
1928 COMMAND_REGISTRATION_DONE
1929 };
1930
1931 const struct command_registration dap_command_handlers[] = {
1932 {
1933 .name = "dap",
1934 .mode = COMMAND_EXEC,
1935 .help = "DAP command group",
1936 .usage = "",
1937 .chain = dap_commands,
1938 },
1939 COMMAND_REGISTRATION_DONE
1940 };
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