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arm_adi_v5: Add ability to ignore the CSYSPWRUPACK bit
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79 #include <helper/jim-nvp.h>
80
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
82
83 /*
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 */
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 {
89 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
90 }
91
92 /***************************************************************************
93 * *
94 * DP and MEM-AP register access through APACC and DPACC *
95 * *
96 ***************************************************************************/
97
98 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 {
100 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
101 ap->csw_default;
102
103 if (csw != ap->csw_value) {
104 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
105 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
106 if (retval != ERROR_OK)
107 return retval;
108 ap->csw_value = csw;
109 }
110 return ERROR_OK;
111 }
112
113 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
114 {
115 if (!ap->tar_valid || tar != ap->tar_value) {
116 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
117 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
118 if (retval != ERROR_OK)
119 return retval;
120 ap->tar_value = tar;
121 ap->tar_valid = true;
122 }
123 return ERROR_OK;
124 }
125
126 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
127 {
128 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
129 if (retval != ERROR_OK) {
130 ap->tar_valid = false;
131 return retval;
132 }
133
134 retval = dap_run(ap->dap);
135 if (retval != ERROR_OK) {
136 ap->tar_valid = false;
137 return retval;
138 }
139
140 ap->tar_value = *tar;
141 ap->tar_valid = true;
142 return ERROR_OK;
143 }
144
145 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
146 {
147 switch (ap->csw_value & CSW_ADDRINC_MASK) {
148 case CSW_ADDRINC_SINGLE:
149 switch (ap->csw_value & CSW_SIZE_MASK) {
150 case CSW_8BIT:
151 return 1;
152 case CSW_16BIT:
153 return 2;
154 case CSW_32BIT:
155 return 4;
156 }
157 case CSW_ADDRINC_PACKED:
158 return 4;
159 }
160 return 0;
161 }
162
163 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
164 */
165 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
166 {
167 if (!ap->tar_valid)
168 return;
169
170 uint32_t inc = mem_ap_get_tar_increment(ap);
171 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
172 ap->tar_valid = false;
173 else
174 ap->tar_value += inc;
175 }
176
177 /**
178 * Queue transactions setting up transfer parameters for the
179 * currently selected MEM-AP.
180 *
181 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
182 * initiate data reads or writes using memory or peripheral addresses.
183 * If the CSW is configured for it, the TAR may be automatically
184 * incremented after each transfer.
185 *
186 * @param ap The MEM-AP.
187 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
188 * matches the cached value, the register is not changed.
189 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
190 * matches the cached address, the register is not changed.
191 *
192 * @return ERROR_OK if the transaction was properly queued, else a fault code.
193 */
194 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
195 {
196 int retval;
197 retval = mem_ap_setup_csw(ap, csw);
198 if (retval != ERROR_OK)
199 return retval;
200 retval = mem_ap_setup_tar(ap, tar);
201 if (retval != ERROR_OK)
202 return retval;
203 return ERROR_OK;
204 }
205
206 /**
207 * Asynchronous (queued) read of a word from memory or a system register.
208 *
209 * @param ap The MEM-AP to access.
210 * @param address Address of the 32-bit word to read; it must be
211 * readable by the currently selected MEM-AP.
212 * @param value points to where the word will be stored when the
213 * transaction queue is flushed (assuming no errors).
214 *
215 * @return ERROR_OK for success. Otherwise a fault code.
216 */
217 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
218 uint32_t *value)
219 {
220 int retval;
221
222 /* Use banked addressing (REG_BDx) to avoid some link traffic
223 * (updating TAR) when reading several consecutive addresses.
224 */
225 retval = mem_ap_setup_transfer(ap,
226 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
227 address & 0xFFFFFFF0);
228 if (retval != ERROR_OK)
229 return retval;
230
231 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
232 }
233
234 /**
235 * Synchronous read of a word from memory or a system register.
236 * As a side effect, this flushes any queued transactions.
237 *
238 * @param ap The MEM-AP to access.
239 * @param address Address of the 32-bit word to read; it must be
240 * readable by the currently selected MEM-AP.
241 * @param value points to where the result will be stored.
242 *
243 * @return ERROR_OK for success; *value holds the result.
244 * Otherwise a fault code.
245 */
246 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
247 uint32_t *value)
248 {
249 int retval;
250
251 retval = mem_ap_read_u32(ap, address, value);
252 if (retval != ERROR_OK)
253 return retval;
254
255 return dap_run(ap->dap);
256 }
257
258 /**
259 * Asynchronous (queued) write of a word to memory or a system register.
260 *
261 * @param ap The MEM-AP to access.
262 * @param address Address to be written; it must be writable by
263 * the currently selected MEM-AP.
264 * @param value Word that will be written to the address when transaction
265 * queue is flushed (assuming no errors).
266 *
267 * @return ERROR_OK for success. Otherwise a fault code.
268 */
269 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
270 uint32_t value)
271 {
272 int retval;
273
274 /* Use banked addressing (REG_BDx) to avoid some link traffic
275 * (updating TAR) when writing several consecutive addresses.
276 */
277 retval = mem_ap_setup_transfer(ap,
278 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
279 address & 0xFFFFFFF0);
280 if (retval != ERROR_OK)
281 return retval;
282
283 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
284 value);
285 }
286
287 /**
288 * Synchronous write of a word to memory or a system register.
289 * As a side effect, this flushes any queued transactions.
290 *
291 * @param ap The MEM-AP to access.
292 * @param address Address to be written; it must be writable by
293 * the currently selected MEM-AP.
294 * @param value Word that will be written.
295 *
296 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
297 */
298 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
299 uint32_t value)
300 {
301 int retval = mem_ap_write_u32(ap, address, value);
302
303 if (retval != ERROR_OK)
304 return retval;
305
306 return dap_run(ap->dap);
307 }
308
309 /**
310 * Synchronous write of a block of memory, using a specific access size.
311 *
312 * @param ap The MEM-AP to access.
313 * @param buffer The data buffer to write. No particular alignment is assumed.
314 * @param size Which access size to use, in bytes. 1, 2 or 4.
315 * @param count The number of writes to do (in size units, not bytes).
316 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
317 * @param addrinc Whether the target address should be increased for each write or not. This
318 * should normally be true, except when writing to e.g. a FIFO.
319 * @return ERROR_OK on success, otherwise an error code.
320 */
321 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
322 uint32_t address, bool addrinc)
323 {
324 struct adiv5_dap *dap = ap->dap;
325 size_t nbytes = size * count;
326 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
327 uint32_t csw_size;
328 uint32_t addr_xor;
329 int retval = ERROR_OK;
330
331 /* TI BE-32 Quirks mode:
332 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
333 * size write address bytes written in order
334 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
335 * 2 TAR ^ 2 (val >> 8), (val)
336 * 1 TAR ^ 3 (val)
337 * For example, if you attempt to write a single byte to address 0, the processor
338 * will actually write a byte to address 3.
339 *
340 * To make writes of size < 4 work as expected, we xor a value with the address before
341 * setting the TAP, and we set the TAP after every transfer rather then relying on
342 * address increment. */
343
344 if (size == 4) {
345 csw_size = CSW_32BIT;
346 addr_xor = 0;
347 } else if (size == 2) {
348 csw_size = CSW_16BIT;
349 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
350 } else if (size == 1) {
351 csw_size = CSW_8BIT;
352 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
353 } else {
354 return ERROR_TARGET_UNALIGNED_ACCESS;
355 }
356
357 if (ap->unaligned_access_bad && (address % size != 0))
358 return ERROR_TARGET_UNALIGNED_ACCESS;
359
360 while (nbytes > 0) {
361 uint32_t this_size = size;
362
363 /* Select packed transfer if possible */
364 if (addrinc && ap->packed_transfers && nbytes >= 4
365 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
366 this_size = 4;
367 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
368 } else {
369 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
370 }
371
372 if (retval != ERROR_OK)
373 break;
374
375 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
376 if (retval != ERROR_OK)
377 return retval;
378
379 /* How many source bytes each transfer will consume, and their location in the DRW,
380 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
381 uint32_t outvalue = 0;
382 uint32_t drw_byte_idx = address;
383 if (dap->ti_be_32_quirks) {
384 switch (this_size) {
385 case 4:
386 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
387 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
388 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
389 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
390 break;
391 case 2:
392 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
393 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
394 break;
395 case 1:
396 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
397 break;
398 }
399 } else {
400 switch (this_size) {
401 case 4:
402 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
403 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
404 /* fallthrough */
405 case 2:
406 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
407 /* fallthrough */
408 case 1:
409 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
410 }
411 }
412
413 nbytes -= this_size;
414
415 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
416 if (retval != ERROR_OK)
417 break;
418
419 mem_ap_update_tar_cache(ap);
420 if (addrinc)
421 address += this_size;
422 }
423
424 /* REVISIT: Might want to have a queued version of this function that does not run. */
425 if (retval == ERROR_OK)
426 retval = dap_run(dap);
427
428 if (retval != ERROR_OK) {
429 uint32_t tar;
430 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
431 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
432 else
433 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
434 }
435
436 return retval;
437 }
438
439 /**
440 * Synchronous read of a block of memory, using a specific access size.
441 *
442 * @param ap The MEM-AP to access.
443 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
444 * @param size Which access size to use, in bytes. 1, 2 or 4.
445 * @param count The number of reads to do (in size units, not bytes).
446 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
447 * @param addrinc Whether the target address should be increased after each read or not. This
448 * should normally be true, except when reading from e.g. a FIFO.
449 * @return ERROR_OK on success, otherwise an error code.
450 */
451 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
452 uint32_t adr, bool addrinc)
453 {
454 struct adiv5_dap *dap = ap->dap;
455 size_t nbytes = size * count;
456 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
457 uint32_t csw_size;
458 uint32_t address = adr;
459 int retval = ERROR_OK;
460
461 /* TI BE-32 Quirks mode:
462 * Reads on big-endian TMS570 behave strangely differently than writes.
463 * They read from the physical address requested, but with DRW byte-reversed.
464 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
465 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
466 * so avoid them. */
467
468 if (size == 4)
469 csw_size = CSW_32BIT;
470 else if (size == 2)
471 csw_size = CSW_16BIT;
472 else if (size == 1)
473 csw_size = CSW_8BIT;
474 else
475 return ERROR_TARGET_UNALIGNED_ACCESS;
476
477 if (ap->unaligned_access_bad && (adr % size != 0))
478 return ERROR_TARGET_UNALIGNED_ACCESS;
479
480 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
481 * over-allocation if packed transfers are going to be used, but determining the real need at
482 * this point would be messy. */
483 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
484 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
485 uint32_t *read_ptr = read_buf;
486 if (read_buf == NULL) {
487 LOG_ERROR("Failed to allocate read buffer");
488 return ERROR_FAIL;
489 }
490
491 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
492 * useful bytes it contains, and their location in the word, depends on the type of transfer
493 * and alignment. */
494 while (nbytes > 0) {
495 uint32_t this_size = size;
496
497 /* Select packed transfer if possible */
498 if (addrinc && ap->packed_transfers && nbytes >= 4
499 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
500 this_size = 4;
501 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
502 } else {
503 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
504 }
505 if (retval != ERROR_OK)
506 break;
507
508 retval = mem_ap_setup_tar(ap, address);
509 if (retval != ERROR_OK)
510 break;
511
512 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
513 if (retval != ERROR_OK)
514 break;
515
516 nbytes -= this_size;
517 if (addrinc)
518 address += this_size;
519
520 mem_ap_update_tar_cache(ap);
521 }
522
523 if (retval == ERROR_OK)
524 retval = dap_run(dap);
525
526 /* Restore state */
527 address = adr;
528 nbytes = size * count;
529 read_ptr = read_buf;
530
531 /* If something failed, read TAR to find out how much data was successfully read, so we can
532 * at least give the caller what we have. */
533 if (retval != ERROR_OK) {
534 uint32_t tar;
535 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
536 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
537 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
538 if (nbytes > tar - address)
539 nbytes = tar - address;
540 } else {
541 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
542 nbytes = 0;
543 }
544 }
545
546 /* Replay loop to populate caller's buffer from the correct word and byte lane */
547 while (nbytes > 0) {
548 uint32_t this_size = size;
549
550 if (addrinc && ap->packed_transfers && nbytes >= 4
551 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
552 this_size = 4;
553 }
554
555 if (dap->ti_be_32_quirks) {
556 switch (this_size) {
557 case 4:
558 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
559 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
560 /* fallthrough */
561 case 2:
562 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
563 /* fallthrough */
564 case 1:
565 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
566 }
567 } else {
568 switch (this_size) {
569 case 4:
570 *buffer++ = *read_ptr >> 8 * (address++ & 3);
571 *buffer++ = *read_ptr >> 8 * (address++ & 3);
572 /* fallthrough */
573 case 2:
574 *buffer++ = *read_ptr >> 8 * (address++ & 3);
575 /* fallthrough */
576 case 1:
577 *buffer++ = *read_ptr >> 8 * (address++ & 3);
578 }
579 }
580
581 read_ptr++;
582 nbytes -= this_size;
583 }
584
585 free(read_buf);
586 return retval;
587 }
588
589 int mem_ap_read_buf(struct adiv5_ap *ap,
590 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
591 {
592 return mem_ap_read(ap, buffer, size, count, address, true);
593 }
594
595 int mem_ap_write_buf(struct adiv5_ap *ap,
596 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
597 {
598 return mem_ap_write(ap, buffer, size, count, address, true);
599 }
600
601 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
602 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
603 {
604 return mem_ap_read(ap, buffer, size, count, address, false);
605 }
606
607 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
608 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
609 {
610 return mem_ap_write(ap, buffer, size, count, address, false);
611 }
612
613 /*--------------------------------------------------------------------------*/
614
615
616 #define DAP_POWER_DOMAIN_TIMEOUT (10)
617
618 /*--------------------------------------------------------------------------*/
619
620 /**
621 * Invalidate cached DP select and cached TAR and CSW of all APs
622 */
623 void dap_invalidate_cache(struct adiv5_dap *dap)
624 {
625 dap->select = DP_SELECT_INVALID;
626 dap->last_read = NULL;
627
628 int i;
629 for (i = 0; i <= 255; i++) {
630 /* force csw and tar write on the next mem-ap access */
631 dap->ap[i].tar_valid = false;
632 dap->ap[i].csw_value = 0;
633 }
634 }
635
636 /**
637 * Initialize a DAP. This sets up the power domains, prepares the DP
638 * for further use and activates overrun checking.
639 *
640 * @param dap The DAP being initialized.
641 */
642 int dap_dp_init(struct adiv5_dap *dap)
643 {
644 int retval;
645
646 LOG_DEBUG("%s", adiv5_dap_name(dap));
647
648 dap_invalidate_cache(dap);
649
650 for (size_t i = 0; i < 30; i++) {
651 /* DP initialization */
652
653 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
654 if (retval == ERROR_OK)
655 break;
656 }
657
658 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
659 if (retval != ERROR_OK)
660 return retval;
661
662 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
663 if (retval != ERROR_OK)
664 return retval;
665
666 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
667 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
668 if (retval != ERROR_OK)
669 return retval;
670
671 /* Check that we have debug power domains activated */
672 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
673 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
674 CDBGPWRUPACK, CDBGPWRUPACK,
675 DAP_POWER_DOMAIN_TIMEOUT);
676 if (retval != ERROR_OK)
677 return retval;
678
679 if (!dap->ignore_syspwrupack) {
680 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
681 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
682 CSYSPWRUPACK, CSYSPWRUPACK,
683 DAP_POWER_DOMAIN_TIMEOUT);
684 if (retval != ERROR_OK)
685 return retval;
686 }
687
688 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
689 if (retval != ERROR_OK)
690 return retval;
691
692 /* With debug power on we can activate OVERRUN checking */
693 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
694 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
695 if (retval != ERROR_OK)
696 return retval;
697 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
698 if (retval != ERROR_OK)
699 return retval;
700
701 retval = dap_run(dap);
702 if (retval != ERROR_OK)
703 return retval;
704
705 return retval;
706 }
707
708 /**
709 * Initialize a DAP. This sets up the power domains, prepares the DP
710 * for further use, and arranges to use AP #0 for all AP operations
711 * until dap_ap-select() changes that policy.
712 *
713 * @param ap The MEM-AP being initialized.
714 */
715 int mem_ap_init(struct adiv5_ap *ap)
716 {
717 /* check that we support packed transfers */
718 uint32_t csw, cfg;
719 int retval;
720 struct adiv5_dap *dap = ap->dap;
721
722 ap->tar_valid = false;
723 ap->csw_value = 0; /* force csw and tar write */
724 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
725 if (retval != ERROR_OK)
726 return retval;
727
728 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
729 if (retval != ERROR_OK)
730 return retval;
731
732 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
733 if (retval != ERROR_OK)
734 return retval;
735
736 retval = dap_run(dap);
737 if (retval != ERROR_OK)
738 return retval;
739
740 if (csw & CSW_ADDRINC_PACKED)
741 ap->packed_transfers = true;
742 else
743 ap->packed_transfers = false;
744
745 /* Packed transfers on TI BE-32 processors do not work correctly in
746 * many cases. */
747 if (dap->ti_be_32_quirks)
748 ap->packed_transfers = false;
749
750 LOG_DEBUG("MEM_AP Packed Transfers: %s",
751 ap->packed_transfers ? "enabled" : "disabled");
752
753 /* The ARM ADI spec leaves implementation-defined whether unaligned
754 * memory accesses work, only work partially, or cause a sticky error.
755 * On TI BE-32 processors, reads seem to return garbage in some bytes
756 * and unaligned writes seem to cause a sticky error.
757 * TODO: it would be nice to have a way to detect whether unaligned
758 * operations are supported on other processors. */
759 ap->unaligned_access_bad = dap->ti_be_32_quirks;
760
761 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
762 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
763
764 return ERROR_OK;
765 }
766
767 /* CID interpretation -- see ARM IHI 0029B section 3
768 * and ARM IHI 0031A table 13-3.
769 */
770 static const char *class_description[16] = {
771 "Reserved", "ROM table", "Reserved", "Reserved",
772 "Reserved", "Reserved", "Reserved", "Reserved",
773 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
774 "Reserved", "OptimoDE DESS",
775 "Generic IP component", "PrimeCell or System component"
776 };
777
778 static bool is_dap_cid_ok(uint32_t cid)
779 {
780 return (cid & 0xffff0fff) == 0xb105000d;
781 }
782
783 /*
784 * This function checks the ID for each access port to find the requested Access Port type
785 */
786 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
787 {
788 int ap_num;
789
790 /* Maximum AP number is 255 since the SELECT register is 8 bits */
791 for (ap_num = 0; ap_num <= 255; ap_num++) {
792
793 /* read the IDR register of the Access Port */
794 uint32_t id_val = 0;
795
796 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
797 if (retval != ERROR_OK)
798 return retval;
799
800 retval = dap_run(dap);
801
802 /* IDR bits:
803 * 31-28 : Revision
804 * 27-24 : JEDEC bank (0x4 for ARM)
805 * 23-17 : JEDEC code (0x3B for ARM)
806 * 16-13 : Class (0b1000=Mem-AP)
807 * 12-8 : Reserved
808 * 7-4 : AP Variant (non-zero for JTAG-AP)
809 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
810 */
811
812 /* Reading register for a non-existant AP should not cause an error,
813 * but just to be sure, try to continue searching if an error does happen.
814 */
815 if ((retval == ERROR_OK) && /* Register read success */
816 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
817 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
818
819 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
820 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
821 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
822 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
823 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
824 ap_num, id_val);
825
826 *ap_out = &dap->ap[ap_num];
827 return ERROR_OK;
828 }
829 }
830
831 LOG_DEBUG("No %s found",
832 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
833 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
834 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
835 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
836 return ERROR_FAIL;
837 }
838
839 int dap_get_debugbase(struct adiv5_ap *ap,
840 uint32_t *dbgbase, uint32_t *apid)
841 {
842 struct adiv5_dap *dap = ap->dap;
843 int retval;
844
845 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
846 if (retval != ERROR_OK)
847 return retval;
848 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
849 if (retval != ERROR_OK)
850 return retval;
851 retval = dap_run(dap);
852 if (retval != ERROR_OK)
853 return retval;
854
855 return ERROR_OK;
856 }
857
858 int dap_lookup_cs_component(struct adiv5_ap *ap,
859 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
860 {
861 uint32_t romentry, entry_offset = 0, component_base, devtype;
862 int retval;
863
864 *addr = 0;
865
866 do {
867 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
868 entry_offset, &romentry);
869 if (retval != ERROR_OK)
870 return retval;
871
872 component_base = (dbgbase & 0xFFFFF000)
873 + (romentry & 0xFFFFF000);
874
875 if (romentry & 0x1) {
876 uint32_t c_cid1;
877 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
878 if (retval != ERROR_OK) {
879 LOG_ERROR("Can't read component with base address 0x%" PRIx32
880 ", the corresponding core might be turned off", component_base);
881 return retval;
882 }
883 if (((c_cid1 >> 4) & 0x0f) == 1) {
884 retval = dap_lookup_cs_component(ap, component_base,
885 type, addr, idx);
886 if (retval == ERROR_OK)
887 break;
888 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
889 return retval;
890 }
891
892 retval = mem_ap_read_atomic_u32(ap,
893 (component_base & 0xfffff000) | 0xfcc,
894 &devtype);
895 if (retval != ERROR_OK)
896 return retval;
897 if ((devtype & 0xff) == type) {
898 if (!*idx) {
899 *addr = component_base;
900 break;
901 } else
902 (*idx)--;
903 }
904 }
905 entry_offset += 4;
906 } while (romentry > 0);
907
908 if (!*addr)
909 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
910
911 return ERROR_OK;
912 }
913
914 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
915 {
916 assert((component_base & 0xFFF) == 0);
917 assert(ap != NULL && cid != NULL && pid != NULL);
918
919 uint32_t cid0, cid1, cid2, cid3;
920 uint32_t pid0, pid1, pid2, pid3, pid4;
921 int retval;
922
923 /* IDs are in last 4K section */
924 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
925 if (retval != ERROR_OK)
926 return retval;
927 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
928 if (retval != ERROR_OK)
929 return retval;
930 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
931 if (retval != ERROR_OK)
932 return retval;
933 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
934 if (retval != ERROR_OK)
935 return retval;
936 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
937 if (retval != ERROR_OK)
938 return retval;
939 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
940 if (retval != ERROR_OK)
941 return retval;
942 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
943 if (retval != ERROR_OK)
944 return retval;
945 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
946 if (retval != ERROR_OK)
947 return retval;
948 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
949 if (retval != ERROR_OK)
950 return retval;
951
952 retval = dap_run(ap->dap);
953 if (retval != ERROR_OK)
954 return retval;
955
956 *cid = (cid3 & 0xff) << 24
957 | (cid2 & 0xff) << 16
958 | (cid1 & 0xff) << 8
959 | (cid0 & 0xff);
960 *pid = (uint64_t)(pid4 & 0xff) << 32
961 | (pid3 & 0xff) << 24
962 | (pid2 & 0xff) << 16
963 | (pid1 & 0xff) << 8
964 | (pid0 & 0xff);
965
966 return ERROR_OK;
967 }
968
969 /* The designer identity code is encoded as:
970 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
971 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
972 * a legacy ASCII Identity Code.
973 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
974 * JEP106 is a standard available from jedec.org
975 */
976
977 /* Part number interpretations are from Cortex
978 * core specs, the CoreSight components TRM
979 * (ARM DDI 0314H), CoreSight System Design
980 * Guide (ARM DGI 0012D) and ETM specs; also
981 * from chip observation (e.g. TI SDTI).
982 */
983
984 /* The legacy code only used the part number field to identify CoreSight peripherals.
985 * This meant that the same part number from two different manufacturers looked the same.
986 * It is desirable for all future additions to identify with both part number and JEP106.
987 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
988 */
989
990 #define ANY_ID 0x1000
991
992 #define ARM_ID 0x4BB
993
994 static const struct {
995 uint16_t designer_id;
996 uint16_t part_num;
997 const char *type;
998 const char *full;
999 } dap_partnums[] = {
1000 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1001 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1002 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1003 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1004 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1005 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1006 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1007 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1008 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1009 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1010 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1011 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1012 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1013 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1014 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1015 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1016 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1017 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1018 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1019 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1020 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1021 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1022 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1023 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1024 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1025 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1026 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1027 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1028 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1029 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1030 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1031 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1032 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1033 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1034 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1035 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1036 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1037 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1038 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1039 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1040 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1041 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1042 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1043 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1044 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1045 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1046 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1047 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1048 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1049 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1050 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1051 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1052 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1053 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1054 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1055 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1056 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1057 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1058 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1059 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1060 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1061 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1062 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1063 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1064 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1065 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1066 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1067 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1068 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1069 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1070 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1071 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1072 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1073 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1074 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1075 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1076 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1077 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1078 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1079 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1080 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1081 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1082 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1083 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1084 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1085 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1086 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1087 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1088 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1089 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1090 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1091 /* legacy comment: 0x113: what? */
1092 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1093 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1094 };
1095
1096 static int dap_rom_display(struct command_context *cmd_ctx,
1097 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1098 {
1099 int retval;
1100 uint64_t pid;
1101 uint32_t cid;
1102 char tabs[16] = "";
1103
1104 if (depth > 16) {
1105 command_print(cmd_ctx, "\tTables too deep");
1106 return ERROR_FAIL;
1107 }
1108
1109 if (depth)
1110 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1111
1112 uint32_t base_addr = dbgbase & 0xFFFFF000;
1113 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1114
1115 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1116 if (retval != ERROR_OK) {
1117 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1118 return ERROR_OK; /* Don't abort recursion */
1119 }
1120
1121 if (!is_dap_cid_ok(cid)) {
1122 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1123 return ERROR_OK; /* Don't abort recursion */
1124 }
1125
1126 /* component may take multiple 4K pages */
1127 uint32_t size = (pid >> 36) & 0xf;
1128 if (size > 0)
1129 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1130
1131 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1132
1133 uint8_t class = (cid >> 12) & 0xf;
1134 uint16_t part_num = pid & 0xfff;
1135 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1136
1137 if (designer_id & 0x80) {
1138 /* JEP106 code */
1139 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1140 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1141 } else {
1142 /* Legacy ASCII ID, clear invalid bits */
1143 designer_id &= 0x7f;
1144 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1145 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1146 }
1147
1148 /* default values to be overwritten upon finding a match */
1149 const char *type = "Unrecognized";
1150 const char *full = "";
1151
1152 /* search dap_partnums[] array for a match */
1153 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1154
1155 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1156 continue;
1157
1158 if (dap_partnums[entry].part_num != part_num)
1159 continue;
1160
1161 type = dap_partnums[entry].type;
1162 full = dap_partnums[entry].full;
1163 break;
1164 }
1165
1166 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1167 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1168
1169 if (class == 1) { /* ROM Table */
1170 uint32_t memtype;
1171 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1172 if (retval != ERROR_OK)
1173 return retval;
1174
1175 if (memtype & 0x01)
1176 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1177 else
1178 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1179
1180 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1181 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1182 uint32_t romentry;
1183 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1184 if (retval != ERROR_OK)
1185 return retval;
1186 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1187 tabs, entry_offset, romentry);
1188 if (romentry & 0x01) {
1189 /* Recurse */
1190 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1191 if (retval != ERROR_OK)
1192 return retval;
1193 } else if (romentry != 0) {
1194 command_print(cmd_ctx, "\t\tComponent not present");
1195 } else {
1196 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1197 break;
1198 }
1199 }
1200 } else if (class == 9) { /* CoreSight component */
1201 const char *major = "Reserved", *subtype = "Reserved";
1202
1203 uint32_t devtype;
1204 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1205 if (retval != ERROR_OK)
1206 return retval;
1207 unsigned minor = (devtype >> 4) & 0x0f;
1208 switch (devtype & 0x0f) {
1209 case 0:
1210 major = "Miscellaneous";
1211 switch (minor) {
1212 case 0:
1213 subtype = "other";
1214 break;
1215 case 4:
1216 subtype = "Validation component";
1217 break;
1218 }
1219 break;
1220 case 1:
1221 major = "Trace Sink";
1222 switch (minor) {
1223 case 0:
1224 subtype = "other";
1225 break;
1226 case 1:
1227 subtype = "Port";
1228 break;
1229 case 2:
1230 subtype = "Buffer";
1231 break;
1232 case 3:
1233 subtype = "Router";
1234 break;
1235 }
1236 break;
1237 case 2:
1238 major = "Trace Link";
1239 switch (minor) {
1240 case 0:
1241 subtype = "other";
1242 break;
1243 case 1:
1244 subtype = "Funnel, router";
1245 break;
1246 case 2:
1247 subtype = "Filter";
1248 break;
1249 case 3:
1250 subtype = "FIFO, buffer";
1251 break;
1252 }
1253 break;
1254 case 3:
1255 major = "Trace Source";
1256 switch (minor) {
1257 case 0:
1258 subtype = "other";
1259 break;
1260 case 1:
1261 subtype = "Processor";
1262 break;
1263 case 2:
1264 subtype = "DSP";
1265 break;
1266 case 3:
1267 subtype = "Engine/Coprocessor";
1268 break;
1269 case 4:
1270 subtype = "Bus";
1271 break;
1272 case 6:
1273 subtype = "Software";
1274 break;
1275 }
1276 break;
1277 case 4:
1278 major = "Debug Control";
1279 switch (minor) {
1280 case 0:
1281 subtype = "other";
1282 break;
1283 case 1:
1284 subtype = "Trigger Matrix";
1285 break;
1286 case 2:
1287 subtype = "Debug Auth";
1288 break;
1289 case 3:
1290 subtype = "Power Requestor";
1291 break;
1292 }
1293 break;
1294 case 5:
1295 major = "Debug Logic";
1296 switch (minor) {
1297 case 0:
1298 subtype = "other";
1299 break;
1300 case 1:
1301 subtype = "Processor";
1302 break;
1303 case 2:
1304 subtype = "DSP";
1305 break;
1306 case 3:
1307 subtype = "Engine/Coprocessor";
1308 break;
1309 case 4:
1310 subtype = "Bus";
1311 break;
1312 case 5:
1313 subtype = "Memory";
1314 break;
1315 }
1316 break;
1317 case 6:
1318 major = "Perfomance Monitor";
1319 switch (minor) {
1320 case 0:
1321 subtype = "other";
1322 break;
1323 case 1:
1324 subtype = "Processor";
1325 break;
1326 case 2:
1327 subtype = "DSP";
1328 break;
1329 case 3:
1330 subtype = "Engine/Coprocessor";
1331 break;
1332 case 4:
1333 subtype = "Bus";
1334 break;
1335 case 5:
1336 subtype = "Memory";
1337 break;
1338 }
1339 break;
1340 }
1341 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1342 (uint8_t)(devtype & 0xff),
1343 major, subtype);
1344 /* REVISIT also show 0xfc8 DevId */
1345 }
1346
1347 return ERROR_OK;
1348 }
1349
1350 int dap_info_command(struct command_context *cmd_ctx,
1351 struct adiv5_ap *ap)
1352 {
1353 int retval;
1354 uint32_t dbgbase, apid;
1355 uint8_t mem_ap;
1356
1357 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1358 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1359 if (retval != ERROR_OK)
1360 return retval;
1361
1362 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1363 if (apid == 0) {
1364 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1365 return ERROR_FAIL;
1366 }
1367
1368 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1369 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1370 command_print(cmd_ctx, "\tType is JTAG-AP");
1371 break;
1372 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1373 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1374 break;
1375 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1376 command_print(cmd_ctx, "\tType is MEM-AP APB");
1377 break;
1378 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1379 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1380 break;
1381 default:
1382 command_print(cmd_ctx, "\tUnknown AP type");
1383 break;
1384 }
1385
1386 /* NOTE: a MEM-AP may have a single CoreSight component that's
1387 * not a ROM table ... or have no such components at all.
1388 */
1389 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1390 if (mem_ap) {
1391 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1392
1393 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1394 command_print(cmd_ctx, "\tNo ROM table present");
1395 } else {
1396 if (dbgbase & 0x01)
1397 command_print(cmd_ctx, "\tValid ROM table present");
1398 else
1399 command_print(cmd_ctx, "\tROM table in legacy format");
1400
1401 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1402 }
1403 }
1404
1405 return ERROR_OK;
1406 }
1407
1408 enum adiv5_cfg_param {
1409 CFG_DAP,
1410 CFG_AP_NUM
1411 };
1412
1413 static const Jim_Nvp nvp_config_opts[] = {
1414 { .name = "-dap", .value = CFG_DAP },
1415 { .name = "-ap-num", .value = CFG_AP_NUM },
1416 { .name = NULL, .value = -1 }
1417 };
1418
1419 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1420 {
1421 struct adiv5_private_config *pc;
1422 int e;
1423
1424 pc = (struct adiv5_private_config *)target->private_config;
1425 if (pc == NULL) {
1426 pc = calloc(1, sizeof(struct adiv5_private_config));
1427 pc->ap_num = -1;
1428 target->private_config = pc;
1429 }
1430
1431 target->has_dap = true;
1432
1433 if (goi->argc > 0) {
1434 Jim_Nvp *n;
1435
1436 Jim_SetEmptyResult(goi->interp);
1437
1438 /* check first if topmost item is for us */
1439 e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
1440 goi->argv[0], &n);
1441 if (e != JIM_OK)
1442 return JIM_CONTINUE;
1443
1444 e = Jim_GetOpt_Obj(goi, NULL);
1445 if (e != JIM_OK)
1446 return e;
1447
1448 switch (n->value) {
1449 case CFG_DAP:
1450 if (goi->isconfigure) {
1451 Jim_Obj *o_t;
1452 struct adiv5_dap *dap;
1453 e = Jim_GetOpt_Obj(goi, &o_t);
1454 if (e != JIM_OK)
1455 return e;
1456 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1457 if (dap == NULL) {
1458 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1459 return JIM_ERR;
1460 }
1461 if (pc->dap != NULL && pc->dap != dap) {
1462 Jim_SetResultString(goi->interp,
1463 "DAP assignment cannot be changed after target was created!", -1);
1464 return JIM_ERR;
1465 }
1466 if (target->tap_configured) {
1467 Jim_SetResultString(goi->interp,
1468 "-chain-position and -dap configparams are mutually exclusive!", -1);
1469 return JIM_ERR;
1470 }
1471 pc->dap = dap;
1472 target->tap = dap->tap;
1473 target->dap_configured = true;
1474 } else {
1475 if (goi->argc != 0) {
1476 Jim_WrongNumArgs(goi->interp,
1477 goi->argc, goi->argv,
1478 "NO PARAMS");
1479 return JIM_ERR;
1480 }
1481
1482 if (pc->dap == NULL) {
1483 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1484 return JIM_ERR;
1485 }
1486 Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1);
1487 }
1488 break;
1489
1490 case CFG_AP_NUM:
1491 if (goi->isconfigure) {
1492 jim_wide ap_num;
1493 e = Jim_GetOpt_Wide(goi, &ap_num);
1494 if (e != JIM_OK)
1495 return e;
1496 pc->ap_num = ap_num;
1497 } else {
1498 if (goi->argc != 0) {
1499 Jim_WrongNumArgs(goi->interp,
1500 goi->argc, goi->argv,
1501 "NO PARAMS");
1502 return JIM_ERR;
1503 }
1504
1505 if (pc->ap_num < 0) {
1506 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1507 return JIM_ERR;
1508 }
1509 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, (int)pc->ap_num));
1510 }
1511 break;
1512 }
1513 }
1514
1515 return JIM_OK;
1516 }
1517
1518 int adiv5_verify_config(struct adiv5_private_config *pc)
1519 {
1520 if (pc == NULL)
1521 return ERROR_FAIL;
1522
1523 if (pc->dap == NULL)
1524 return ERROR_FAIL;
1525
1526 return ERROR_OK;
1527 }
1528
1529
1530 COMMAND_HANDLER(handle_dap_info_command)
1531 {
1532 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1533 uint32_t apsel;
1534
1535 switch (CMD_ARGC) {
1536 case 0:
1537 apsel = dap->apsel;
1538 break;
1539 case 1:
1540 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1541 if (apsel >= 256)
1542 return ERROR_COMMAND_SYNTAX_ERROR;
1543 break;
1544 default:
1545 return ERROR_COMMAND_SYNTAX_ERROR;
1546 }
1547
1548 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1549 }
1550
1551 COMMAND_HANDLER(dap_baseaddr_command)
1552 {
1553 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1554 uint32_t apsel, baseaddr;
1555 int retval;
1556
1557 switch (CMD_ARGC) {
1558 case 0:
1559 apsel = dap->apsel;
1560 break;
1561 case 1:
1562 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1563 /* AP address is in bits 31:24 of DP_SELECT */
1564 if (apsel >= 256)
1565 return ERROR_COMMAND_SYNTAX_ERROR;
1566 break;
1567 default:
1568 return ERROR_COMMAND_SYNTAX_ERROR;
1569 }
1570
1571 /* NOTE: assumes we're talking to a MEM-AP, which
1572 * has a base address. There are other kinds of AP,
1573 * though they're not common for now. This should
1574 * use the ID register to verify it's a MEM-AP.
1575 */
1576 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1577 if (retval != ERROR_OK)
1578 return retval;
1579 retval = dap_run(dap);
1580 if (retval != ERROR_OK)
1581 return retval;
1582
1583 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1584
1585 return retval;
1586 }
1587
1588 COMMAND_HANDLER(dap_memaccess_command)
1589 {
1590 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1591 uint32_t memaccess_tck;
1592
1593 switch (CMD_ARGC) {
1594 case 0:
1595 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1596 break;
1597 case 1:
1598 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1599 break;
1600 default:
1601 return ERROR_COMMAND_SYNTAX_ERROR;
1602 }
1603 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1604
1605 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1606 dap->ap[dap->apsel].memaccess_tck);
1607
1608 return ERROR_OK;
1609 }
1610
1611 COMMAND_HANDLER(dap_apsel_command)
1612 {
1613 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1614 uint32_t apsel, apid;
1615 int retval;
1616
1617 switch (CMD_ARGC) {
1618 case 0:
1619 apsel = dap->apsel;
1620 break;
1621 case 1:
1622 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1623 /* AP address is in bits 31:24 of DP_SELECT */
1624 if (apsel >= 256)
1625 return ERROR_COMMAND_SYNTAX_ERROR;
1626 break;
1627 default:
1628 return ERROR_COMMAND_SYNTAX_ERROR;
1629 }
1630
1631 dap->apsel = apsel;
1632
1633 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1634 if (retval != ERROR_OK)
1635 return retval;
1636 retval = dap_run(dap);
1637 if (retval != ERROR_OK)
1638 return retval;
1639
1640 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1641 apsel, apid);
1642
1643 return retval;
1644 }
1645
1646 COMMAND_HANDLER(dap_apcsw_command)
1647 {
1648 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1649 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1650 uint32_t sprot = 0;
1651
1652 switch (CMD_ARGC) {
1653 case 0:
1654 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1655 (dap->apsel), apcsw);
1656 break;
1657 case 1:
1658 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1659 /* AP address is in bits 31:24 of DP_SELECT */
1660 if (sprot > 1)
1661 return ERROR_COMMAND_SYNTAX_ERROR;
1662 if (sprot)
1663 apcsw |= CSW_SPROT;
1664 else
1665 apcsw &= ~CSW_SPROT;
1666 break;
1667 default:
1668 return ERROR_COMMAND_SYNTAX_ERROR;
1669 }
1670 dap->ap[dap->apsel].csw_default = apcsw;
1671
1672 return 0;
1673 }
1674
1675
1676
1677 COMMAND_HANDLER(dap_apid_command)
1678 {
1679 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1680 uint32_t apsel, apid;
1681 int retval;
1682
1683 switch (CMD_ARGC) {
1684 case 0:
1685 apsel = dap->apsel;
1686 break;
1687 case 1:
1688 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1689 /* AP address is in bits 31:24 of DP_SELECT */
1690 if (apsel >= 256)
1691 return ERROR_COMMAND_SYNTAX_ERROR;
1692 break;
1693 default:
1694 return ERROR_COMMAND_SYNTAX_ERROR;
1695 }
1696
1697 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1698 if (retval != ERROR_OK)
1699 return retval;
1700 retval = dap_run(dap);
1701 if (retval != ERROR_OK)
1702 return retval;
1703
1704 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1705
1706 return retval;
1707 }
1708
1709 COMMAND_HANDLER(dap_apreg_command)
1710 {
1711 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1712 uint32_t apsel, reg, value;
1713 int retval;
1714
1715 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1716 return ERROR_COMMAND_SYNTAX_ERROR;
1717
1718 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1719 /* AP address is in bits 31:24 of DP_SELECT */
1720 if (apsel >= 256)
1721 return ERROR_COMMAND_SYNTAX_ERROR;
1722
1723 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1724 if (reg >= 256 || (reg & 3))
1725 return ERROR_COMMAND_SYNTAX_ERROR;
1726
1727 if (CMD_ARGC == 3) {
1728 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1729 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1730 } else {
1731 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1732 }
1733 if (retval == ERROR_OK)
1734 retval = dap_run(dap);
1735
1736 if (retval != ERROR_OK)
1737 return retval;
1738
1739 if (CMD_ARGC == 2)
1740 command_print(CMD_CTX, "0x%08" PRIx32, value);
1741
1742 return retval;
1743 }
1744
1745 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1746 {
1747 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1748 uint32_t enable = dap->ti_be_32_quirks;
1749
1750 switch (CMD_ARGC) {
1751 case 0:
1752 break;
1753 case 1:
1754 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1755 if (enable > 1)
1756 return ERROR_COMMAND_SYNTAX_ERROR;
1757 break;
1758 default:
1759 return ERROR_COMMAND_SYNTAX_ERROR;
1760 }
1761 dap->ti_be_32_quirks = enable;
1762 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1763 enable ? "enabled" : "disabled");
1764
1765 return 0;
1766 }
1767
1768 const struct command_registration dap_instance_commands[] = {
1769 {
1770 .name = "info",
1771 .handler = handle_dap_info_command,
1772 .mode = COMMAND_EXEC,
1773 .help = "display ROM table for MEM-AP "
1774 "(default currently selected AP)",
1775 .usage = "[ap_num]",
1776 },
1777 {
1778 .name = "apsel",
1779 .handler = dap_apsel_command,
1780 .mode = COMMAND_EXEC,
1781 .help = "Set the currently selected AP (default 0) "
1782 "and display the result",
1783 .usage = "[ap_num]",
1784 },
1785 {
1786 .name = "apcsw",
1787 .handler = dap_apcsw_command,
1788 .mode = COMMAND_EXEC,
1789 .help = "Set csw access bit ",
1790 .usage = "[sprot]",
1791 },
1792
1793 {
1794 .name = "apid",
1795 .handler = dap_apid_command,
1796 .mode = COMMAND_EXEC,
1797 .help = "return ID register from AP "
1798 "(default currently selected AP)",
1799 .usage = "[ap_num]",
1800 },
1801 {
1802 .name = "apreg",
1803 .handler = dap_apreg_command,
1804 .mode = COMMAND_EXEC,
1805 .help = "read/write a register from AP "
1806 "(reg is byte address of a word register, like 0 4 8...)",
1807 .usage = "ap_num reg [value]",
1808 },
1809 {
1810 .name = "baseaddr",
1811 .handler = dap_baseaddr_command,
1812 .mode = COMMAND_EXEC,
1813 .help = "return debug base address from MEM-AP "
1814 "(default currently selected AP)",
1815 .usage = "[ap_num]",
1816 },
1817 {
1818 .name = "memaccess",
1819 .handler = dap_memaccess_command,
1820 .mode = COMMAND_EXEC,
1821 .help = "set/get number of extra tck for MEM-AP memory "
1822 "bus access [0-255]",
1823 .usage = "[cycles]",
1824 },
1825 {
1826 .name = "ti_be_32_quirks",
1827 .handler = dap_ti_be_32_quirks_command,
1828 .mode = COMMAND_CONFIG,
1829 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1830 .usage = "[enable]",
1831 },
1832 COMMAND_REGISTRATION_DONE
1833 };
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|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)