1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
29 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
30 * debugging architecture. Compared with previous versions, this includes
31 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
32 * transport, and focusses on memory mapped resources as defined by the
33 * CoreSight architecture.
35 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
36 * basic components: a Debug Port (DP) transporting messages to and from a
37 * debugger, and an Access Port (AP) accessing resources. Three types of DP
38 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
39 * One uses only SWD for communication, and is called SW-DP. The third can
40 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
41 * is used to access memory mapped resources and is called a MEM-AP. Also a
42 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * Relevant specifications from ARM include:
48 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
49 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
51 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
52 * Cortex-M3(tm) TRM, ARM DDI 0337G
59 #include "arm_adi_v5.h"
60 #include <helper/time_support.h>
64 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
65 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
66 * result checking until swjdp_end_transaction()
67 * This must be done before using or deallocating any return variables.
68 * swjdp->trans_mode == TRANS_MODE_ATOMIC
69 * All reads and writes to the AHB bus are checked for valid completion, and return values
70 * are immediatley available.
74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
77 uint32_t tar_block_size(uint32_t address)
78 Return the largest block starting at address that does not cross a tar block size alignment boundary
80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
82 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
85 /***************************************************************************
87 * DPACC and APACC scanchain access through JTAG-DP *
89 ***************************************************************************/
92 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
93 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
94 * discusses operations which access these registers.
96 * Note that only one scan is performed. If RnW is set, a separate scan
97 * will be needed to collect the data which was read; the "invalue" collects
98 * the posted result of a preceding operation, not the current one.
100 * @param swjdp the DAP
101 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
102 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
103 * SELECT register has more addressing bits.
104 * @param RnW false iff outvalue will be written to the DP or AP
105 * @param outvalue points to a 32-bit (little-endian) integer
106 * @param invalue NULL, or points to a 32-bit (little-endian) integer
107 * @param ack points to where the three bit JTAG_ACK_* code will be stored
109 static int adi_jtag_dp_scan(struct swjdp_common
*swjdp
,
110 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
111 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
113 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
114 struct scan_field fields
[2];
115 uint8_t out_addr_buf
;
117 jtag_set_end_state(TAP_IDLE
);
118 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
120 /* Add specified number of tck clocks before accessing memory bus */
122 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
123 * they provide more time for the (MEM) AP to complete the read ...
124 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
126 if ((instr
== JTAG_DP_APACC
)
127 && ((reg_addr
== AP_REG_DRW
)
128 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
129 && (swjdp
->memaccess_tck
!= 0))
130 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
132 /* Scan out a read or write operation using some DP or AP register.
133 * For APACC access with any sticky error flag set, this is discarded.
135 fields
[0].tap
= jtag_info
->tap
;
136 fields
[0].num_bits
= 3;
137 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
138 fields
[0].out_value
= &out_addr_buf
;
139 fields
[0].in_value
= ack
;
141 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
142 * complete; data we write is discarded, data we read is unpredictable.
143 * When overrun detect is active, STICKYORUN is set.
146 fields
[1].tap
= jtag_info
->tap
;
147 fields
[1].num_bits
= 32;
148 fields
[1].out_value
= outvalue
;
149 fields
[1].in_value
= invalue
;
151 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
156 /* Scan out and in from host ordered uint32_t variables */
157 static int adi_jtag_dp_scan_u32(struct swjdp_common
*swjdp
,
158 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
159 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
161 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
162 struct scan_field fields
[2];
163 uint8_t out_value_buf
[4];
164 uint8_t out_addr_buf
;
166 jtag_set_end_state(TAP_IDLE
);
167 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
169 /* Add specified number of tck clocks before accessing memory bus */
171 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
172 * they provide more time for the (MEM) AP to complete the read ...
174 if ((instr
== JTAG_DP_APACC
)
175 && ((reg_addr
== AP_REG_DRW
)
176 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
177 && (swjdp
->memaccess_tck
!= 0))
178 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
180 fields
[0].tap
= jtag_info
->tap
;
181 fields
[0].num_bits
= 3;
182 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
183 fields
[0].out_value
= &out_addr_buf
;
184 fields
[0].in_value
= ack
;
186 fields
[1].tap
= jtag_info
->tap
;
187 fields
[1].num_bits
= 32;
188 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
189 fields
[1].out_value
= out_value_buf
;
190 fields
[1].in_value
= NULL
;
194 fields
[1].in_value
= (uint8_t *)invalue
;
195 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
197 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
) invalue
);
201 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
207 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
208 static int scan_inout_check(struct swjdp_common
*swjdp
,
209 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
210 uint8_t *outvalue
, uint8_t *invalue
)
212 adi_jtag_dp_scan(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
214 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
215 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
,
216 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
218 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
219 * ack = OK/FAULT and the check CTRL_STAT
221 if ((instr
== JTAG_DP_APACC
)
222 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
223 return jtagdp_transaction_endcheck(swjdp
);
228 static int scan_inout_check_u32(struct swjdp_common
*swjdp
,
229 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
230 uint32_t outvalue
, uint32_t *invalue
)
232 /* Issue the read or write */
233 adi_jtag_dp_scan_u32(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
235 /* For reads, collect posted value; RDBUFF has no other effect.
236 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
238 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
239 adi_jtag_dp_scan_u32(swjdp
, JTAG_DP_DPACC
,
240 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
242 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
243 * ack = OK/FAULT and then check CTRL_STAT
245 if ((instr
== JTAG_DP_APACC
)
246 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
247 return jtagdp_transaction_endcheck(swjdp
);
252 int jtagdp_transaction_endcheck(struct swjdp_common
*swjdp
)
257 /* too expensive to call keep_alive() here */
260 /* Danger!!!! BROKEN!!!! */
261 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
262 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
263 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
264 R956 introduced the check on return value here and now Michael Schwingen reports
265 that this code no longer works....
267 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
269 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
271 LOG_ERROR("BUG: Why does this fail the first time????");
273 /* Why??? second time it works??? */
276 /* Post CTRL/STAT read; discard any previous posted read value
277 * but collect its ACK status.
279 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
280 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
281 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
284 swjdp
->ack
= swjdp
->ack
& 0x7;
286 /* common code path avoids calling timeval_ms() */
287 if (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
289 long long then
= timeval_ms();
291 while (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
293 if (swjdp
->ack
== JTAG_ACK_WAIT
)
295 if ((timeval_ms()-then
) > 1000)
297 /* NOTE: this would be a good spot
298 * to use JTAG_DP_ABORT.
300 LOG_WARNING("Timeout (1000ms) waiting "
302 "in JTAG-DP transaction");
303 return ERROR_JTAG_DEVICE_ERROR
;
308 LOG_WARNING("Invalid ACK %#x "
309 "in JTAG-DP transaction",
311 return ERROR_JTAG_DEVICE_ERROR
;
314 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
315 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
316 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
318 swjdp
->ack
= swjdp
->ack
& 0x7;
322 /* Check for STICKYERR and STICKYORUN */
323 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
325 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32
, ctrlstat
);
326 /* Check power to debug regions */
327 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
329 ahbap_debugport_init(swjdp
);
333 uint32_t mem_ap_csw
, mem_ap_tar
;
335 /* Print information about last AHBAP access */
336 LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
337 ", ap_csw 0x%" PRIx32
", ap_tar 0x%" PRIx32
,
338 swjdp
->dp_select_value
, swjdp
->ap_csw_value
,
339 swjdp
->ap_tar_value
);
340 if (ctrlstat
& SSTICKYORUN
)
341 LOG_ERROR("JTAG-DP OVERRUN - "
342 "check clock or reduce jtag speed");
344 if (ctrlstat
& SSTICKYERR
)
345 LOG_ERROR("JTAG-DP STICKY ERROR");
347 /* Clear Sticky Error Bits */
348 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
349 DP_CTRL_STAT
, DPAP_WRITE
,
350 swjdp
->dp_ctrl_stat
| SSTICKYORUN
352 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
353 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
354 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
357 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32
, ctrlstat
);
359 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
360 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
361 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
363 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%"
364 PRIx32
, mem_ap_csw
, mem_ap_tar
);
367 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
369 return ERROR_JTAG_DEVICE_ERROR
;
375 /***************************************************************************
377 * DP and MEM-AP register access through APACC and DPACC *
379 ***************************************************************************/
381 static int dap_dp_write_reg(struct swjdp_common
*swjdp
,
382 uint32_t value
, uint8_t reg_addr
)
384 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
385 reg_addr
, DPAP_WRITE
, value
, NULL
);
388 static int dap_dp_read_reg(struct swjdp_common
*swjdp
,
389 uint32_t *value
, uint8_t reg_addr
)
391 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
392 reg_addr
, DPAP_READ
, 0, value
);
395 int dap_ap_select(struct swjdp_common
*swjdp
,uint8_t apsel
)
398 select
= (apsel
<< 24) & 0xFF000000;
400 if (select
!= swjdp
->apsel
)
402 swjdp
->apsel
= select
;
403 /* Switching AP invalidates cached values */
404 swjdp
->dp_select_value
= -1;
405 swjdp
->ap_csw_value
= -1;
406 swjdp
->ap_tar_value
= -1;
412 static int dap_dp_bankselect(struct swjdp_common
*swjdp
, uint32_t ap_reg
)
415 select
= (ap_reg
& 0x000000F0);
417 if (select
!= swjdp
->dp_select_value
)
419 dap_dp_write_reg(swjdp
, select
| swjdp
->apsel
, DP_SELECT
);
420 swjdp
->dp_select_value
= select
;
426 static int dap_ap_write_reg(struct swjdp_common
*swjdp
,
427 uint32_t reg_addr
, uint8_t *out_value_buf
)
429 dap_dp_bankselect(swjdp
, reg_addr
);
430 scan_inout_check(swjdp
, JTAG_DP_APACC
, reg_addr
,
431 DPAP_WRITE
, out_value_buf
, NULL
);
436 int dap_ap_write_reg_u32(struct swjdp_common
*swjdp
, uint32_t reg_addr
, uint32_t value
)
438 uint8_t out_value_buf
[4];
440 buf_set_u32(out_value_buf
, 0, 32, value
);
441 dap_dp_bankselect(swjdp
, reg_addr
);
442 scan_inout_check(swjdp
, JTAG_DP_APACC
, reg_addr
,
443 DPAP_WRITE
, out_value_buf
, NULL
);
448 int dap_ap_read_reg_u32(struct swjdp_common
*swjdp
, uint32_t reg_addr
, uint32_t *value
)
450 dap_dp_bankselect(swjdp
, reg_addr
);
451 scan_inout_check_u32(swjdp
, JTAG_DP_APACC
, reg_addr
,
452 DPAP_READ
, 0, value
);
457 /***************************************************************************
459 * AHB-AP access to memory and system registers on AHB bus *
461 ***************************************************************************/
463 int dap_setup_accessport(struct swjdp_common
*swjdp
, uint32_t csw
, uint32_t tar
)
465 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
466 if (csw
!= swjdp
->ap_csw_value
)
468 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
469 dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
470 swjdp
->ap_csw_value
= csw
;
472 if (tar
!= swjdp
->ap_tar_value
)
474 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
475 dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
476 swjdp
->ap_tar_value
= tar
;
478 if (csw
& CSW_ADDRINC_MASK
)
480 /* Do not cache TAR value when autoincrementing */
481 swjdp
->ap_tar_value
= -1;
486 /*****************************************************************************
488 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
490 * Read a uint32_t value from memory or system register *
491 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
492 * but with less overhead *
493 *****************************************************************************/
494 int mem_ap_read_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t *value
)
496 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
498 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
499 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
504 int mem_ap_read_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t *value
)
506 mem_ap_read_u32(swjdp
, address
, value
);
508 return jtagdp_transaction_endcheck(swjdp
);
511 /*****************************************************************************
513 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
515 * Write a uint32_t value to memory or memory mapped register *
517 *****************************************************************************/
518 int mem_ap_write_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t value
)
520 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
522 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
523 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
528 int mem_ap_write_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t value
)
530 mem_ap_write_u32(swjdp
, address
, value
);
532 return jtagdp_transaction_endcheck(swjdp
);
535 /*****************************************************************************
537 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
539 * Write a buffer in target order (little endian) *
541 *****************************************************************************/
542 int mem_ap_write_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
544 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
545 uint32_t adr
= address
;
546 uint8_t* pBuffer
= buffer
;
548 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
553 /* if we have an unaligned access - reorder data */
556 for (writecount
= 0; writecount
< count
; writecount
++)
560 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
562 for (i
= 0; i
< 4; i
++)
564 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
568 pBuffer
+= sizeof(uint32_t);
574 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
575 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
576 if (wcount
< blocksize
)
579 /* handle unaligned data at 4k boundary */
583 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
585 for (writecount
= 0; writecount
< blocksize
; writecount
++)
587 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
590 if (jtagdp_transaction_endcheck(swjdp
) == ERROR_OK
)
592 wcount
= wcount
- blocksize
;
593 address
= address
+ 4 * blocksize
;
594 buffer
= buffer
+ 4 * blocksize
;
603 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
604 return ERROR_JTAG_DEVICE_ERROR
;
611 static int mem_ap_write_buf_packed_u16(struct swjdp_common
*swjdp
,
612 uint8_t *buffer
, int count
, uint32_t address
)
614 int retval
= ERROR_OK
;
615 int wcount
, blocksize
, writecount
, i
;
617 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
625 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
626 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
628 if (wcount
< blocksize
)
631 /* handle unaligned data at 4k boundary */
635 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
636 writecount
= blocksize
;
640 nbytes
= MIN((writecount
<< 1), 4);
644 if (mem_ap_write_buf_u16(swjdp
, buffer
,
645 nbytes
, address
) != ERROR_OK
)
647 LOG_WARNING("Block write error address "
648 "0x%" PRIx32
", count 0x%x",
650 return ERROR_JTAG_DEVICE_ERROR
;
653 address
+= nbytes
>> 1;
658 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
660 for (i
= 0; i
< nbytes
; i
++)
662 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
667 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
668 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
669 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
671 LOG_WARNING("Block write error address "
672 "0x%" PRIx32
", count 0x%x",
674 return ERROR_JTAG_DEVICE_ERROR
;
678 buffer
+= nbytes
>> 1;
679 writecount
-= nbytes
>> 1;
681 } while (writecount
);
688 int mem_ap_write_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
690 int retval
= ERROR_OK
;
693 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
695 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
699 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
701 memcpy(&svalue
, buffer
, sizeof(uint16_t));
702 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
703 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
704 retval
= jtagdp_transaction_endcheck(swjdp
);
713 static int mem_ap_write_buf_packed_u8(struct swjdp_common
*swjdp
,
714 uint8_t *buffer
, int count
, uint32_t address
)
716 int retval
= ERROR_OK
;
717 int wcount
, blocksize
, writecount
, i
;
719 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
727 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
728 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
730 if (wcount
< blocksize
)
733 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
734 writecount
= blocksize
;
738 nbytes
= MIN(writecount
, 4);
742 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
744 LOG_WARNING("Block write error address "
745 "0x%" PRIx32
", count 0x%x",
747 return ERROR_JTAG_DEVICE_ERROR
;
755 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
757 for (i
= 0; i
< nbytes
; i
++)
759 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
764 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
765 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
766 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
768 LOG_WARNING("Block write error address "
769 "0x%" PRIx32
", count 0x%x",
771 return ERROR_JTAG_DEVICE_ERROR
;
776 writecount
-= nbytes
;
778 } while (writecount
);
785 int mem_ap_write_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
787 int retval
= ERROR_OK
;
790 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
792 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
796 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
797 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
798 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
799 retval
= jtagdp_transaction_endcheck(swjdp
);
808 /*********************************************************************************
810 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
812 * Read block fast in target order (little endian) into a buffer *
814 **********************************************************************************/
815 int mem_ap_read_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
817 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
818 uint32_t adr
= address
;
819 uint8_t* pBuffer
= buffer
;
821 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
828 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
829 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
830 if (wcount
< blocksize
)
833 /* handle unaligned data at 4k boundary */
837 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
839 /* Scan out first read */
840 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
841 DPAP_READ
, 0, NULL
, NULL
);
842 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
844 /* Scan out next read; scan in posted value for the
845 * previous one. Assumes read is acked "OK/FAULT",
846 * and CTRL_STAT says that meant "OK".
848 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
849 DPAP_READ
, 0, buffer
+ 4 * readcount
,
853 /* Scan in last posted value; RDBUFF has no other effect,
854 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
856 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
, DP_RDBUFF
,
857 DPAP_READ
, 0, buffer
+ 4 * readcount
,
859 if (jtagdp_transaction_endcheck(swjdp
) == ERROR_OK
)
861 wcount
= wcount
- blocksize
;
862 address
+= 4 * blocksize
;
863 buffer
+= 4 * blocksize
;
872 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
873 return ERROR_JTAG_DEVICE_ERROR
;
877 /* if we have an unaligned access - reorder data */
880 for (readcount
= 0; readcount
< count
; readcount
++)
884 memcpy(&data
, pBuffer
, sizeof(uint32_t));
886 for (i
= 0; i
< 4; i
++)
888 *((uint8_t*)pBuffer
) = (data
>> 8 * (adr
& 0x3));
898 static int mem_ap_read_buf_packed_u16(struct swjdp_common
*swjdp
,
899 uint8_t *buffer
, int count
, uint32_t address
)
902 int retval
= ERROR_OK
;
903 int wcount
, blocksize
, readcount
, i
;
905 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
913 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
914 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
915 if (wcount
< blocksize
)
918 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
920 /* handle unaligned data at 4k boundary */
923 readcount
= blocksize
;
927 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
928 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
930 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
931 return ERROR_JTAG_DEVICE_ERROR
;
934 nbytes
= MIN((readcount
<< 1), 4);
936 for (i
= 0; i
< nbytes
; i
++)
938 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
943 readcount
-= (nbytes
>> 1);
951 int mem_ap_read_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
954 int retval
= ERROR_OK
;
957 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
959 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
963 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
964 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
965 retval
= jtagdp_transaction_endcheck(swjdp
);
968 for (i
= 0; i
< 2; i
++)
970 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
977 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
978 memcpy(buffer
, &svalue
, sizeof(uint16_t));
988 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
989 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
991 * The solution is to arrange for a large out/in scan in this loop and
992 * and convert data afterwards.
994 static int mem_ap_read_buf_packed_u8(struct swjdp_common
*swjdp
,
995 uint8_t *buffer
, int count
, uint32_t address
)
998 int retval
= ERROR_OK
;
999 int wcount
, blocksize
, readcount
, i
;
1001 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1009 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1010 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
1012 if (wcount
< blocksize
)
1015 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
1016 readcount
= blocksize
;
1020 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1021 if (jtagdp_transaction_endcheck(swjdp
) != ERROR_OK
)
1023 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1024 return ERROR_JTAG_DEVICE_ERROR
;
1027 nbytes
= MIN(readcount
, 4);
1029 for (i
= 0; i
< nbytes
; i
++)
1031 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1036 readcount
-= nbytes
;
1037 } while (readcount
);
1038 wcount
-= blocksize
;
1044 int mem_ap_read_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
1047 int retval
= ERROR_OK
;
1050 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
1052 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1056 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
1057 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1058 retval
= jtagdp_transaction_endcheck(swjdp
);
1059 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1071 * @todo Rename this. We also need an initialization scheme which account
1072 * for SWD transports not just JTAG; that will need to address differences
1073 * in layering. (JTAG is useful without any debug target; but not SWD.)
1074 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1076 int ahbap_debugport_init(struct swjdp_common
*swjdp
)
1078 uint32_t idreg
, romaddr
, dummy
;
1085 /* Default MEM-AP setup.
1087 * REVISIT AP #0 may be an inappropriate default for this.
1088 * Should we probe, or receve a hint from the caller?
1089 * Presumably we can ignore the possibility of multiple APs.
1092 swjdp
->ap_csw_value
= -1;
1093 swjdp
->ap_tar_value
= -1;
1095 /* DP initialization */
1096 swjdp
->trans_mode
= TRANS_MODE_ATOMIC
;
1097 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1098 dap_dp_write_reg(swjdp
, SSTICKYERR
, DP_CTRL_STAT
);
1099 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1101 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1103 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1104 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1105 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1108 /* Check that we have debug power domains activated */
1109 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
1111 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1112 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1113 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1118 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
1120 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1121 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1122 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1127 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1128 /* With debug power on we can activate OVERRUN checking */
1129 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1130 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1131 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1134 * REVISIT this isn't actually *initializing* anything in an AP,
1135 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1136 * Should it? If the ROM address is valid, is this the right
1137 * place to scan the table and do any topology detection?
1139 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &idreg
);
1140 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &romaddr
);
1142 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1143 ", Debug ROM Address 0x%" PRIx32
,
1144 swjdp
->apsel
, idreg
, romaddr
);
1149 /* CID interpretation -- see ARM IHI 0029B section 3
1150 * and ARM IHI 0031A table 13-3.
1152 static const char *class_description
[16] ={
1153 "Reserved", "ROM table", "Reserved", "Reserved",
1154 "Reserved", "Reserved", "Reserved", "Reserved",
1155 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1156 "Reserved", "OptimoDE DESS",
1157 "Generic IP component", "PrimeCell or System component"
1161 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1163 return cid3
== 0xb1 && cid2
== 0x05
1164 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1167 int dap_info_command(struct command_context
*cmd_ctx
, struct swjdp_common
*swjdp
, int apsel
)
1170 uint32_t dbgbase
, apid
;
1171 int romtable_present
= 0;
1175 apselold
= swjdp
->apsel
;
1176 dap_ap_select(swjdp
, apsel
);
1177 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &dbgbase
);
1178 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1179 jtagdp_transaction_endcheck(swjdp
);
1180 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1181 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1182 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1188 command_print(cmd_ctx
, "\tType is JTAG-AP");
1191 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1194 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1197 command_print(cmd_ctx
, "\tUnknown AP type");
1201 /* NOTE: a MEM-AP may have a single CoreSight component that's
1202 * not a ROM table ... or have no such components at all.
1205 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1210 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1213 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1214 if (romtable_present
)
1216 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1217 uint16_t entry_offset
;
1219 /* bit 16 of apid indicates a memory access port */
1221 command_print(cmd_ctx
, "\tValid ROM table present");
1223 command_print(cmd_ctx
, "\tROM table in legacy format");
1225 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1226 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1227 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1228 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1229 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1230 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1231 jtagdp_transaction_endcheck(swjdp
);
1232 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1233 command_print(cmd_ctx
, "\tCID3 0x%2.2" PRIx32
1234 ", CID2 0x%2.2" PRIx32
1235 ", CID1 0x%2.2" PRIx32
1236 ", CID0 0x%2.2" PRIx32
,
1237 cid3
, cid2
, cid1
, cid0
);
1239 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1241 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1242 "Dedicated debug bus.");
1244 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1248 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1249 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1252 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1253 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1254 uint32_t component_start
, component_base
;
1258 component_base
= (uint32_t)((dbgbase
& 0xFFFFF000)
1259 + (int)(romentry
& 0xFFFFF000));
1260 mem_ap_read_atomic_u32(swjdp
,
1261 (component_base
& 0xFFFFF000) | 0xFE0, &c_pid0
);
1262 mem_ap_read_atomic_u32(swjdp
,
1263 (component_base
& 0xFFFFF000) | 0xFE4, &c_pid1
);
1264 mem_ap_read_atomic_u32(swjdp
,
1265 (component_base
& 0xFFFFF000) | 0xFE8, &c_pid2
);
1266 mem_ap_read_atomic_u32(swjdp
,
1267 (component_base
& 0xFFFFF000) | 0xFEC, &c_pid3
);
1268 mem_ap_read_atomic_u32(swjdp
,
1269 (component_base
& 0xFFFFF000) | 0xFD0, &c_pid4
);
1270 mem_ap_read_atomic_u32(swjdp
,
1271 (component_base
& 0xFFFFF000) | 0xFF0, &c_cid0
);
1272 mem_ap_read_atomic_u32(swjdp
,
1273 (component_base
& 0xFFFFF000) | 0xFF4, &c_cid1
);
1274 mem_ap_read_atomic_u32(swjdp
,
1275 (component_base
& 0xFFFFF000) | 0xFF8, &c_cid2
);
1276 mem_ap_read_atomic_u32(swjdp
,
1277 (component_base
& 0xFFFFF000) | 0xFFC, &c_cid3
);
1278 component_start
= component_base
- 0x1000*(c_pid4
>> 4);
1280 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
1281 ", start address 0x%" PRIx32
,
1282 component_base
, component_start
);
1283 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1284 (int) (c_cid1
>> 4) & 0xf,
1285 /* See ARM IHI 0029B Table 3-3 */
1286 class_description
[(c_cid1
>> 4) & 0xf]);
1288 /* CoreSight component? */
1289 if (((c_cid1
>> 4) & 0x0f) == 9) {
1292 char *major
= "Reserved", *subtype
= "Reserved";
1294 mem_ap_read_atomic_u32(swjdp
,
1295 (component_base
& 0xfffff000) | 0xfcc,
1297 minor
= (devtype
>> 4) & 0x0f;
1298 switch (devtype
& 0x0f) {
1300 major
= "Miscellaneous";
1306 subtype
= "Validation component";
1311 major
= "Trace Sink";
1325 major
= "Trace Link";
1331 subtype
= "Funnel, router";
1337 subtype
= "FIFO, buffer";
1342 major
= "Trace Source";
1348 subtype
= "Processor";
1354 subtype
= "Engine/Coprocessor";
1362 major
= "Debug Control";
1368 subtype
= "Trigger Matrix";
1371 subtype
= "Debug Auth";
1376 major
= "Debug Logic";
1382 subtype
= "Processor";
1388 subtype
= "Engine/Coprocessor";
1393 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1394 (unsigned) (devtype
& 0xff),
1396 /* REVISIT also show 0xfc8 DevId */
1399 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1400 command_print(cmd_ctx
, "\t\tCID3 0x%2.2" PRIx32
1401 ", CID2 0x%2.2" PRIx32
1402 ", CID1 0x%2.2" PRIx32
1403 ", CID0 0x%2.2" PRIx32
,
1404 c_cid3
, c_cid2
, c_cid1
, c_cid0
);
1405 command_print(cmd_ctx
, "\t\tPeripheral ID[4..0] = hex "
1406 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1408 (int) c_pid3
, (int) c_pid2
,
1409 (int) c_pid1
, (int) c_pid0
);
1411 /* Part number interpretations are from Cortex
1412 * core specs, the CoreSight components TRM
1413 * (ARM DDI 0314H), and ETM specs; also from
1414 * chip observation (e.g. TI SDTI).
1416 part_num
= c_pid0
& 0xff;
1417 part_num
|= (c_pid1
& 0x0f) << 8;
1420 type
= "Cortex-M3 NVIC";
1421 full
= "(Interrupt Controller)";
1424 type
= "Cortex-M3 ITM";
1425 full
= "(Instrumentation Trace Module)";
1428 type
= "Cortex-M3 DWT";
1429 full
= "(Data Watchpoint and Trace)";
1432 type
= "Cortex-M3 FBP";
1433 full
= "(Flash Patch and Breakpoint)";
1436 type
= "CoreSight ETM11";
1437 full
= "(Embedded Trace)";
1439 // case 0x113: what?
1440 case 0x120: /* from OMAP3 memmap */
1442 full
= "(System Debug Trace Interface)";
1444 case 0x343: /* from OMAP3 memmap */
1449 type
= "Cortex-M3 ETM";
1450 full
= "(Embedded Trace)";
1453 type
= "Coresight CTI";
1454 full
= "(Cross Trigger)";
1457 type
= "Coresight ETB";
1458 full
= "(Trace Buffer)";
1461 type
= "Coresight CSTF";
1462 full
= "(Trace Funnel)";
1465 type
= "CoreSight ETM9";
1466 full
= "(Embedded Trace)";
1469 type
= "Coresight TPIU";
1470 full
= "(Trace Port Interface Unit)";
1473 type
= "Cortex-A8 ETM";
1474 full
= "(Embedded Trace)";
1477 type
= "Cortex-A8 CTI";
1478 full
= "(Cross Trigger)";
1481 type
= "Cortex-M3 TPIU";
1482 full
= "(Trace Port Interface Unit)";
1485 type
= "Cortex-A8 Debug";
1486 full
= "(Debug Unit)";
1489 type
= "-*- unrecognized -*-";
1493 command_print(cmd_ctx
, "\t\tPart is %s %s",
1499 command_print(cmd_ctx
, "\t\tComponent not present");
1501 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1504 } while (romentry
> 0);
1508 command_print(cmd_ctx
, "\tNo ROM table present");
1510 dap_ap_select(swjdp
, apselold
);
1515 DAP_COMMAND_HANDLER(dap_baseaddr_command
)
1517 uint32_t apsel
, apselsave
, baseaddr
;
1520 apselsave
= swjdp
->apsel
;
1523 apsel
= swjdp
->apsel
;
1526 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1529 return ERROR_COMMAND_SYNTAX_ERROR
;
1532 if (apselsave
!= apsel
)
1533 dap_ap_select(swjdp
, apsel
);
1535 /* NOTE: assumes we're talking to a MEM-AP, which
1536 * has a base address. There are other kinds of AP,
1537 * though they're not common for now. This should
1538 * use the ID register to verify it's a MEM-AP.
1540 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &baseaddr
);
1541 retval
= jtagdp_transaction_endcheck(swjdp
);
1542 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1544 if (apselsave
!= apsel
)
1545 dap_ap_select(swjdp
, apselsave
);
1550 DAP_COMMAND_HANDLER(dap_memaccess_command
)
1552 uint32_t memaccess_tck
;
1556 memaccess_tck
= swjdp
->memaccess_tck
;
1559 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1562 return ERROR_COMMAND_SYNTAX_ERROR
;
1564 swjdp
->memaccess_tck
= memaccess_tck
;
1566 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1567 swjdp
->memaccess_tck
);
1572 DAP_COMMAND_HANDLER(dap_apsel_command
)
1574 uint32_t apsel
, apid
;
1582 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1585 return ERROR_COMMAND_SYNTAX_ERROR
;
1588 dap_ap_select(swjdp
, apsel
);
1589 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1590 retval
= jtagdp_transaction_endcheck(swjdp
);
1591 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1597 DAP_COMMAND_HANDLER(dap_apid_command
)
1599 uint32_t apsel
, apselsave
, apid
;
1602 apselsave
= swjdp
->apsel
;
1605 apsel
= swjdp
->apsel
;
1608 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1611 return ERROR_COMMAND_SYNTAX_ERROR
;
1614 if (apselsave
!= apsel
)
1615 dap_ap_select(swjdp
, apsel
);
1617 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1618 retval
= jtagdp_transaction_endcheck(swjdp
);
1619 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1620 if (apselsave
!= apsel
)
1621 dap_ap_select(swjdp
, apselsave
);
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