1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
88 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
)
108 uint32_t new_ap
= (ap
<< 24) & 0xFF000000;
110 if (new_ap
!= dap
->ap_current
) {
111 dap
->ap_current
= new_ap
;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap
->ap_bank_value
= -1;
119 static int dap_setup_accessport_csw(struct adiv5_dap
*dap
, uint32_t csw
)
121 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
|
122 dap
->ap
[dap_ap_get_select(dap
)].csw_default
;
124 if (csw
!= dap
->ap
[dap_ap_get_select(dap
)].csw_value
) {
125 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
126 int retval
= dap_queue_ap_write(dap
, MEM_AP_REG_CSW
, csw
);
127 if (retval
!= ERROR_OK
)
129 dap
->ap
[dap_ap_get_select(dap
)].csw_value
= csw
;
134 static int dap_setup_accessport_tar(struct adiv5_dap
*dap
, uint32_t tar
)
136 if (tar
!= dap
->ap
[dap_ap_get_select(dap
)].tar_value
||
137 (dap
->ap
[dap_ap_get_select(dap
)].csw_value
& CSW_ADDRINC_MASK
)) {
138 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
139 int retval
= dap_queue_ap_write(dap
, MEM_AP_REG_TAR
, tar
);
140 if (retval
!= ERROR_OK
)
142 dap
->ap
[dap_ap_get_select(dap
)].tar_value
= tar
;
148 * Queue transactions setting up transfer parameters for the
149 * currently selected MEM-AP.
151 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
152 * initiate data reads or writes using memory or peripheral addresses.
153 * If the CSW is configured for it, the TAR may be automatically
154 * incremented after each transfer.
156 * @todo Rename to reflect it being specifically a MEM-AP function.
158 * @param dap The DAP connected to the MEM-AP.
159 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
160 * matches the cached value, the register is not changed.
161 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
162 * matches the cached address, the register is not changed.
164 * @return ERROR_OK if the transaction was properly queued, else a fault code.
166 int dap_setup_accessport(struct adiv5_dap
*dap
, uint32_t csw
, uint32_t tar
)
169 retval
= dap_setup_accessport_csw(dap
, csw
);
170 if (retval
!= ERROR_OK
)
172 retval
= dap_setup_accessport_tar(dap
, tar
);
173 if (retval
!= ERROR_OK
)
179 * Asynchronous (queued) read of a word from memory or a system register.
181 * @param dap The DAP connected to the MEM-AP performing the read.
182 * @param address Address of the 32-bit word to read; it must be
183 * readable by the currently selected MEM-AP.
184 * @param value points to where the word will be stored when the
185 * transaction queue is flushed (assuming no errors).
187 * @return ERROR_OK for success. Otherwise a fault code.
189 static int mem_ap_read_u32(struct adiv5_dap
*dap
, uint32_t address
,
194 /* Use banked addressing (REG_BDx) to avoid some link traffic
195 * (updating TAR) when reading several consecutive addresses.
197 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
198 address
& 0xFFFFFFF0);
199 if (retval
!= ERROR_OK
)
202 return dap_queue_ap_read(dap
, MEM_AP_REG_BD0
| (address
& 0xC), value
);
206 * Synchronous read of a word from memory or a system register.
207 * As a side effect, this flushes any queued transactions.
209 * @param dap The DAP connected to the MEM-AP performing the read.
210 * @param address Address of the 32-bit word to read; it must be
211 * readable by the currently selected MEM-AP.
212 * @param value points to where the result will be stored.
214 * @return ERROR_OK for success; *value holds the result.
215 * Otherwise a fault code.
217 static int mem_ap_read_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
222 retval
= mem_ap_read_u32(dap
, address
, value
);
223 if (retval
!= ERROR_OK
)
230 * Asynchronous (queued) write of a word to memory or a system register.
232 * @param dap The DAP connected to the MEM-AP.
233 * @param address Address to be written; it must be writable by
234 * the currently selected MEM-AP.
235 * @param value Word that will be written to the address when transaction
236 * queue is flushed (assuming no errors).
238 * @return ERROR_OK for success. Otherwise a fault code.
240 static int mem_ap_write_u32(struct adiv5_dap
*dap
, uint32_t address
,
245 /* Use banked addressing (REG_BDx) to avoid some link traffic
246 * (updating TAR) when writing several consecutive addresses.
248 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
249 address
& 0xFFFFFFF0);
250 if (retval
!= ERROR_OK
)
253 return dap_queue_ap_write(dap
, MEM_AP_REG_BD0
| (address
& 0xC),
258 * Synchronous write of a word to memory or a system register.
259 * As a side effect, this flushes any queued transactions.
261 * @param dap The DAP connected to the MEM-AP.
262 * @param address Address to be written; it must be writable by
263 * the currently selected MEM-AP.
264 * @param value Word that will be written.
266 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
268 static int mem_ap_write_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
271 int retval
= mem_ap_write_u32(dap
, address
, value
);
273 if (retval
!= ERROR_OK
)
280 * Synchronous write of a block of memory, using a specific access size.
282 * @param dap The DAP connected to the MEM-AP.
283 * @param buffer The data buffer to write. No particular alignment is assumed.
284 * @param size Which access size to use, in bytes. 1, 2 or 4.
285 * @param count The number of writes to do (in size units, not bytes).
286 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
287 * @param addrinc Whether the target address should be increased for each write or not. This
288 * should normally be true, except when writing to e.g. a FIFO.
289 * @return ERROR_OK on success, otherwise an error code.
291 static int mem_ap_write(struct adiv5_dap
*dap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
292 uint32_t address
, bool addrinc
)
294 struct adiv5_ap
*ap
= &dap
->ap
[dap_ap_get_select(dap
)];
295 size_t nbytes
= size
* count
;
296 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
301 /* TI BE-32 Quirks mode:
302 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
303 * size write address bytes written in order
304 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
305 * 2 TAR ^ 2 (val >> 8), (val)
307 * For example, if you attempt to write a single byte to address 0, the processor
308 * will actually write a byte to address 3.
310 * To make writes of size < 4 work as expected, we xor a value with the address before
311 * setting the TAP, and we set the TAP after every transfer rather then relying on
312 * address increment. */
315 csw_size
= CSW_32BIT
;
317 } else if (size
== 2) {
318 csw_size
= CSW_16BIT
;
319 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
320 } else if (size
== 1) {
322 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
324 return ERROR_TARGET_UNALIGNED_ACCESS
;
327 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
328 return ERROR_TARGET_UNALIGNED_ACCESS
;
330 retval
= dap_setup_accessport_tar(dap
, address
^ addr_xor
);
331 if (retval
!= ERROR_OK
)
335 uint32_t this_size
= size
;
337 /* Select packed transfer if possible */
338 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
339 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
341 retval
= dap_setup_accessport_csw(dap
, csw_size
| CSW_ADDRINC_PACKED
);
343 retval
= dap_setup_accessport_csw(dap
, csw_size
| csw_addrincr
);
346 if (retval
!= ERROR_OK
)
349 /* How many source bytes each transfer will consume, and their location in the DRW,
350 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
351 uint32_t outvalue
= 0;
352 if (dap
->ti_be_32_quirks
) {
355 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
356 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
357 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
358 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
361 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
362 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
365 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (address
++ & 3) ^ addr_xor
);
371 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
372 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
374 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
376 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
382 retval
= dap_queue_ap_write(dap
, MEM_AP_REG_DRW
, outvalue
);
383 if (retval
!= ERROR_OK
)
386 /* Rewrite TAR if it wrapped or we're xoring addresses */
387 if (addrinc
&& (addr_xor
|| (address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0))) {
388 retval
= dap_setup_accessport_tar(dap
, address
^ addr_xor
);
389 if (retval
!= ERROR_OK
)
394 /* REVISIT: Might want to have a queued version of this function that does not run. */
395 if (retval
== ERROR_OK
)
396 retval
= dap_run(dap
);
398 if (retval
!= ERROR_OK
) {
400 if (dap_queue_ap_read(dap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
401 && dap_run(dap
) == ERROR_OK
)
402 LOG_ERROR("Failed to write memory at 0x%08"PRIx32
, tar
);
404 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
411 * Synchronous read of a block of memory, using a specific access size.
413 * @param dap The DAP connected to the MEM-AP.
414 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
415 * @param size Which access size to use, in bytes. 1, 2 or 4.
416 * @param count The number of reads to do (in size units, not bytes).
417 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
418 * @param addrinc Whether the target address should be increased after each read or not. This
419 * should normally be true, except when reading from e.g. a FIFO.
420 * @return ERROR_OK on success, otherwise an error code.
422 static int mem_ap_read(struct adiv5_dap
*dap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
423 uint32_t adr
, bool addrinc
)
425 struct adiv5_ap
*ap
= &dap
->ap
[dap_ap_get_select(dap
)];
426 size_t nbytes
= size
* count
;
427 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
429 uint32_t address
= adr
;
432 /* TI BE-32 Quirks mode:
433 * Reads on big-endian TMS570 behave strangely differently than writes.
434 * They read from the physical address requested, but with DRW byte-reversed.
435 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
436 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
440 csw_size
= CSW_32BIT
;
442 csw_size
= CSW_16BIT
;
446 return ERROR_TARGET_UNALIGNED_ACCESS
;
448 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
449 return ERROR_TARGET_UNALIGNED_ACCESS
;
451 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
452 * over-allocation if packed transfers are going to be used, but determining the real need at
453 * this point would be messy. */
454 uint32_t *read_buf
= malloc(count
* sizeof(uint32_t));
455 uint32_t *read_ptr
= read_buf
;
456 if (read_buf
== NULL
) {
457 LOG_ERROR("Failed to allocate read buffer");
461 retval
= dap_setup_accessport_tar(dap
, address
);
462 if (retval
!= ERROR_OK
) {
467 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
468 * useful bytes it contains, and their location in the word, depends on the type of transfer
471 uint32_t this_size
= size
;
473 /* Select packed transfer if possible */
474 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
475 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
477 retval
= dap_setup_accessport_csw(dap
, csw_size
| CSW_ADDRINC_PACKED
);
479 retval
= dap_setup_accessport_csw(dap
, csw_size
| csw_addrincr
);
481 if (retval
!= ERROR_OK
)
484 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_DRW
, read_ptr
++);
485 if (retval
!= ERROR_OK
)
489 address
+= this_size
;
491 /* Rewrite TAR if it wrapped */
492 if (addrinc
&& address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0) {
493 retval
= dap_setup_accessport_tar(dap
, address
);
494 if (retval
!= ERROR_OK
)
499 if (retval
== ERROR_OK
)
500 retval
= dap_run(dap
);
504 nbytes
= size
* count
;
507 /* If something failed, read TAR to find out how much data was successfully read, so we can
508 * at least give the caller what we have. */
509 if (retval
!= ERROR_OK
) {
511 if (dap_queue_ap_read(dap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
512 && dap_run(dap
) == ERROR_OK
) {
513 LOG_ERROR("Failed to read memory at 0x%08"PRIx32
, tar
);
514 if (nbytes
> tar
- address
)
515 nbytes
= tar
- address
;
517 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
522 /* Replay loop to populate caller's buffer from the correct word and byte lane */
524 uint32_t this_size
= size
;
526 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
527 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
531 if (dap
->ti_be_32_quirks
) {
534 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
535 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
537 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
539 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
544 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
545 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
547 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
549 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
561 /*--------------------------------------------------------------------*/
562 /* Wrapping function with selection of AP */
563 /*--------------------------------------------------------------------*/
564 int mem_ap_sel_read_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
565 uint32_t address
, uint32_t *value
)
567 dap_ap_select(swjdp
, ap
);
568 return mem_ap_read_u32(swjdp
, address
, value
);
571 int mem_ap_sel_write_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
572 uint32_t address
, uint32_t value
)
574 dap_ap_select(swjdp
, ap
);
575 return mem_ap_write_u32(swjdp
, address
, value
);
578 int mem_ap_sel_read_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
579 uint32_t address
, uint32_t *value
)
581 dap_ap_select(swjdp
, ap
);
582 return mem_ap_read_atomic_u32(swjdp
, address
, value
);
585 int mem_ap_sel_write_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
586 uint32_t address
, uint32_t value
)
588 dap_ap_select(swjdp
, ap
);
589 return mem_ap_write_atomic_u32(swjdp
, address
, value
);
592 int mem_ap_sel_read_buf(struct adiv5_dap
*swjdp
, uint8_t ap
,
593 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
595 dap_ap_select(swjdp
, ap
);
596 return mem_ap_read(swjdp
, buffer
, size
, count
, address
, true);
599 int mem_ap_sel_write_buf(struct adiv5_dap
*swjdp
, uint8_t ap
,
600 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
602 dap_ap_select(swjdp
, ap
);
603 return mem_ap_write(swjdp
, buffer
, size
, count
, address
, true);
606 int mem_ap_sel_read_buf_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
607 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
609 dap_ap_select(swjdp
, ap
);
610 return mem_ap_read(swjdp
, buffer
, size
, count
, address
, false);
613 int mem_ap_sel_write_buf_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
614 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
616 dap_ap_select(swjdp
, ap
);
617 return mem_ap_write(swjdp
, buffer
, size
, count
, address
, false);
620 /*--------------------------------------------------------------------------*/
623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
625 /* FIXME don't import ... just initialize as
626 * part of DAP transport setup
628 extern const struct dap_ops jtag_dp_ops
;
630 /*--------------------------------------------------------------------------*/
635 struct adiv5_dap
*dap_init(void)
637 struct adiv5_dap
*dap
= calloc(1, sizeof(struct adiv5_dap
));
639 /* Set up with safe defaults */
640 for (i
= 0; i
<= 255; i
++) {
641 dap
->ap
[i
].dap
= dap
;
642 dap
->ap
[i
].ap_num
= i
;
643 /* memaccess_tck max is 255 */
644 dap
->ap
[i
].memaccess_tck
= 255;
645 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
646 dap
->ap
[i
].tar_autoincr_block
= (1<<10);
652 * Initialize a DAP. This sets up the power domains, prepares the DP
653 * for further use, and arranges to use AP #0 for all AP operations
654 * until dap_ap-select() changes that policy.
656 * @param dap The DAP being initialized.
658 * @todo Rename this. We also need an initialization scheme which account
659 * for SWD transports not just JTAG; that will need to address differences
660 * in layering. (JTAG is useful without any debug target; but not SWD.)
661 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
663 int ahbap_debugport_init(struct adiv5_dap
*dap
, uint8_t apsel
)
665 /* check that we support packed transfers */
668 struct adiv5_ap
*ap
= &dap
->ap
[apsel
];
672 /* JTAG-DP or SWJ-DP, in JTAG mode
673 * ... for SWD mode this is patched as part
677 dap
->ops
= &jtag_dp_ops
;
679 /* Default MEM-AP setup.
681 * REVISIT AP #0 may be an inappropriate default for this.
682 * Should we probe, or take a hint from the caller?
683 * Presumably we can ignore the possibility of multiple APs.
685 dap
->ap_current
= -1;
686 dap_ap_select(dap
, apsel
);
687 dap
->last_read
= NULL
;
689 for (size_t i
= 0; i
< 10; i
++) {
690 /* DP initialization */
692 dap
->dp_bank_value
= 0;
694 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
695 if (retval
!= ERROR_OK
)
698 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
699 if (retval
!= ERROR_OK
)
702 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
703 if (retval
!= ERROR_OK
)
706 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
707 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
708 if (retval
!= ERROR_OK
)
711 /* Check that we have debug power domains activated */
712 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
713 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
714 CDBGPWRUPACK
, CDBGPWRUPACK
,
715 DAP_POWER_DOMAIN_TIMEOUT
);
716 if (retval
!= ERROR_OK
)
719 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
720 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
721 CSYSPWRUPACK
, CSYSPWRUPACK
,
722 DAP_POWER_DOMAIN_TIMEOUT
);
723 if (retval
!= ERROR_OK
)
726 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
727 if (retval
!= ERROR_OK
)
729 /* With debug power on we can activate OVERRUN checking */
730 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
731 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
732 if (retval
!= ERROR_OK
)
734 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
735 if (retval
!= ERROR_OK
)
738 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
739 if (retval
!= ERROR_OK
)
742 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_CSW
, &csw
);
743 if (retval
!= ERROR_OK
)
746 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_CFG
, &cfg
);
747 if (retval
!= ERROR_OK
)
750 retval
= dap_run(dap
);
751 if (retval
!= ERROR_OK
)
757 if (retval
!= ERROR_OK
)
760 if (csw
& CSW_ADDRINC_PACKED
)
761 ap
->packed_transfers
= true;
763 ap
->packed_transfers
= false;
765 /* Packed transfers on TI BE-32 processors do not work correctly in
767 if (dap
->ti_be_32_quirks
)
768 ap
->packed_transfers
= false;
770 LOG_DEBUG("MEM_AP Packed Transfers: %s",
771 ap
->packed_transfers
? "enabled" : "disabled");
773 /* The ARM ADI spec leaves implementation-defined whether unaligned
774 * memory accesses work, only work partially, or cause a sticky error.
775 * On TI BE-32 processors, reads seem to return garbage in some bytes
776 * and unaligned writes seem to cause a sticky error.
777 * TODO: it would be nice to have a way to detect whether unaligned
778 * operations are supported on other processors. */
779 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
781 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
782 !!(cfg
& 0x04), !!(cfg
& 0x02), !!(cfg
& 0x01));
787 /* CID interpretation -- see ARM IHI 0029B section 3
788 * and ARM IHI 0031A table 13-3.
790 static const char *class_description
[16] = {
791 "Reserved", "ROM table", "Reserved", "Reserved",
792 "Reserved", "Reserved", "Reserved", "Reserved",
793 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
794 "Reserved", "OptimoDE DESS",
795 "Generic IP component", "PrimeCell or System component"
798 static bool is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
800 return cid3
== 0xb1 && cid2
== 0x05
801 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
805 * This function checks the ID for each access port to find the requested Access Port type
807 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, uint8_t *ap_num_out
)
811 /* Maximum AP number is 255 since the SELECT register is 8 bits */
812 for (ap
= 0; ap
<= 255; ap
++) {
814 /* read the IDR register of the Access Port */
816 dap_ap_select(dap
, ap
);
818 int retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &id_val
);
819 if (retval
!= ERROR_OK
)
822 retval
= dap_run(dap
);
826 * 27-24 : JEDEC bank (0x4 for ARM)
827 * 23-17 : JEDEC code (0x3B for ARM)
830 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
833 /* Reading register for a non-existant AP should not cause an error,
834 * but just to be sure, try to continue searching if an error does happen.
836 if ((retval
== ERROR_OK
) && /* Register read success */
837 ((id_val
& 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
838 ((id_val
& 0xFF) == type_to_find
)) { /* type matches*/
840 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
841 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
842 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
843 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown",
851 LOG_DEBUG("No %s found",
852 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
853 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
854 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown");
858 int dap_get_debugbase(struct adiv5_dap
*dap
, int ap
,
859 uint32_t *dbgbase
, uint32_t *apid
)
864 /* AP address is in bits 31:24 of DP_SELECT */
866 return ERROR_COMMAND_SYNTAX_ERROR
;
868 ap_old
= dap_ap_get_select(dap
);
869 dap_ap_select(dap
, ap
);
871 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_BASE
, dbgbase
);
872 if (retval
!= ERROR_OK
)
874 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, apid
);
875 if (retval
!= ERROR_OK
)
877 retval
= dap_run(dap
);
878 if (retval
!= ERROR_OK
)
881 dap_ap_select(dap
, ap_old
);
886 int dap_lookup_cs_component(struct adiv5_dap
*dap
, int ap
,
887 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
)
890 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
894 return ERROR_COMMAND_SYNTAX_ERROR
;
897 ap_old
= dap_ap_get_select(dap
);
898 dap_ap_select(dap
, ap
);
901 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) |
902 entry_offset
, &romentry
);
903 if (retval
!= ERROR_OK
)
906 component_base
= (dbgbase
& 0xFFFFF000)
907 + (romentry
& 0xFFFFF000);
909 if (romentry
& 0x1) {
911 retval
= mem_ap_read_atomic_u32(dap
, component_base
| 0xff4, &c_cid1
);
912 if (retval
!= ERROR_OK
) {
913 LOG_ERROR("Can't read component with base address 0x%" PRIx32
914 ", the corresponding core might be turned off", component_base
);
917 if (((c_cid1
>> 4) & 0x0f) == 1) {
918 retval
= dap_lookup_cs_component(dap
, ap
, component_base
,
920 if (retval
== ERROR_OK
)
922 if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
926 retval
= mem_ap_read_atomic_u32(dap
,
927 (component_base
& 0xfffff000) | 0xfcc,
929 if (retval
!= ERROR_OK
)
931 if ((devtype
& 0xff) == type
) {
933 *addr
= component_base
;
940 } while (romentry
> 0);
942 dap_ap_select(dap
, ap_old
);
945 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
950 static int dap_rom_display(struct command_context
*cmd_ctx
,
951 struct adiv5_dap
*dap
, int ap
, uint32_t dbgbase
, int depth
)
954 uint32_t cid0
, cid1
, cid2
, cid3
, memtype
, romentry
;
955 uint16_t entry_offset
;
959 command_print(cmd_ctx
, "\tTables too deep");
964 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
966 /* bit 16 of apid indicates a memory access port */
968 command_print(cmd_ctx
, "\t%sValid ROM table present", tabs
);
970 command_print(cmd_ctx
, "\t%sROM table in legacy format", tabs
);
972 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
973 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
974 if (retval
!= ERROR_OK
)
976 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
977 if (retval
!= ERROR_OK
)
979 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
980 if (retval
!= ERROR_OK
)
982 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
983 if (retval
!= ERROR_OK
)
985 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
986 if (retval
!= ERROR_OK
)
988 retval
= dap_run(dap
);
989 if (retval
!= ERROR_OK
)
992 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
993 command_print(cmd_ctx
, "\t%sCID3 0x%02x"
998 (unsigned)cid3
, (unsigned)cid2
,
999 (unsigned)cid1
, (unsigned)cid0
);
1001 command_print(cmd_ctx
, "\t%sMEMTYPE system memory present on bus", tabs
);
1003 command_print(cmd_ctx
, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs
);
1005 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1006 for (entry_offset
= 0; ; entry_offset
+= 4) {
1007 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1008 if (retval
!= ERROR_OK
)
1010 command_print(cmd_ctx
, "\t%sROMTABLE[0x%x] = 0x%" PRIx32
"",
1011 tabs
, entry_offset
, romentry
);
1012 if (romentry
& 0x01) {
1013 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1014 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1015 uint32_t component_base
;
1017 const char *type
, *full
;
1019 component_base
= (dbgbase
& 0xFFFFF000) + (romentry
& 0xFFFFF000);
1021 /* IDs are in last 4K section */
1022 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE0, &c_pid0
);
1023 if (retval
!= ERROR_OK
) {
1024 command_print(cmd_ctx
, "\t%s\tCan't read component with base address 0x%" PRIx32
1025 ", the corresponding core might be turned off", tabs
, component_base
);
1029 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE4, &c_pid1
);
1030 if (retval
!= ERROR_OK
)
1033 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE8, &c_pid2
);
1034 if (retval
!= ERROR_OK
)
1037 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFEC, &c_pid3
);
1038 if (retval
!= ERROR_OK
)
1041 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFD0, &c_pid4
);
1042 if (retval
!= ERROR_OK
)
1046 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF0, &c_cid0
);
1047 if (retval
!= ERROR_OK
)
1050 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF4, &c_cid1
);
1051 if (retval
!= ERROR_OK
)
1054 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF8, &c_cid2
);
1055 if (retval
!= ERROR_OK
)
1058 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFFC, &c_cid3
);
1059 if (retval
!= ERROR_OK
)
1063 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
", "
1064 "start address 0x%" PRIx32
, component_base
,
1065 /* component may take multiple 4K pages */
1066 (uint32_t)(component_base
- 0x1000*(c_pid4
>> 4)));
1067 command_print(cmd_ctx
, "\t\tComponent class is 0x%" PRIx8
", %s",
1068 (uint8_t)((c_cid1
>> 4) & 0xf),
1069 /* See ARM IHI 0029B Table 3-3 */
1070 class_description
[(c_cid1
>> 4) & 0xf]);
1072 /* CoreSight component? */
1073 if (((c_cid1
>> 4) & 0x0f) == 9) {
1076 const char *major
= "Reserved", *subtype
= "Reserved";
1078 retval
= mem_ap_read_atomic_u32(dap
,
1079 (component_base
& 0xfffff000) | 0xfcc,
1081 if (retval
!= ERROR_OK
)
1083 minor
= (devtype
>> 4) & 0x0f;
1084 switch (devtype
& 0x0f) {
1086 major
= "Miscellaneous";
1092 subtype
= "Validation component";
1097 major
= "Trace Sink";
1114 major
= "Trace Link";
1120 subtype
= "Funnel, router";
1126 subtype
= "FIFO, buffer";
1131 major
= "Trace Source";
1137 subtype
= "Processor";
1143 subtype
= "Engine/Coprocessor";
1149 subtype
= "Software";
1154 major
= "Debug Control";
1160 subtype
= "Trigger Matrix";
1163 subtype
= "Debug Auth";
1166 subtype
= "Power Requestor";
1171 major
= "Debug Logic";
1177 subtype
= "Processor";
1183 subtype
= "Engine/Coprocessor";
1194 major
= "Perfomance Monitor";
1200 subtype
= "Processor";
1206 subtype
= "Engine/Coprocessor";
1217 command_print(cmd_ctx
, "\t\tType is 0x%02" PRIx8
", %s, %s",
1218 (uint8_t)(devtype
& 0xff),
1220 /* REVISIT also show 0xfc8 DevId */
1223 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1224 command_print(cmd_ctx
,
1233 command_print(cmd_ctx
,
1234 "\t\tPeripheral ID[4..0] = hex "
1235 "%02x %02x %02x %02x %02x",
1236 (int)c_pid4
, (int)c_pid3
, (int)c_pid2
,
1237 (int)c_pid1
, (int)c_pid0
);
1239 /* Part number interpretations are from Cortex
1240 * core specs, the CoreSight components TRM
1241 * (ARM DDI 0314H), CoreSight System Design
1242 * Guide (ARM DGI 0012D) and ETM specs; also
1243 * from chip observation (e.g. TI SDTI).
1245 part_num
= (c_pid0
& 0xff);
1246 part_num
|= (c_pid1
& 0x0f) << 8;
1249 type
= "Cortex-M3 NVIC";
1250 full
= "(Interrupt Controller)";
1253 type
= "Cortex-M3 ITM";
1254 full
= "(Instrumentation Trace Module)";
1257 type
= "Cortex-M3 DWT";
1258 full
= "(Data Watchpoint and Trace)";
1261 type
= "Cortex-M3 FBP";
1262 full
= "(Flash Patch and Breakpoint)";
1265 type
= "Cortex-M0 SCS";
1266 full
= "(System Control Space)";
1269 type
= "Cortex-M0 DWT";
1270 full
= "(Data Watchpoint and Trace)";
1273 type
= "Cortex-M0 BPU";
1274 full
= "(Breakpoint Unit)";
1277 type
= "Cortex-M4 SCS";
1278 full
= "(System Control Space)";
1281 type
= "CoreSight ETM11";
1282 full
= "(Embedded Trace)";
1284 /* case 0x113: what? */
1285 case 0x120: /* from OMAP3 memmap */
1287 full
= "(System Debug Trace Interface)";
1289 case 0x343: /* from OMAP3 memmap */
1294 type
= "Coresight CTI";
1295 full
= "(Cross Trigger)";
1298 type
= "Coresight ETB";
1299 full
= "(Trace Buffer)";
1302 type
= "Coresight CSTF";
1303 full
= "(Trace Funnel)";
1306 type
= "CoreSight ETM9";
1307 full
= "(Embedded Trace)";
1310 type
= "Coresight TPIU";
1311 full
= "(Trace Port Interface Unit)";
1314 type
= "Coresight ITM";
1315 full
= "(Instrumentation Trace Macrocell)";
1318 type
= "Coresight SWO";
1319 full
= "(Single Wire Output)";
1322 type
= "Coresight HTM";
1323 full
= "(AHB Trace Macrocell)";
1326 type
= "CoreSight ETM11";
1327 full
= "(Embedded Trace)";
1330 type
= "Cortex-A8 ETM";
1331 full
= "(Embedded Trace)";
1334 type
= "Cortex-A8 CTI";
1335 full
= "(Cross Trigger)";
1338 type
= "Cortex-M3 TPIU";
1339 full
= "(Trace Port Interface Unit)";
1342 type
= "Cortex-M3 ETM";
1343 full
= "(Embedded Trace)";
1346 type
= "Cortex-M4 ETM";
1347 full
= "(Embedded Trace)";
1350 type
= "Cortex-R4 ETM";
1351 full
= "(Embedded Trace)";
1354 type
= "CoreSight Component";
1355 full
= "(unidentified Cortex-A9 component)";
1358 type
= "CoreSight TMC";
1359 full
= "(Trace Memory Controller)";
1362 type
= "CoreSight STM";
1363 full
= "(System Trace Macrocell)";
1366 type
= "CoreSight PMU";
1367 full
= "(Performance Monitoring Unit)";
1370 type
= "Cortex-M4 TPUI";
1371 full
= "(Trace Port Interface Unit)";
1374 type
= "Cortex-A5 ETM";
1375 full
= "(Embedded Trace)";
1378 type
= "Cortex-A5 Debug";
1379 full
= "(Debug Unit)";
1382 type
= "Cortex-A8 Debug";
1383 full
= "(Debug Unit)";
1386 type
= "Cortex-A9 Debug";
1387 full
= "(Debug Unit)";
1390 type
= "Cortex-A15 Debug";
1391 full
= "(Debug Unit)";
1394 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32
, part_num
);
1395 type
= "-*- unrecognized -*-";
1399 command_print(cmd_ctx
, "\t\tPart is %s %s",
1403 if (((c_cid1
>> 4) & 0x0f) == 1) {
1404 retval
= dap_rom_display(cmd_ctx
, dap
, ap
, component_base
, depth
+ 1);
1405 if (retval
!= ERROR_OK
)
1410 command_print(cmd_ctx
, "\t\tComponent not present");
1415 command_print(cmd_ctx
, "\t%s\tEnd of ROM table", tabs
);
1419 static int dap_info_command(struct command_context
*cmd_ctx
,
1420 struct adiv5_dap
*dap
, int ap
)
1423 uint32_t dbgbase
, apid
;
1424 int romtable_present
= 0;
1428 retval
= dap_get_debugbase(dap
, ap
, &dbgbase
, &apid
);
1429 if (retval
!= ERROR_OK
)
1432 ap_old
= dap_ap_get_select(dap
);
1433 dap_ap_select(dap
, ap
);
1435 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1436 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1437 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1439 switch (apid
&0x0F) {
1441 command_print(cmd_ctx
, "\tType is JTAG-AP");
1444 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1447 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1450 command_print(cmd_ctx
, "\tUnknown AP type");
1454 /* NOTE: a MEM-AP may have a single CoreSight component that's
1455 * not a ROM table ... or have no such components at all.
1458 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
, dbgbase
);
1460 command_print(cmd_ctx
, "No AP found at this ap 0x%x", ap
);
1462 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1463 if (romtable_present
)
1464 dap_rom_display(cmd_ctx
, dap
, ap
, dbgbase
, 0);
1466 command_print(cmd_ctx
, "\tNo ROM table present");
1467 dap_ap_select(dap
, ap_old
);
1472 COMMAND_HANDLER(handle_dap_info_command
)
1474 struct target
*target
= get_current_target(CMD_CTX
);
1475 struct arm
*arm
= target_to_arm(target
);
1476 struct adiv5_dap
*dap
= arm
->dap
;
1484 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1487 return ERROR_COMMAND_SYNTAX_ERROR
;
1490 return dap_info_command(CMD_CTX
, dap
, apsel
);
1493 COMMAND_HANDLER(dap_baseaddr_command
)
1495 struct target
*target
= get_current_target(CMD_CTX
);
1496 struct arm
*arm
= target_to_arm(target
);
1497 struct adiv5_dap
*dap
= arm
->dap
;
1499 uint32_t apsel
, baseaddr
;
1507 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1508 /* AP address is in bits 31:24 of DP_SELECT */
1510 return ERROR_COMMAND_SYNTAX_ERROR
;
1513 return ERROR_COMMAND_SYNTAX_ERROR
;
1516 dap_ap_select(dap
, apsel
);
1518 /* NOTE: assumes we're talking to a MEM-AP, which
1519 * has a base address. There are other kinds of AP,
1520 * though they're not common for now. This should
1521 * use the ID register to verify it's a MEM-AP.
1523 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_BASE
, &baseaddr
);
1524 if (retval
!= ERROR_OK
)
1526 retval
= dap_run(dap
);
1527 if (retval
!= ERROR_OK
)
1530 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1535 COMMAND_HANDLER(dap_memaccess_command
)
1537 struct target
*target
= get_current_target(CMD_CTX
);
1538 struct arm
*arm
= target_to_arm(target
);
1539 struct adiv5_dap
*dap
= arm
->dap
;
1541 uint32_t memaccess_tck
;
1545 memaccess_tck
= dap
->ap
[dap
->apsel
].memaccess_tck
;
1548 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1551 return ERROR_COMMAND_SYNTAX_ERROR
;
1553 dap
->ap
[dap
->apsel
].memaccess_tck
= memaccess_tck
;
1555 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1556 dap
->ap
[dap
->apsel
].memaccess_tck
);
1561 COMMAND_HANDLER(dap_apsel_command
)
1563 struct target
*target
= get_current_target(CMD_CTX
);
1564 struct arm
*arm
= target_to_arm(target
);
1565 struct adiv5_dap
*dap
= arm
->dap
;
1567 uint32_t apsel
, apid
;
1575 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1576 /* AP address is in bits 31:24 of DP_SELECT */
1578 return ERROR_COMMAND_SYNTAX_ERROR
;
1581 return ERROR_COMMAND_SYNTAX_ERROR
;
1585 dap_ap_select(dap
, apsel
);
1587 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1588 if (retval
!= ERROR_OK
)
1590 retval
= dap_run(dap
);
1591 if (retval
!= ERROR_OK
)
1594 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1600 COMMAND_HANDLER(dap_apcsw_command
)
1602 struct target
*target
= get_current_target(CMD_CTX
);
1603 struct arm
*arm
= target_to_arm(target
);
1604 struct adiv5_dap
*dap
= arm
->dap
;
1606 uint32_t apcsw
= dap
->ap
[dap
->apsel
].csw_default
, sprot
= 0;
1610 command_print(CMD_CTX
, "apsel %" PRIi32
" selected, csw 0x%8.8" PRIx32
,
1611 (dap
->apsel
), apcsw
);
1614 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], sprot
);
1615 /* AP address is in bits 31:24 of DP_SELECT */
1617 return ERROR_COMMAND_SYNTAX_ERROR
;
1621 apcsw
&= ~CSW_SPROT
;
1624 return ERROR_COMMAND_SYNTAX_ERROR
;
1626 dap
->ap
[dap
->apsel
].csw_default
= apcsw
;
1633 COMMAND_HANDLER(dap_apid_command
)
1635 struct target
*target
= get_current_target(CMD_CTX
);
1636 struct arm
*arm
= target_to_arm(target
);
1637 struct adiv5_dap
*dap
= arm
->dap
;
1639 uint32_t apsel
, apid
;
1647 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1648 /* AP address is in bits 31:24 of DP_SELECT */
1650 return ERROR_COMMAND_SYNTAX_ERROR
;
1653 return ERROR_COMMAND_SYNTAX_ERROR
;
1656 dap_ap_select(dap
, apsel
);
1658 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1659 if (retval
!= ERROR_OK
)
1661 retval
= dap_run(dap
);
1662 if (retval
!= ERROR_OK
)
1665 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1670 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
1672 struct target
*target
= get_current_target(CMD_CTX
);
1673 struct arm
*arm
= target_to_arm(target
);
1674 struct adiv5_dap
*dap
= arm
->dap
;
1676 uint32_t enable
= dap
->ti_be_32_quirks
;
1682 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], enable
);
1684 return ERROR_COMMAND_SYNTAX_ERROR
;
1687 return ERROR_COMMAND_SYNTAX_ERROR
;
1689 dap
->ti_be_32_quirks
= enable
;
1690 command_print(CMD_CTX
, "TI BE-32 quirks mode %s",
1691 enable
? "enabled" : "disabled");
1696 static const struct command_registration dap_commands
[] = {
1699 .handler
= handle_dap_info_command
,
1700 .mode
= COMMAND_EXEC
,
1701 .help
= "display ROM table for MEM-AP "
1702 "(default currently selected AP)",
1703 .usage
= "[ap_num]",
1707 .handler
= dap_apsel_command
,
1708 .mode
= COMMAND_EXEC
,
1709 .help
= "Set the currently selected AP (default 0) "
1710 "and display the result",
1711 .usage
= "[ap_num]",
1715 .handler
= dap_apcsw_command
,
1716 .mode
= COMMAND_EXEC
,
1717 .help
= "Set csw access bit ",
1723 .handler
= dap_apid_command
,
1724 .mode
= COMMAND_EXEC
,
1725 .help
= "return ID register from AP "
1726 "(default currently selected AP)",
1727 .usage
= "[ap_num]",
1731 .handler
= dap_baseaddr_command
,
1732 .mode
= COMMAND_EXEC
,
1733 .help
= "return debug base address from MEM-AP "
1734 "(default currently selected AP)",
1735 .usage
= "[ap_num]",
1738 .name
= "memaccess",
1739 .handler
= dap_memaccess_command
,
1740 .mode
= COMMAND_EXEC
,
1741 .help
= "set/get number of extra tck for MEM-AP memory "
1742 "bus access [0-255]",
1743 .usage
= "[cycles]",
1746 .name
= "ti_be_32_quirks",
1747 .handler
= dap_ti_be_32_quirks_command
,
1748 .mode
= COMMAND_CONFIG
,
1749 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
1750 .usage
= "[enable]",
1752 COMMAND_REGISTRATION_DONE
1755 const struct command_registration dap_command_handlers
[] = {
1758 .mode
= COMMAND_EXEC
,
1759 .help
= "DAP command group",
1761 .chain
= dap_commands
,
1763 COMMAND_REGISTRATION_DONE
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