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ARM: dap info fix + tweaks
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 /**
28 * @file
29 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
30 * debugging architecture. Compared with previous versions, this includes
31 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
32 * transport, and focusses on memory mapped resources as defined by the
33 * CoreSight architecture.
34 *
35 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
36 * basic components: a Debug Port (DP) transporting messages to and from a
37 * debugger, and an Access Port (AP) accessing resources. Three types of DP
38 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
39 * One uses only SWD for communication, and is called SW-DP. The third can
40 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
41 * is used to access memory mapped resources and is called a MEM-AP. Also a
42 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
43 */
44
45 /*
46 * Relevant specifications from ARM include:
47 *
48 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
49 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
50 *
51 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
52 * Cortex-M3(tm) TRM, ARM DDI 0337G
53 */
54
55 #ifdef HAVE_CONFIG_H
56 #include "config.h"
57 #endif
58
59 #include "arm_adi_v5.h"
60 #include <helper/time_support.h>
61
62 /*
63 * Transaction Mode:
64 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
65 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
66 * result checking until swjdp_end_transaction()
67 * This must be done before using or deallocating any return variables.
68 * swjdp->trans_mode == TRANS_MODE_ATOMIC
69 * All reads and writes to the AHB bus are checked for valid completion, and return values
70 * are immediatley available.
71 */
72
73
74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
75
76 /*
77 uint32_t tar_block_size(uint32_t address)
78 Return the largest block starting at address that does not cross a tar block size alignment boundary
79 */
80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
81 {
82 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
83 }
84
85 /***************************************************************************
86 * *
87 * DPACC and APACC scanchain access through JTAG-DP *
88 * *
89 ***************************************************************************/
90
91 /* Scan out and in from target ordered uint8_t buffers */
92 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
93 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
94 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
95 {
96 struct arm_jtag *jtag_info = swjdp->jtag_info;
97 struct scan_field fields[2];
98 uint8_t out_addr_buf;
99
100 jtag_set_end_state(TAP_IDLE);
101 arm_jtag_set_instr(jtag_info, instr, NULL);
102
103 /* Add specified number of tck clocks before accessing memory bus */
104 if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
105 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
106
107 fields[0].tap = jtag_info->tap;
108 fields[0].num_bits = 3;
109 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
110 fields[0].out_value = &out_addr_buf;
111 fields[0].in_value = ack;
112
113 fields[1].tap = jtag_info->tap;
114 fields[1].num_bits = 32;
115 fields[1].out_value = outvalue;
116 fields[1].in_value = invalue;
117
118 jtag_add_dr_scan(2, fields, jtag_get_end_state());
119
120 return ERROR_OK;
121 }
122
123 /* Scan out and in from host ordered uint32_t variables */
124 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
125 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
126 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
127 {
128 struct arm_jtag *jtag_info = swjdp->jtag_info;
129 struct scan_field fields[2];
130 uint8_t out_value_buf[4];
131 uint8_t out_addr_buf;
132
133 jtag_set_end_state(TAP_IDLE);
134 arm_jtag_set_instr(jtag_info, instr, NULL);
135
136 /* Add specified number of tck clocks before accessing memory bus */
137 if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
138 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
139
140 fields[0].tap = jtag_info->tap;
141 fields[0].num_bits = 3;
142 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
143 fields[0].out_value = &out_addr_buf;
144 fields[0].in_value = ack;
145
146 fields[1].tap = jtag_info->tap;
147 fields[1].num_bits = 32;
148 buf_set_u32(out_value_buf, 0, 32, outvalue);
149 fields[1].out_value = out_value_buf;
150 fields[1].in_value = NULL;
151
152 if (invalue)
153 {
154 fields[1].in_value = (uint8_t *)invalue;
155 jtag_add_dr_scan(2, fields, jtag_get_end_state());
156
157 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
158 } else
159 {
160
161 jtag_add_dr_scan(2, fields, jtag_get_end_state());
162 }
163
164 return ERROR_OK;
165 }
166
167 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
168 static int scan_inout_check(struct swjdp_common *swjdp,
169 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
170 uint8_t *outvalue, uint8_t *invalue)
171 {
172 adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
173
174 if ((RnW == DPAP_READ) && (invalue != NULL))
175 {
176 adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
177 }
178
179 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */
180 if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
181 {
182 return swjdp_transaction_endcheck(swjdp);
183 }
184
185 return ERROR_OK;
186 }
187
188 static int scan_inout_check_u32(struct swjdp_common *swjdp,
189 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
190 uint32_t outvalue, uint32_t *invalue)
191 {
192 adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
193
194 if ((RnW == DPAP_READ) && (invalue != NULL))
195 {
196 adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
197 }
198
199 /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */
200 if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
201 {
202 return swjdp_transaction_endcheck(swjdp);
203 }
204
205 return ERROR_OK;
206 }
207
208 int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
209 {
210 int retval;
211 uint32_t ctrlstat;
212
213 /* too expensive to call keep_alive() here */
214
215 #if 0
216 /* Danger!!!! BROKEN!!!! */
217 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
218 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
219 R956 introduced the check on return value here and now Michael Schwingen reports
220 that this code no longer works....
221
222 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
223 */
224 if ((retval = jtag_execute_queue()) != ERROR_OK)
225 {
226 LOG_ERROR("BUG: Why does this fail the first time????");
227 }
228 /* Why??? second time it works??? */
229 #endif
230
231 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
232 if ((retval = jtag_execute_queue()) != ERROR_OK)
233 return retval;
234
235 swjdp->ack = swjdp->ack & 0x7;
236
237 if (swjdp->ack != 2)
238 {
239 long long then = timeval_ms();
240 while (swjdp->ack != 2)
241 {
242 if (swjdp->ack == 1)
243 {
244 if ((timeval_ms()-then) > 1000)
245 {
246 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
247 return ERROR_JTAG_DEVICE_ERROR;
248 }
249 }
250 else
251 {
252 LOG_WARNING("Invalid ACK in SWJDP transaction");
253 return ERROR_JTAG_DEVICE_ERROR;
254 }
255
256 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
257 if ((retval = jtag_execute_queue()) != ERROR_OK)
258 return retval;
259 swjdp->ack = swjdp->ack & 0x7;
260 }
261 } else
262 {
263 /* common code path avoids fn to timeval_ms() */
264 }
265
266 /* Check for STICKYERR and STICKYORUN */
267 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
268 {
269 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
270 /* Check power to debug regions */
271 if ((ctrlstat & 0xf0000000) != 0xf0000000)
272 {
273 ahbap_debugport_init(swjdp);
274 }
275 else
276 {
277 uint32_t mem_ap_csw, mem_ap_tar;
278
279 /* Print information about last AHBAP access */
280 LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
281 if (ctrlstat & SSTICKYORUN)
282 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
283
284 if (ctrlstat & SSTICKYERR)
285 LOG_ERROR("SWJ-DP STICKY ERROR");
286
287 /* Clear Sticky Error Bits */
288 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
289 scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
290 if ((retval = jtag_execute_queue()) != ERROR_OK)
291 return retval;
292
293 LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
294
295 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
296 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
297 if ((retval = jtag_execute_queue()) != ERROR_OK)
298 return retval;
299 LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
300
301 }
302 if ((retval = jtag_execute_queue()) != ERROR_OK)
303 return retval;
304 return ERROR_JTAG_DEVICE_ERROR;
305 }
306
307 return ERROR_OK;
308 }
309
310 /***************************************************************************
311 * *
312 * DP and MEM-AP register access through APACC and DPACC *
313 * *
314 ***************************************************************************/
315
316 static int dap_dp_write_reg(struct swjdp_common *swjdp,
317 uint32_t value, uint8_t reg_addr)
318 {
319 return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
320 }
321
322 static int dap_dp_read_reg(struct swjdp_common *swjdp,
323 uint32_t *value, uint8_t reg_addr)
324 {
325 return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
326 }
327
328 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
329 {
330 uint32_t select;
331 select = (apsel << 24) & 0xFF000000;
332
333 if (select != swjdp->apsel)
334 {
335 swjdp->apsel = select;
336 /* Switching AP invalidates cached values */
337 swjdp->dp_select_value = -1;
338 swjdp->ap_csw_value = -1;
339 swjdp->ap_tar_value = -1;
340 }
341
342 return ERROR_OK;
343 }
344
345 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
346 {
347 uint32_t select;
348 select = (ap_reg & 0x000000F0);
349
350 if (select != swjdp->dp_select_value)
351 {
352 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
353 swjdp->dp_select_value = select;
354 }
355
356 return ERROR_OK;
357 }
358
359 static int dap_ap_write_reg(struct swjdp_common *swjdp,
360 uint32_t reg_addr, uint8_t *out_value_buf)
361 {
362 dap_dp_bankselect(swjdp, reg_addr);
363 scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
364
365 return ERROR_OK;
366 }
367
368 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
369 {
370 uint8_t out_value_buf[4];
371
372 buf_set_u32(out_value_buf, 0, 32, value);
373 dap_dp_bankselect(swjdp, reg_addr);
374 scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
375
376 return ERROR_OK;
377 }
378
379 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
380 {
381 dap_dp_bankselect(swjdp, reg_addr);
382 scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value);
383
384 return ERROR_OK;
385 }
386
387 /***************************************************************************
388 * *
389 * AHB-AP access to memory and system registers on AHB bus *
390 * *
391 ***************************************************************************/
392
393 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
394 {
395 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
396 if (csw != swjdp->ap_csw_value)
397 {
398 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
399 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
400 swjdp->ap_csw_value = csw;
401 }
402 if (tar != swjdp->ap_tar_value)
403 {
404 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
405 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
406 swjdp->ap_tar_value = tar;
407 }
408 if (csw & CSW_ADDRINC_MASK)
409 {
410 /* Do not cache TAR value when autoincrementing */
411 swjdp->ap_tar_value = -1;
412 }
413 return ERROR_OK;
414 }
415
416 /*****************************************************************************
417 * *
418 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
419 * *
420 * Read a uint32_t value from memory or system register *
421 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
422 * but with less overhead *
423 *****************************************************************************/
424 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
425 {
426 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
427
428 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
429 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
430
431 return ERROR_OK;
432 }
433
434 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
435 {
436 mem_ap_read_u32(swjdp, address, value);
437
438 return swjdp_transaction_endcheck(swjdp);
439 }
440
441 /*****************************************************************************
442 * *
443 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
444 * *
445 * Write a uint32_t value to memory or memory mapped register *
446 * *
447 *****************************************************************************/
448 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
449 {
450 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
451
452 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
453 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
454
455 return ERROR_OK;
456 }
457
458 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
459 {
460 mem_ap_write_u32(swjdp, address, value);
461
462 return swjdp_transaction_endcheck(swjdp);
463 }
464
465 /*****************************************************************************
466 * *
467 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
468 * *
469 * Write a buffer in target order (little endian) *
470 * *
471 *****************************************************************************/
472 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
473 {
474 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
475 uint32_t adr = address;
476 uint8_t* pBuffer = buffer;
477
478 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
479
480 count >>= 2;
481 wcount = count;
482
483 /* if we have an unaligned access - reorder data */
484 if (adr & 0x3u)
485 {
486 for (writecount = 0; writecount < count; writecount++)
487 {
488 int i;
489 uint32_t outvalue;
490 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
491
492 for (i = 0; i < 4; i++)
493 {
494 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
495 outvalue >>= 8;
496 adr++;
497 }
498 pBuffer += sizeof(uint32_t);
499 }
500 }
501
502 while (wcount > 0)
503 {
504 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
505 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
506 if (wcount < blocksize)
507 blocksize = wcount;
508
509 /* handle unaligned data at 4k boundary */
510 if (blocksize == 0)
511 blocksize = 1;
512
513 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
514
515 for (writecount = 0; writecount < blocksize; writecount++)
516 {
517 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
518 }
519
520 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
521 {
522 wcount = wcount - blocksize;
523 address = address + 4 * blocksize;
524 buffer = buffer + 4 * blocksize;
525 }
526 else
527 {
528 errorcount++;
529 }
530
531 if (errorcount > 1)
532 {
533 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
534 return ERROR_JTAG_DEVICE_ERROR;
535 }
536 }
537
538 return retval;
539 }
540
541 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
542 uint8_t *buffer, int count, uint32_t address)
543 {
544 int retval = ERROR_OK;
545 int wcount, blocksize, writecount, i;
546
547 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
548
549 wcount = count >> 1;
550
551 while (wcount > 0)
552 {
553 int nbytes;
554
555 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
556 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
557
558 if (wcount < blocksize)
559 blocksize = wcount;
560
561 /* handle unaligned data at 4k boundary */
562 if (blocksize == 0)
563 blocksize = 1;
564
565 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
566 writecount = blocksize;
567
568 do
569 {
570 nbytes = MIN((writecount << 1), 4);
571
572 if (nbytes < 4)
573 {
574 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
575 {
576 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
577 return ERROR_JTAG_DEVICE_ERROR;
578 }
579
580 address += nbytes >> 1;
581 }
582 else
583 {
584 uint32_t outvalue;
585 memcpy(&outvalue, buffer, sizeof(uint32_t));
586
587 for (i = 0; i < nbytes; i++)
588 {
589 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
590 outvalue >>= 8;
591 address++;
592 }
593
594 memcpy(&outvalue, buffer, sizeof(uint32_t));
595 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
596 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
597 {
598 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
599 return ERROR_JTAG_DEVICE_ERROR;
600 }
601 }
602
603 buffer += nbytes >> 1;
604 writecount -= nbytes >> 1;
605
606 } while (writecount);
607 wcount -= blocksize;
608 }
609
610 return retval;
611 }
612
613 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
614 {
615 int retval = ERROR_OK;
616
617 if (count >= 4)
618 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
619
620 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
621
622 while (count > 0)
623 {
624 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
625 uint16_t svalue;
626 memcpy(&svalue, buffer, sizeof(uint16_t));
627 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
628 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
629 retval = swjdp_transaction_endcheck(swjdp);
630 count -= 2;
631 address += 2;
632 buffer += 2;
633 }
634
635 return retval;
636 }
637
638 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
639 uint8_t *buffer, int count, uint32_t address)
640 {
641 int retval = ERROR_OK;
642 int wcount, blocksize, writecount, i;
643
644 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
645
646 wcount = count;
647
648 while (wcount > 0)
649 {
650 int nbytes;
651
652 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
653 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
654
655 if (wcount < blocksize)
656 blocksize = wcount;
657
658 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
659 writecount = blocksize;
660
661 do
662 {
663 nbytes = MIN(writecount, 4);
664
665 if (nbytes < 4)
666 {
667 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
668 {
669 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
670 return ERROR_JTAG_DEVICE_ERROR;
671 }
672
673 address += nbytes;
674 }
675 else
676 {
677 uint32_t outvalue;
678 memcpy(&outvalue, buffer, sizeof(uint32_t));
679
680 for (i = 0; i < nbytes; i++)
681 {
682 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
683 outvalue >>= 8;
684 address++;
685 }
686
687 memcpy(&outvalue, buffer, sizeof(uint32_t));
688 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
689 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
690 {
691 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
692 return ERROR_JTAG_DEVICE_ERROR;
693 }
694 }
695
696 buffer += nbytes;
697 writecount -= nbytes;
698
699 } while (writecount);
700 wcount -= blocksize;
701 }
702
703 return retval;
704 }
705
706 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
707 {
708 int retval = ERROR_OK;
709
710 if (count >= 4)
711 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
712
713 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
714
715 while (count > 0)
716 {
717 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
718 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
719 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
720 retval = swjdp_transaction_endcheck(swjdp);
721 count--;
722 address++;
723 buffer++;
724 }
725
726 return retval;
727 }
728
729 /*********************************************************************************
730 * *
731 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
732 * *
733 * Read block fast in target order (little endian) into a buffer *
734 * *
735 **********************************************************************************/
736 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
737 {
738 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
739 uint32_t adr = address;
740 uint8_t* pBuffer = buffer;
741
742 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
743
744 count >>= 2;
745 wcount = count;
746
747 while (wcount > 0)
748 {
749 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
750 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
751 if (wcount < blocksize)
752 blocksize = wcount;
753
754 /* handle unaligned data at 4k boundary */
755 if (blocksize == 0)
756 blocksize = 1;
757
758 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
759
760 /* Scan out first read */
761 adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
762 for (readcount = 0; readcount < blocksize - 1; readcount++)
763 {
764 /* Scan out read instruction and scan in previous value */
765 adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
766 }
767
768 /* Scan in last value */
769 adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
770 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
771 {
772 wcount = wcount - blocksize;
773 address += 4 * blocksize;
774 buffer += 4 * blocksize;
775 }
776 else
777 {
778 errorcount++;
779 }
780
781 if (errorcount > 1)
782 {
783 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
784 return ERROR_JTAG_DEVICE_ERROR;
785 }
786 }
787
788 /* if we have an unaligned access - reorder data */
789 if (adr & 0x3u)
790 {
791 for (readcount = 0; readcount < count; readcount++)
792 {
793 int i;
794 uint32_t data;
795 memcpy(&data, pBuffer, sizeof(uint32_t));
796
797 for (i = 0; i < 4; i++)
798 {
799 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
800 pBuffer++;
801 adr++;
802 }
803 }
804 }
805
806 return retval;
807 }
808
809 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
810 uint8_t *buffer, int count, uint32_t address)
811 {
812 uint32_t invalue;
813 int retval = ERROR_OK;
814 int wcount, blocksize, readcount, i;
815
816 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
817
818 wcount = count >> 1;
819
820 while (wcount > 0)
821 {
822 int nbytes;
823
824 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
825 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
826 if (wcount < blocksize)
827 blocksize = wcount;
828
829 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
830
831 /* handle unaligned data at 4k boundary */
832 if (blocksize == 0)
833 blocksize = 1;
834 readcount = blocksize;
835
836 do
837 {
838 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
839 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
840 {
841 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
842 return ERROR_JTAG_DEVICE_ERROR;
843 }
844
845 nbytes = MIN((readcount << 1), 4);
846
847 for (i = 0; i < nbytes; i++)
848 {
849 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
850 buffer++;
851 address++;
852 }
853
854 readcount -= (nbytes >> 1);
855 } while (readcount);
856 wcount -= blocksize;
857 }
858
859 return retval;
860 }
861
862 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
863 {
864 uint32_t invalue, i;
865 int retval = ERROR_OK;
866
867 if (count >= 4)
868 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
869
870 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
871
872 while (count > 0)
873 {
874 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
875 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
876 retval = swjdp_transaction_endcheck(swjdp);
877 if (address & 0x1)
878 {
879 for (i = 0; i < 2; i++)
880 {
881 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
882 buffer++;
883 address++;
884 }
885 }
886 else
887 {
888 uint16_t svalue = (invalue >> 8 * (address & 0x3));
889 memcpy(buffer, &svalue, sizeof(uint16_t));
890 address += 2;
891 buffer += 2;
892 }
893 count -= 2;
894 }
895
896 return retval;
897 }
898
899 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
900 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
901 *
902 * The solution is to arrange for a large out/in scan in this loop and
903 * and convert data afterwards.
904 */
905 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
906 uint8_t *buffer, int count, uint32_t address)
907 {
908 uint32_t invalue;
909 int retval = ERROR_OK;
910 int wcount, blocksize, readcount, i;
911
912 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
913
914 wcount = count;
915
916 while (wcount > 0)
917 {
918 int nbytes;
919
920 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
921 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
922
923 if (wcount < blocksize)
924 blocksize = wcount;
925
926 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
927 readcount = blocksize;
928
929 do
930 {
931 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
932 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
933 {
934 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
935 return ERROR_JTAG_DEVICE_ERROR;
936 }
937
938 nbytes = MIN(readcount, 4);
939
940 for (i = 0; i < nbytes; i++)
941 {
942 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
943 buffer++;
944 address++;
945 }
946
947 readcount -= nbytes;
948 } while (readcount);
949 wcount -= blocksize;
950 }
951
952 return retval;
953 }
954
955 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
956 {
957 uint32_t invalue;
958 int retval = ERROR_OK;
959
960 if (count >= 4)
961 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
962
963 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
964
965 while (count > 0)
966 {
967 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
968 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
969 retval = swjdp_transaction_endcheck(swjdp);
970 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
971 count--;
972 address++;
973 buffer++;
974 }
975
976 return retval;
977 }
978
979 /**
980 * Initialize a DAP.
981 *
982 * @todo Rename this. We also need an initialization scheme which account
983 * for SWD transports not just JTAG; that will need to address differences
984 * in layering. (JTAG is useful without any debug target; but not SWD.)
985 */
986 int ahbap_debugport_init(struct swjdp_common *swjdp)
987 {
988 uint32_t idreg, romaddr, dummy;
989 uint32_t ctrlstat;
990 int cnt = 0;
991 int retval;
992
993 LOG_DEBUG(" ");
994
995 /* Default MEM-AP setup.
996 *
997 * REVISIT AP #0 may be an inappropriate default for this.
998 * Should we probe, or receve a hint from the caller?
999 * Presumably we can ignore the possibility of multiple APs.
1000 */
1001 swjdp->apsel = 0;
1002 swjdp->ap_csw_value = -1;
1003 swjdp->ap_tar_value = -1;
1004
1005 /* DP initialization */
1006 swjdp->trans_mode = TRANS_MODE_ATOMIC;
1007 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1008 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1009 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1010
1011 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1012
1013 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1014 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1015 if ((retval = jtag_execute_queue()) != ERROR_OK)
1016 return retval;
1017
1018 /* Check that we have debug power domains activated */
1019 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1020 {
1021 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1022 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1023 if ((retval = jtag_execute_queue()) != ERROR_OK)
1024 return retval;
1025 alive_sleep(10);
1026 }
1027
1028 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1029 {
1030 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1031 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1032 if ((retval = jtag_execute_queue()) != ERROR_OK)
1033 return retval;
1034 alive_sleep(10);
1035 }
1036
1037 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1038 /* With debug power on we can activate OVERRUN checking */
1039 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1040 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1041 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1042
1043 /*
1044 * REVISIT this isn't actually *initializing* anything in an AP,
1045 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1046 * Should it? If the ROM address is valid, is this the right
1047 * place to scan the table and do any topology detection?
1048 */
1049 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1050 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1051
1052 LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
1053
1054 return ERROR_OK;
1055 }
1056
1057 /* CID interpretation -- see ARM IHI 0029B section 3
1058 * and ARM IHI 0031A table 13-3.
1059 */
1060 static const char *class_description[16] ={
1061 "Reserved", "ROM table", "Reserved", "Reserved",
1062 "Reserved", "Reserved", "Reserved", "Reserved",
1063 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1064 "Reserved", "OptimoDE DESS",
1065 "Generic IP component", "PrimeCell or System component"
1066 };
1067
1068 static bool
1069 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1070 {
1071 return cid3 == 0xb1 && cid2 == 0x05
1072 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1073 }
1074
1075 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1076 {
1077
1078 uint32_t dbgbase, apid;
1079 int romtable_present = 0;
1080 uint8_t mem_ap;
1081 uint32_t apselold;
1082
1083 apselold = swjdp->apsel;
1084 dap_ap_select(swjdp, apsel);
1085 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1086 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1087 swjdp_transaction_endcheck(swjdp);
1088 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1089 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1090 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1091 if (apid)
1092 {
1093 switch (apid&0x0F)
1094 {
1095 case 0:
1096 command_print(cmd_ctx, "\tType is JTAG-AP");
1097 break;
1098 case 1:
1099 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1100 break;
1101 case 2:
1102 command_print(cmd_ctx, "\tType is MEM-AP APB");
1103 break;
1104 default:
1105 command_print(cmd_ctx, "\tUnknown AP type");
1106 break;
1107 }
1108
1109 /* NOTE: a MEM-AP may have a single CoreSight component that's
1110 * not a ROM table ... or have no such components at all.
1111 */
1112 if (mem_ap)
1113 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1114 dbgbase);
1115 }
1116 else
1117 {
1118 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1119 }
1120
1121 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1122 if (romtable_present)
1123 {
1124 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1125 uint16_t entry_offset;
1126
1127 /* bit 16 of apid indicates a memory access port */
1128 if (dbgbase & 0x02)
1129 command_print(cmd_ctx, "\tValid ROM table present");
1130 else
1131 command_print(cmd_ctx, "\tROM table in legacy format");
1132
1133 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1134 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1135 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1136 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1137 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1138 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1139 swjdp_transaction_endcheck(swjdp);
1140 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1141 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1142 ", CID2 0x%2.2" PRIx32
1143 ", CID1 0x%2.2" PRIx32
1144 ", CID0 0x%2.2" PRIx32,
1145 cid3, cid2, cid1, cid0);
1146 if (memtype & 0x01)
1147 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1148 else
1149 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1150 "Dedicated debug bus.");
1151
1152 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1153 entry_offset = 0;
1154 do
1155 {
1156 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1157 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1158 if (romentry&0x01)
1159 {
1160 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1161 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1162 uint32_t component_start, component_base;
1163 unsigned part_num;
1164 char *type, *full;
1165
1166 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1167 + (int)(romentry & 0xFFFFF000));
1168 mem_ap_read_atomic_u32(swjdp,
1169 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1170 mem_ap_read_atomic_u32(swjdp,
1171 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1172 mem_ap_read_atomic_u32(swjdp,
1173 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1174 mem_ap_read_atomic_u32(swjdp,
1175 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1176 mem_ap_read_atomic_u32(swjdp,
1177 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1178 mem_ap_read_atomic_u32(swjdp,
1179 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1180 mem_ap_read_atomic_u32(swjdp,
1181 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1182 mem_ap_read_atomic_u32(swjdp,
1183 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1184 mem_ap_read_atomic_u32(swjdp,
1185 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1186 component_start = component_base - 0x1000*(c_pid4 >> 4);
1187
1188 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1189 ", start address 0x%" PRIx32,
1190 component_base, component_start);
1191 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1192 (int) (c_cid1 >> 4) & 0xf,
1193 /* See ARM IHI 0029B Table 3-3 */
1194 class_description[(c_cid1 >> 4) & 0xf]);
1195
1196 /* CoreSight component? */
1197 if (((c_cid1 >> 4) & 0x0f) == 9) {
1198 uint32_t devtype;
1199 unsigned minor;
1200 char *major = "Reserved", *subtype = "Reserved";
1201
1202 mem_ap_read_atomic_u32(swjdp,
1203 (component_base & 0xfffff000) | 0xfcc,
1204 &devtype);
1205 minor = (devtype >> 4) & 0x0f;
1206 switch (devtype & 0x0f) {
1207 case 0:
1208 major = "Miscellaneous";
1209 switch (minor) {
1210 case 0:
1211 subtype = "other";
1212 break;
1213 case 4:
1214 subtype = "Validation component";
1215 break;
1216 }
1217 break;
1218 case 1:
1219 major = "Trace Sink";
1220 switch (minor) {
1221 case 0:
1222 subtype = "other";
1223 break;
1224 case 1:
1225 subtype = "Port";
1226 break;
1227 case 2:
1228 subtype = "Buffer";
1229 break;
1230 }
1231 break;
1232 case 2:
1233 major = "Trace Link";
1234 switch (minor) {
1235 case 0:
1236 subtype = "other";
1237 break;
1238 case 1:
1239 subtype = "Funnel, router";
1240 break;
1241 case 2:
1242 subtype = "Filter";
1243 break;
1244 case 3:
1245 subtype = "FIFO, buffer";
1246 break;
1247 }
1248 break;
1249 case 3:
1250 major = "Trace Source";
1251 switch (minor) {
1252 case 0:
1253 subtype = "other";
1254 break;
1255 case 1:
1256 subtype = "Processor";
1257 break;
1258 case 2:
1259 subtype = "DSP";
1260 break;
1261 case 3:
1262 subtype = "Engine/Coprocessor";
1263 break;
1264 case 4:
1265 subtype = "Bus";
1266 break;
1267 }
1268 break;
1269 case 4:
1270 major = "Debug Control";
1271 switch (minor) {
1272 case 0:
1273 subtype = "other";
1274 break;
1275 case 1:
1276 subtype = "Trigger Matrix";
1277 break;
1278 case 2:
1279 subtype = "Debug Auth";
1280 break;
1281 }
1282 break;
1283 case 5:
1284 major = "Debug Logic";
1285 switch (minor) {
1286 case 0:
1287 subtype = "other";
1288 break;
1289 case 1:
1290 subtype = "Processor";
1291 break;
1292 case 2:
1293 subtype = "DSP";
1294 break;
1295 case 3:
1296 subtype = "Engine/Coprocessor";
1297 break;
1298 }
1299 break;
1300 }
1301 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1302 (unsigned) (devtype & 0xff),
1303 major, subtype);
1304 /* REVISIT also show 0xfc8 DevId */
1305 }
1306
1307 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1308 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1309 ", CID2 0x%2.2" PRIx32
1310 ", CID1 0x%2.2" PRIx32
1311 ", CID0 0x%2.2" PRIx32,
1312 c_cid3, c_cid2, c_cid1, c_cid0);
1313 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1314 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1315 (int) c_pid4,
1316 (int) c_pid3, (int) c_pid2,
1317 (int) c_pid1, (int) c_pid0);
1318
1319 /* Part number interpretations are from Cortex
1320 * core specs, the CoreSight components TRM
1321 * (ARM DDI 0314H), and ETM specs; also from
1322 * chip observation (e.g. TI SDTI).
1323 */
1324 part_num = c_pid0 & 0xff;
1325 part_num |= (c_pid1 & 0x0f) << 8;
1326 switch (part_num) {
1327 case 0x000:
1328 type = "Cortex-M3 NVIC";
1329 full = "(Interrupt Controller)";
1330 break;
1331 case 0x001:
1332 type = "Cortex-M3 ITM";
1333 full = "(Instrumentation Trace Module)";
1334 break;
1335 case 0x002:
1336 type = "Cortex-M3 DWT";
1337 full = "(Data Watchpoint and Trace)";
1338 break;
1339 case 0x003:
1340 type = "Cortex-M3 FBP";
1341 full = "(Flash Patch and Breakpoint)";
1342 break;
1343 case 0x00d:
1344 type = "CoreSight ETM11";
1345 full = "(Embedded Trace)";
1346 break;
1347 // case 0x113: what?
1348 case 0x120: /* from OMAP3 memmap */
1349 type = "TI SDTI";
1350 full = "(System Debug Trace Interface)";
1351 break;
1352 case 0x343: /* from OMAP3 memmap */
1353 type = "TI DAPCTL";
1354 full = "";
1355 break;
1356 case 0x4e0:
1357 type = "Cortex-M3 ETM";
1358 full = "(Embedded Trace)";
1359 break;
1360 case 0x906:
1361 type = "Coresight CTI";
1362 full = "(Cross Trigger)";
1363 break;
1364 case 0x907:
1365 type = "Coresight ETB";
1366 full = "(Trace Buffer)";
1367 break;
1368 case 0x908:
1369 type = "Coresight CSTF";
1370 full = "(Trace Funnel)";
1371 break;
1372 case 0x910:
1373 type = "CoreSight ETM9";
1374 full = "(Embedded Trace)";
1375 break;
1376 case 0x912:
1377 type = "Coresight TPIU";
1378 full = "(Trace Port Interface Unit)";
1379 break;
1380 case 0x921:
1381 type = "Cortex-A8 ETM";
1382 full = "(Embedded Trace)";
1383 break;
1384 case 0x922:
1385 type = "Cortex-A8 CTI";
1386 full = "(Cross Trigger)";
1387 break;
1388 case 0x923:
1389 type = "Cortex-M3 TPIU";
1390 full = "(Trace Port Interface Unit)";
1391 break;
1392 case 0xc08:
1393 type = "Cortex-A8 Debug";
1394 full = "(Debug Unit)";
1395 break;
1396 default:
1397 type = "-*- unrecognized -*-";
1398 full = "";
1399 break;
1400 }
1401 command_print(cmd_ctx, "\t\tPart is %s %s",
1402 type, full);
1403 }
1404 else
1405 {
1406 if (romentry)
1407 command_print(cmd_ctx, "\t\tComponent not present");
1408 else
1409 command_print(cmd_ctx, "\t\tEnd of ROM table");
1410 }
1411 entry_offset += 4;
1412 } while (romentry > 0);
1413 }
1414 else
1415 {
1416 command_print(cmd_ctx, "\tNo ROM table present");
1417 }
1418 dap_ap_select(swjdp, apselold);
1419
1420 return ERROR_OK;
1421 }
1422
1423 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1424 {
1425 uint32_t apsel, apselsave, baseaddr;
1426 int retval;
1427
1428 apselsave = swjdp->apsel;
1429 switch (CMD_ARGC) {
1430 case 0:
1431 apsel = swjdp->apsel;
1432 break;
1433 case 1:
1434 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1435 break;
1436 default:
1437 return ERROR_COMMAND_SYNTAX_ERROR;
1438 }
1439
1440 if (apselsave != apsel)
1441 dap_ap_select(swjdp, apsel);
1442
1443 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1444 retval = swjdp_transaction_endcheck(swjdp);
1445 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1446
1447 if (apselsave != apsel)
1448 dap_ap_select(swjdp, apselsave);
1449
1450 return retval;
1451 }
1452
1453 DAP_COMMAND_HANDLER(dap_memaccess_command)
1454 {
1455 uint32_t memaccess_tck;
1456
1457 switch (CMD_ARGC) {
1458 case 0:
1459 memaccess_tck = swjdp->memaccess_tck;
1460 break;
1461 case 1:
1462 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1463 break;
1464 default:
1465 return ERROR_COMMAND_SYNTAX_ERROR;
1466 }
1467 swjdp->memaccess_tck = memaccess_tck;
1468
1469 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1470 swjdp->memaccess_tck);
1471
1472 return ERROR_OK;
1473 }
1474
1475 DAP_COMMAND_HANDLER(dap_apsel_command)
1476 {
1477 uint32_t apsel, apid;
1478 int retval;
1479
1480 switch (CMD_ARGC) {
1481 case 0:
1482 apsel = 0;
1483 break;
1484 case 1:
1485 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1486 break;
1487 default:
1488 return ERROR_COMMAND_SYNTAX_ERROR;
1489 }
1490
1491 dap_ap_select(swjdp, apsel);
1492 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1493 retval = swjdp_transaction_endcheck(swjdp);
1494 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1495 apsel, apid);
1496
1497 return retval;
1498 }
1499
1500 DAP_COMMAND_HANDLER(dap_apid_command)
1501 {
1502 uint32_t apsel, apselsave, apid;
1503 int retval;
1504
1505 apselsave = swjdp->apsel;
1506 switch (CMD_ARGC) {
1507 case 0:
1508 apsel = swjdp->apsel;
1509 break;
1510 case 1:
1511 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1512 break;
1513 default:
1514 return ERROR_COMMAND_SYNTAX_ERROR;
1515 }
1516
1517 if (apselsave != apsel)
1518 dap_ap_select(swjdp, apsel);
1519
1520 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1521 retval = swjdp_transaction_endcheck(swjdp);
1522 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1523 if (apselsave != apsel)
1524 dap_ap_select(swjdp, apselsave);
1525
1526 return retval;
1527 }
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