1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
29 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
30 * debugging architecture. Compared with previous versions, this includes
31 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
32 * transport, and focusses on memory mapped resources as defined by the
33 * CoreSight architecture.
35 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
36 * basic components: a Debug Port (DP) transporting messages to and from a
37 * debugger, and an Access Port (AP) accessing resources. Three types of DP
38 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
39 * One uses only SWD for communication, and is called SW-DP. The third can
40 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
41 * is used to access memory mapped resources and is called a MEM-AP. Also a
42 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * Relevant specifications from ARM include:
48 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
49 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
51 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
52 * Cortex-M3(tm) TRM, ARM DDI 0337G
59 #include "arm_adi_v5.h"
60 #include <helper/time_support.h>
64 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
65 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
66 * result checking until swjdp_end_transaction()
67 * This must be done before using or deallocating any return variables.
68 * swjdp->trans_mode == TRANS_MODE_ATOMIC
69 * All reads and writes to the AHB bus are checked for valid completion, and return values
70 * are immediatley available.
74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
77 uint32_t tar_block_size(uint32_t address)
78 Return the largest block starting at address that does not cross a tar block size alignment boundary
80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
82 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
85 /***************************************************************************
87 * DPACC and APACC scanchain access through JTAG-DP *
89 ***************************************************************************/
92 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
93 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
94 * discusses operations which access these registers.
96 * Note that only one scan is performed. If RnW is set, a separate scan
97 * will be needed to collect the data which was read; the "invalue" collects
98 * the posted result of a preceding operation, not the current one.
100 * @param swjdp the DAP
101 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
102 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
103 * SELECT register has more addressing bits.
104 * @param RnW false iff outvalue will be written to the DP or AP
105 * @param outvalue points to a 32-bit (little-endian) integer
106 * @param invalue NULL, or points to a 32-bit (little-endian) integer
107 * @param ack points to where the three bit JTAG_ACK_* code will be stored
109 static int adi_jtag_dp_scan(struct swjdp_common
*swjdp
,
110 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
111 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
113 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
114 struct scan_field fields
[2];
115 uint8_t out_addr_buf
;
117 jtag_set_end_state(TAP_IDLE
);
118 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
120 /* Add specified number of tck clocks before accessing memory bus */
122 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
123 * they provide more time for the (MEM) AP to complete the read ...
124 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
126 if ((instr
== JTAG_DP_APACC
)
127 && ((reg_addr
== AP_REG_DRW
)
128 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
129 && (swjdp
->memaccess_tck
!= 0))
130 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
132 /* Scan out a read or write operation using some DP or AP register.
133 * For APACC access with any sticky error flag set, this is discarded.
135 fields
[0].tap
= jtag_info
->tap
;
136 fields
[0].num_bits
= 3;
137 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
138 fields
[0].out_value
= &out_addr_buf
;
139 fields
[0].in_value
= ack
;
141 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
142 * complete; data we write is discarded, data we read is unpredictable.
143 * When overrun detect is active, STICKYORUN is set.
146 fields
[1].tap
= jtag_info
->tap
;
147 fields
[1].num_bits
= 32;
148 fields
[1].out_value
= outvalue
;
149 fields
[1].in_value
= invalue
;
151 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
156 /* Scan out and in from host ordered uint32_t variables */
157 static int adi_jtag_dp_scan_u32(struct swjdp_common
*swjdp
,
158 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
159 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
161 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
162 struct scan_field fields
[2];
163 uint8_t out_value_buf
[4];
164 uint8_t out_addr_buf
;
166 jtag_set_end_state(TAP_IDLE
);
167 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
169 /* Add specified number of tck clocks before accessing memory bus */
171 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
172 * they provide more time for the (MEM) AP to complete the read ...
174 if ((instr
== JTAG_DP_APACC
)
175 && ((reg_addr
== AP_REG_DRW
)
176 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
177 && (swjdp
->memaccess_tck
!= 0))
178 jtag_add_runtest(swjdp
->memaccess_tck
, jtag_set_end_state(TAP_IDLE
));
180 fields
[0].tap
= jtag_info
->tap
;
181 fields
[0].num_bits
= 3;
182 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
183 fields
[0].out_value
= &out_addr_buf
;
184 fields
[0].in_value
= ack
;
186 fields
[1].tap
= jtag_info
->tap
;
187 fields
[1].num_bits
= 32;
188 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
189 fields
[1].out_value
= out_value_buf
;
190 fields
[1].in_value
= NULL
;
194 fields
[1].in_value
= (uint8_t *)invalue
;
195 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
197 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
) invalue
);
201 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
207 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
208 static int scan_inout_check(struct swjdp_common
*swjdp
,
209 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
210 uint8_t *outvalue
, uint8_t *invalue
)
212 adi_jtag_dp_scan(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
214 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
215 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
,
216 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
218 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
219 * ack = OK/FAULT and the check CTRL_STAT
221 if ((instr
== JTAG_DP_APACC
)
222 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
223 return swjdp_transaction_endcheck(swjdp
);
228 static int scan_inout_check_u32(struct swjdp_common
*swjdp
,
229 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
230 uint32_t outvalue
, uint32_t *invalue
)
232 /* Issue the read or write */
233 adi_jtag_dp_scan_u32(swjdp
, instr
, reg_addr
, RnW
, outvalue
, NULL
, NULL
);
235 /* For reads, collect posted value; RDBUFF has no other effect.
236 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
238 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
239 adi_jtag_dp_scan_u32(swjdp
, JTAG_DP_DPACC
,
240 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
242 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
243 * ack = OK/FAULT and then check CTRL_STAT
245 if ((instr
== JTAG_DP_APACC
)
246 && (swjdp
->trans_mode
== TRANS_MODE_ATOMIC
))
247 return swjdp_transaction_endcheck(swjdp
);
252 int swjdp_transaction_endcheck(struct swjdp_common
*swjdp
)
257 /* too expensive to call keep_alive() here */
260 /* Danger!!!! BROKEN!!!! */
261 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
262 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
263 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
264 R956 introduced the check on return value here and now Michael Schwingen reports
265 that this code no longer works....
267 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
269 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
271 LOG_ERROR("BUG: Why does this fail the first time????");
273 /* Why??? second time it works??? */
276 /* Post CTRL/STAT read; discard any previous posted read value
277 * but collect its ACK status.
279 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
280 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
281 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
284 swjdp
->ack
= swjdp
->ack
& 0x7;
286 /* common code path avoids calling timeval_ms() */
287 if (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
289 long long then
= timeval_ms();
291 while (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
293 if (swjdp
->ack
== JTAG_ACK_WAIT
)
295 if ((timeval_ms()-then
) > 1000)
297 /* NOTE: this would be a good spot
298 * to use JTAG_DP_ABORT.
300 LOG_WARNING("Timeout (1000ms) waiting "
302 "in JTAG-DP transaction");
303 return ERROR_JTAG_DEVICE_ERROR
;
308 LOG_WARNING("Invalid ACK "
309 "in JTAG-DP transaction");
310 return ERROR_JTAG_DEVICE_ERROR
;
313 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
314 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
315 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
317 swjdp
->ack
= swjdp
->ack
& 0x7;
321 /* Check for STICKYERR and STICKYORUN */
322 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
324 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32
"", ctrlstat
);
325 /* Check power to debug regions */
326 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
328 ahbap_debugport_init(swjdp
);
332 uint32_t mem_ap_csw
, mem_ap_tar
;
334 /* Print information about last AHBAP access */
335 LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
", ap_csw 0x%" PRIx32
", ap_tar 0x%" PRIx32
"", swjdp
->dp_select_value
, swjdp
->ap_csw_value
, swjdp
->ap_tar_value
);
336 if (ctrlstat
& SSTICKYORUN
)
337 LOG_ERROR("JTAG-DP OVERRUN - "
338 "check clock or reduce jtag speed");
340 if (ctrlstat
& SSTICKYERR
)
341 LOG_ERROR("JTAG-DP STICKY ERROR");
343 /* Clear Sticky Error Bits */
344 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
345 DP_CTRL_STAT
, DPAP_WRITE
,
346 swjdp
->dp_ctrl_stat
| SSTICKYORUN
348 scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
349 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
350 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
353 LOG_DEBUG("swjdp: status 0x%" PRIx32
"", ctrlstat
);
355 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
356 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
357 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
359 LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%" PRIx32
"", mem_ap_csw
, mem_ap_tar
);
362 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
364 return ERROR_JTAG_DEVICE_ERROR
;
370 /***************************************************************************
372 * DP and MEM-AP register access through APACC and DPACC *
374 ***************************************************************************/
376 static int dap_dp_write_reg(struct swjdp_common
*swjdp
,
377 uint32_t value
, uint8_t reg_addr
)
379 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
380 reg_addr
, DPAP_WRITE
, value
, NULL
);
383 static int dap_dp_read_reg(struct swjdp_common
*swjdp
,
384 uint32_t *value
, uint8_t reg_addr
)
386 return scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
387 reg_addr
, DPAP_READ
, 0, value
);
390 int dap_ap_select(struct swjdp_common
*swjdp
,uint8_t apsel
)
393 select
= (apsel
<< 24) & 0xFF000000;
395 if (select
!= swjdp
->apsel
)
397 swjdp
->apsel
= select
;
398 /* Switching AP invalidates cached values */
399 swjdp
->dp_select_value
= -1;
400 swjdp
->ap_csw_value
= -1;
401 swjdp
->ap_tar_value
= -1;
407 static int dap_dp_bankselect(struct swjdp_common
*swjdp
, uint32_t ap_reg
)
410 select
= (ap_reg
& 0x000000F0);
412 if (select
!= swjdp
->dp_select_value
)
414 dap_dp_write_reg(swjdp
, select
| swjdp
->apsel
, DP_SELECT
);
415 swjdp
->dp_select_value
= select
;
421 static int dap_ap_write_reg(struct swjdp_common
*swjdp
,
422 uint32_t reg_addr
, uint8_t *out_value_buf
)
424 dap_dp_bankselect(swjdp
, reg_addr
);
425 scan_inout_check(swjdp
, JTAG_DP_APACC
, reg_addr
,
426 DPAP_WRITE
, out_value_buf
, NULL
);
431 int dap_ap_write_reg_u32(struct swjdp_common
*swjdp
, uint32_t reg_addr
, uint32_t value
)
433 uint8_t out_value_buf
[4];
435 buf_set_u32(out_value_buf
, 0, 32, value
);
436 dap_dp_bankselect(swjdp
, reg_addr
);
437 scan_inout_check(swjdp
, JTAG_DP_APACC
, reg_addr
,
438 DPAP_WRITE
, out_value_buf
, NULL
);
443 int dap_ap_read_reg_u32(struct swjdp_common
*swjdp
, uint32_t reg_addr
, uint32_t *value
)
445 dap_dp_bankselect(swjdp
, reg_addr
);
446 scan_inout_check_u32(swjdp
, JTAG_DP_APACC
, reg_addr
,
447 DPAP_READ
, 0, value
);
452 /***************************************************************************
454 * AHB-AP access to memory and system registers on AHB bus *
456 ***************************************************************************/
458 int dap_setup_accessport(struct swjdp_common
*swjdp
, uint32_t csw
, uint32_t tar
)
460 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
461 if (csw
!= swjdp
->ap_csw_value
)
463 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
464 dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
465 swjdp
->ap_csw_value
= csw
;
467 if (tar
!= swjdp
->ap_tar_value
)
469 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
470 dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
471 swjdp
->ap_tar_value
= tar
;
473 if (csw
& CSW_ADDRINC_MASK
)
475 /* Do not cache TAR value when autoincrementing */
476 swjdp
->ap_tar_value
= -1;
481 /*****************************************************************************
483 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) *
485 * Read a uint32_t value from memory or system register *
486 * Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
487 * but with less overhead *
488 *****************************************************************************/
489 int mem_ap_read_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t *value
)
491 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
493 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
494 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
499 int mem_ap_read_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t *value
)
501 mem_ap_read_u32(swjdp
, address
, value
);
503 return swjdp_transaction_endcheck(swjdp
);
506 /*****************************************************************************
508 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) *
510 * Write a uint32_t value to memory or memory mapped register *
512 *****************************************************************************/
513 int mem_ap_write_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t value
)
515 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
517 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, address
& 0xFFFFFFF0);
518 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
523 int mem_ap_write_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
, uint32_t value
)
525 mem_ap_write_u32(swjdp
, address
, value
);
527 return swjdp_transaction_endcheck(swjdp
);
530 /*****************************************************************************
532 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
534 * Write a buffer in target order (little endian) *
536 *****************************************************************************/
537 int mem_ap_write_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
539 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
540 uint32_t adr
= address
;
541 uint8_t* pBuffer
= buffer
;
543 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
548 /* if we have an unaligned access - reorder data */
551 for (writecount
= 0; writecount
< count
; writecount
++)
555 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
557 for (i
= 0; i
< 4; i
++)
559 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
563 pBuffer
+= sizeof(uint32_t);
569 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
570 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
571 if (wcount
< blocksize
)
574 /* handle unaligned data at 4k boundary */
578 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
580 for (writecount
= 0; writecount
< blocksize
; writecount
++)
582 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
585 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
587 wcount
= wcount
- blocksize
;
588 address
= address
+ 4 * blocksize
;
589 buffer
= buffer
+ 4 * blocksize
;
598 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
599 return ERROR_JTAG_DEVICE_ERROR
;
606 static int mem_ap_write_buf_packed_u16(struct swjdp_common
*swjdp
,
607 uint8_t *buffer
, int count
, uint32_t address
)
609 int retval
= ERROR_OK
;
610 int wcount
, blocksize
, writecount
, i
;
612 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
620 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
621 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
623 if (wcount
< blocksize
)
626 /* handle unaligned data at 4k boundary */
630 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
631 writecount
= blocksize
;
635 nbytes
= MIN((writecount
<< 1), 4);
639 if (mem_ap_write_buf_u16(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
641 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
642 return ERROR_JTAG_DEVICE_ERROR
;
645 address
+= nbytes
>> 1;
650 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
652 for (i
= 0; i
< nbytes
; i
++)
654 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
659 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
660 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
661 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
663 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
664 return ERROR_JTAG_DEVICE_ERROR
;
668 buffer
+= nbytes
>> 1;
669 writecount
-= nbytes
>> 1;
671 } while (writecount
);
678 int mem_ap_write_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
680 int retval
= ERROR_OK
;
683 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
685 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
689 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
691 memcpy(&svalue
, buffer
, sizeof(uint16_t));
692 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
693 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
694 retval
= swjdp_transaction_endcheck(swjdp
);
703 static int mem_ap_write_buf_packed_u8(struct swjdp_common
*swjdp
,
704 uint8_t *buffer
, int count
, uint32_t address
)
706 int retval
= ERROR_OK
;
707 int wcount
, blocksize
, writecount
, i
;
709 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
717 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
718 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
720 if (wcount
< blocksize
)
723 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
724 writecount
= blocksize
;
728 nbytes
= MIN(writecount
, 4);
732 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
734 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
735 return ERROR_JTAG_DEVICE_ERROR
;
743 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
745 for (i
= 0; i
< nbytes
; i
++)
747 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
752 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
753 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
754 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
756 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
757 return ERROR_JTAG_DEVICE_ERROR
;
762 writecount
-= nbytes
;
764 } while (writecount
);
771 int mem_ap_write_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
773 int retval
= ERROR_OK
;
776 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
778 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
782 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
783 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
784 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
785 retval
= swjdp_transaction_endcheck(swjdp
);
794 /*********************************************************************************
796 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
798 * Read block fast in target order (little endian) into a buffer *
800 **********************************************************************************/
801 int mem_ap_read_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
803 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
804 uint32_t adr
= address
;
805 uint8_t* pBuffer
= buffer
;
807 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
814 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
815 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
816 if (wcount
< blocksize
)
819 /* handle unaligned data at 4k boundary */
823 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
825 /* Scan out first read */
826 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
827 DPAP_READ
, 0, NULL
, NULL
);
828 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
830 /* Scan out next read; scan in posted value for the
831 * previous one. Assumes read is acked "OK/FAULT",
832 * and CTRL_STAT says that meant "OK".
834 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
835 DPAP_READ
, 0, buffer
+ 4 * readcount
,
839 /* Scan in last posted value; RDBUFF has no other effect,
840 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
842 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
, DP_RDBUFF
,
843 DPAP_READ
, 0, buffer
+ 4 * readcount
,
845 if (swjdp_transaction_endcheck(swjdp
) == ERROR_OK
)
847 wcount
= wcount
- blocksize
;
848 address
+= 4 * blocksize
;
849 buffer
+= 4 * blocksize
;
858 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
859 return ERROR_JTAG_DEVICE_ERROR
;
863 /* if we have an unaligned access - reorder data */
866 for (readcount
= 0; readcount
< count
; readcount
++)
870 memcpy(&data
, pBuffer
, sizeof(uint32_t));
872 for (i
= 0; i
< 4; i
++)
874 *((uint8_t*)pBuffer
) = (data
>> 8 * (adr
& 0x3));
884 static int mem_ap_read_buf_packed_u16(struct swjdp_common
*swjdp
,
885 uint8_t *buffer
, int count
, uint32_t address
)
888 int retval
= ERROR_OK
;
889 int wcount
, blocksize
, readcount
, i
;
891 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
899 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
900 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
901 if (wcount
< blocksize
)
904 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
906 /* handle unaligned data at 4k boundary */
909 readcount
= blocksize
;
913 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
914 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
916 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
917 return ERROR_JTAG_DEVICE_ERROR
;
920 nbytes
= MIN((readcount
<< 1), 4);
922 for (i
= 0; i
< nbytes
; i
++)
924 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
929 readcount
-= (nbytes
>> 1);
937 int mem_ap_read_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
940 int retval
= ERROR_OK
;
943 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
945 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
949 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
950 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
951 retval
= swjdp_transaction_endcheck(swjdp
);
954 for (i
= 0; i
< 2; i
++)
956 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
963 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
964 memcpy(buffer
, &svalue
, sizeof(uint16_t));
974 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
975 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
977 * The solution is to arrange for a large out/in scan in this loop and
978 * and convert data afterwards.
980 static int mem_ap_read_buf_packed_u8(struct swjdp_common
*swjdp
,
981 uint8_t *buffer
, int count
, uint32_t address
)
984 int retval
= ERROR_OK
;
985 int wcount
, blocksize
, readcount
, i
;
987 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
995 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
996 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
998 if (wcount
< blocksize
)
1001 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
1002 readcount
= blocksize
;
1006 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1007 if (swjdp_transaction_endcheck(swjdp
) != ERROR_OK
)
1009 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1010 return ERROR_JTAG_DEVICE_ERROR
;
1013 nbytes
= MIN(readcount
, 4);
1015 for (i
= 0; i
< nbytes
; i
++)
1017 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1022 readcount
-= nbytes
;
1023 } while (readcount
);
1024 wcount
-= blocksize
;
1030 int mem_ap_read_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
1033 int retval
= ERROR_OK
;
1036 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
1038 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
1042 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
1043 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1044 retval
= swjdp_transaction_endcheck(swjdp
);
1045 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1057 * @todo Rename this. We also need an initialization scheme which account
1058 * for SWD transports not just JTAG; that will need to address differences
1059 * in layering. (JTAG is useful without any debug target; but not SWD.)
1061 int ahbap_debugport_init(struct swjdp_common
*swjdp
)
1063 uint32_t idreg
, romaddr
, dummy
;
1070 /* Default MEM-AP setup.
1072 * REVISIT AP #0 may be an inappropriate default for this.
1073 * Should we probe, or receve a hint from the caller?
1074 * Presumably we can ignore the possibility of multiple APs.
1077 swjdp
->ap_csw_value
= -1;
1078 swjdp
->ap_tar_value
= -1;
1080 /* DP initialization */
1081 swjdp
->trans_mode
= TRANS_MODE_ATOMIC
;
1082 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1083 dap_dp_write_reg(swjdp
, SSTICKYERR
, DP_CTRL_STAT
);
1084 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1086 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1088 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1089 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1090 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1093 /* Check that we have debug power domains activated */
1094 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
1096 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1097 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1098 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1103 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
1105 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1106 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1107 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1112 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1113 /* With debug power on we can activate OVERRUN checking */
1114 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1115 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1116 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1119 * REVISIT this isn't actually *initializing* anything in an AP,
1120 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1121 * Should it? If the ROM address is valid, is this the right
1122 * place to scan the table and do any topology detection?
1124 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &idreg
);
1125 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &romaddr
);
1127 LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32
", Debug ROM Address 0x%" PRIx32
"", idreg
, romaddr
);
1132 /* CID interpretation -- see ARM IHI 0029B section 3
1133 * and ARM IHI 0031A table 13-3.
1135 static const char *class_description
[16] ={
1136 "Reserved", "ROM table", "Reserved", "Reserved",
1137 "Reserved", "Reserved", "Reserved", "Reserved",
1138 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1139 "Reserved", "OptimoDE DESS",
1140 "Generic IP component", "PrimeCell or System component"
1144 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1146 return cid3
== 0xb1 && cid2
== 0x05
1147 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1150 int dap_info_command(struct command_context
*cmd_ctx
, struct swjdp_common
*swjdp
, int apsel
)
1153 uint32_t dbgbase
, apid
;
1154 int romtable_present
= 0;
1158 apselold
= swjdp
->apsel
;
1159 dap_ap_select(swjdp
, apsel
);
1160 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &dbgbase
);
1161 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1162 swjdp_transaction_endcheck(swjdp
);
1163 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1164 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1165 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1171 command_print(cmd_ctx
, "\tType is JTAG-AP");
1174 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1177 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1180 command_print(cmd_ctx
, "\tUnknown AP type");
1184 /* NOTE: a MEM-AP may have a single CoreSight component that's
1185 * not a ROM table ... or have no such components at all.
1188 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1193 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1196 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1197 if (romtable_present
)
1199 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1200 uint16_t entry_offset
;
1202 /* bit 16 of apid indicates a memory access port */
1204 command_print(cmd_ctx
, "\tValid ROM table present");
1206 command_print(cmd_ctx
, "\tROM table in legacy format");
1208 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1209 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1210 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1211 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1212 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1213 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1214 swjdp_transaction_endcheck(swjdp
);
1215 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1216 command_print(cmd_ctx
, "\tCID3 0x%2.2" PRIx32
1217 ", CID2 0x%2.2" PRIx32
1218 ", CID1 0x%2.2" PRIx32
1219 ", CID0 0x%2.2" PRIx32
,
1220 cid3
, cid2
, cid1
, cid0
);
1222 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1224 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1225 "Dedicated debug bus.");
1227 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1231 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1232 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1235 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1236 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1237 uint32_t component_start
, component_base
;
1241 component_base
= (uint32_t)((dbgbase
& 0xFFFFF000)
1242 + (int)(romentry
& 0xFFFFF000));
1243 mem_ap_read_atomic_u32(swjdp
,
1244 (component_base
& 0xFFFFF000) | 0xFE0, &c_pid0
);
1245 mem_ap_read_atomic_u32(swjdp
,
1246 (component_base
& 0xFFFFF000) | 0xFE4, &c_pid1
);
1247 mem_ap_read_atomic_u32(swjdp
,
1248 (component_base
& 0xFFFFF000) | 0xFE8, &c_pid2
);
1249 mem_ap_read_atomic_u32(swjdp
,
1250 (component_base
& 0xFFFFF000) | 0xFEC, &c_pid3
);
1251 mem_ap_read_atomic_u32(swjdp
,
1252 (component_base
& 0xFFFFF000) | 0xFD0, &c_pid4
);
1253 mem_ap_read_atomic_u32(swjdp
,
1254 (component_base
& 0xFFFFF000) | 0xFF0, &c_cid0
);
1255 mem_ap_read_atomic_u32(swjdp
,
1256 (component_base
& 0xFFFFF000) | 0xFF4, &c_cid1
);
1257 mem_ap_read_atomic_u32(swjdp
,
1258 (component_base
& 0xFFFFF000) | 0xFF8, &c_cid2
);
1259 mem_ap_read_atomic_u32(swjdp
,
1260 (component_base
& 0xFFFFF000) | 0xFFC, &c_cid3
);
1261 component_start
= component_base
- 0x1000*(c_pid4
>> 4);
1263 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
1264 ", start address 0x%" PRIx32
,
1265 component_base
, component_start
);
1266 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1267 (int) (c_cid1
>> 4) & 0xf,
1268 /* See ARM IHI 0029B Table 3-3 */
1269 class_description
[(c_cid1
>> 4) & 0xf]);
1271 /* CoreSight component? */
1272 if (((c_cid1
>> 4) & 0x0f) == 9) {
1275 char *major
= "Reserved", *subtype
= "Reserved";
1277 mem_ap_read_atomic_u32(swjdp
,
1278 (component_base
& 0xfffff000) | 0xfcc,
1280 minor
= (devtype
>> 4) & 0x0f;
1281 switch (devtype
& 0x0f) {
1283 major
= "Miscellaneous";
1289 subtype
= "Validation component";
1294 major
= "Trace Sink";
1308 major
= "Trace Link";
1314 subtype
= "Funnel, router";
1320 subtype
= "FIFO, buffer";
1325 major
= "Trace Source";
1331 subtype
= "Processor";
1337 subtype
= "Engine/Coprocessor";
1345 major
= "Debug Control";
1351 subtype
= "Trigger Matrix";
1354 subtype
= "Debug Auth";
1359 major
= "Debug Logic";
1365 subtype
= "Processor";
1371 subtype
= "Engine/Coprocessor";
1376 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1377 (unsigned) (devtype
& 0xff),
1379 /* REVISIT also show 0xfc8 DevId */
1382 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1383 command_print(cmd_ctx
, "\t\tCID3 0x%2.2" PRIx32
1384 ", CID2 0x%2.2" PRIx32
1385 ", CID1 0x%2.2" PRIx32
1386 ", CID0 0x%2.2" PRIx32
,
1387 c_cid3
, c_cid2
, c_cid1
, c_cid0
);
1388 command_print(cmd_ctx
, "\t\tPeripheral ID[4..0] = hex "
1389 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1391 (int) c_pid3
, (int) c_pid2
,
1392 (int) c_pid1
, (int) c_pid0
);
1394 /* Part number interpretations are from Cortex
1395 * core specs, the CoreSight components TRM
1396 * (ARM DDI 0314H), and ETM specs; also from
1397 * chip observation (e.g. TI SDTI).
1399 part_num
= c_pid0
& 0xff;
1400 part_num
|= (c_pid1
& 0x0f) << 8;
1403 type
= "Cortex-M3 NVIC";
1404 full
= "(Interrupt Controller)";
1407 type
= "Cortex-M3 ITM";
1408 full
= "(Instrumentation Trace Module)";
1411 type
= "Cortex-M3 DWT";
1412 full
= "(Data Watchpoint and Trace)";
1415 type
= "Cortex-M3 FBP";
1416 full
= "(Flash Patch and Breakpoint)";
1419 type
= "CoreSight ETM11";
1420 full
= "(Embedded Trace)";
1422 // case 0x113: what?
1423 case 0x120: /* from OMAP3 memmap */
1425 full
= "(System Debug Trace Interface)";
1427 case 0x343: /* from OMAP3 memmap */
1432 type
= "Cortex-M3 ETM";
1433 full
= "(Embedded Trace)";
1436 type
= "Coresight CTI";
1437 full
= "(Cross Trigger)";
1440 type
= "Coresight ETB";
1441 full
= "(Trace Buffer)";
1444 type
= "Coresight CSTF";
1445 full
= "(Trace Funnel)";
1448 type
= "CoreSight ETM9";
1449 full
= "(Embedded Trace)";
1452 type
= "Coresight TPIU";
1453 full
= "(Trace Port Interface Unit)";
1456 type
= "Cortex-A8 ETM";
1457 full
= "(Embedded Trace)";
1460 type
= "Cortex-A8 CTI";
1461 full
= "(Cross Trigger)";
1464 type
= "Cortex-M3 TPIU";
1465 full
= "(Trace Port Interface Unit)";
1468 type
= "Cortex-A8 Debug";
1469 full
= "(Debug Unit)";
1472 type
= "-*- unrecognized -*-";
1476 command_print(cmd_ctx
, "\t\tPart is %s %s",
1482 command_print(cmd_ctx
, "\t\tComponent not present");
1484 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1487 } while (romentry
> 0);
1491 command_print(cmd_ctx
, "\tNo ROM table present");
1493 dap_ap_select(swjdp
, apselold
);
1498 DAP_COMMAND_HANDLER(dap_baseaddr_command
)
1500 uint32_t apsel
, apselsave
, baseaddr
;
1503 apselsave
= swjdp
->apsel
;
1506 apsel
= swjdp
->apsel
;
1509 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1512 return ERROR_COMMAND_SYNTAX_ERROR
;
1515 if (apselsave
!= apsel
)
1516 dap_ap_select(swjdp
, apsel
);
1518 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &baseaddr
);
1519 retval
= swjdp_transaction_endcheck(swjdp
);
1520 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1522 if (apselsave
!= apsel
)
1523 dap_ap_select(swjdp
, apselsave
);
1528 DAP_COMMAND_HANDLER(dap_memaccess_command
)
1530 uint32_t memaccess_tck
;
1534 memaccess_tck
= swjdp
->memaccess_tck
;
1537 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1540 return ERROR_COMMAND_SYNTAX_ERROR
;
1542 swjdp
->memaccess_tck
= memaccess_tck
;
1544 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1545 swjdp
->memaccess_tck
);
1550 DAP_COMMAND_HANDLER(dap_apsel_command
)
1552 uint32_t apsel
, apid
;
1560 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1563 return ERROR_COMMAND_SYNTAX_ERROR
;
1566 dap_ap_select(swjdp
, apsel
);
1567 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1568 retval
= swjdp_transaction_endcheck(swjdp
);
1569 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1575 DAP_COMMAND_HANDLER(dap_apid_command
)
1577 uint32_t apsel
, apselsave
, apid
;
1580 apselsave
= swjdp
->apsel
;
1583 apsel
= swjdp
->apsel
;
1586 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1589 return ERROR_COMMAND_SYNTAX_ERROR
;
1592 if (apselsave
!= apsel
)
1593 dap_ap_select(swjdp
, apsel
);
1595 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1596 retval
= swjdp_transaction_endcheck(swjdp
);
1597 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1598 if (apselsave
!= apsel
)
1599 dap_ap_select(swjdp
, apselsave
);
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