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arm_adi_v5: add dap apreg command for AP register read/write
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
81
82 /*
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
85 */
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
87 {
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
89 }
90
91 /***************************************************************************
92 * *
93 * DP and MEM-AP register access through APACC and DPACC *
94 * *
95 ***************************************************************************/
96
97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
98 {
99 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
100 ap->csw_default;
101
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
106 return retval;
107 ap->csw_value = csw;
108 }
109 return ERROR_OK;
110 }
111
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
113 {
114 if (tar != ap->tar_value ||
115 (ap->csw_value & CSW_ADDRINC_MASK)) {
116 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
117 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
118 if (retval != ERROR_OK)
119 return retval;
120 ap->tar_value = tar;
121 }
122 return ERROR_OK;
123 }
124
125 /**
126 * Queue transactions setting up transfer parameters for the
127 * currently selected MEM-AP.
128 *
129 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
130 * initiate data reads or writes using memory or peripheral addresses.
131 * If the CSW is configured for it, the TAR may be automatically
132 * incremented after each transfer.
133 *
134 * @param ap The MEM-AP.
135 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
136 * matches the cached value, the register is not changed.
137 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
138 * matches the cached address, the register is not changed.
139 *
140 * @return ERROR_OK if the transaction was properly queued, else a fault code.
141 */
142 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
143 {
144 int retval;
145 retval = mem_ap_setup_csw(ap, csw);
146 if (retval != ERROR_OK)
147 return retval;
148 retval = mem_ap_setup_tar(ap, tar);
149 if (retval != ERROR_OK)
150 return retval;
151 return ERROR_OK;
152 }
153
154 /**
155 * Asynchronous (queued) read of a word from memory or a system register.
156 *
157 * @param ap The MEM-AP to access.
158 * @param address Address of the 32-bit word to read; it must be
159 * readable by the currently selected MEM-AP.
160 * @param value points to where the word will be stored when the
161 * transaction queue is flushed (assuming no errors).
162 *
163 * @return ERROR_OK for success. Otherwise a fault code.
164 */
165 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
166 uint32_t *value)
167 {
168 int retval;
169
170 /* Use banked addressing (REG_BDx) to avoid some link traffic
171 * (updating TAR) when reading several consecutive addresses.
172 */
173 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
174 address & 0xFFFFFFF0);
175 if (retval != ERROR_OK)
176 return retval;
177
178 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
179 }
180
181 /**
182 * Synchronous read of a word from memory or a system register.
183 * As a side effect, this flushes any queued transactions.
184 *
185 * @param ap The MEM-AP to access.
186 * @param address Address of the 32-bit word to read; it must be
187 * readable by the currently selected MEM-AP.
188 * @param value points to where the result will be stored.
189 *
190 * @return ERROR_OK for success; *value holds the result.
191 * Otherwise a fault code.
192 */
193 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
194 uint32_t *value)
195 {
196 int retval;
197
198 retval = mem_ap_read_u32(ap, address, value);
199 if (retval != ERROR_OK)
200 return retval;
201
202 return dap_run(ap->dap);
203 }
204
205 /**
206 * Asynchronous (queued) write of a word to memory or a system register.
207 *
208 * @param ap The MEM-AP to access.
209 * @param address Address to be written; it must be writable by
210 * the currently selected MEM-AP.
211 * @param value Word that will be written to the address when transaction
212 * queue is flushed (assuming no errors).
213 *
214 * @return ERROR_OK for success. Otherwise a fault code.
215 */
216 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
217 uint32_t value)
218 {
219 int retval;
220
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when writing several consecutive addresses.
223 */
224 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
225 address & 0xFFFFFFF0);
226 if (retval != ERROR_OK)
227 return retval;
228
229 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
230 value);
231 }
232
233 /**
234 * Synchronous write of a word to memory or a system register.
235 * As a side effect, this flushes any queued transactions.
236 *
237 * @param ap The MEM-AP to access.
238 * @param address Address to be written; it must be writable by
239 * the currently selected MEM-AP.
240 * @param value Word that will be written.
241 *
242 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
243 */
244 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
245 uint32_t value)
246 {
247 int retval = mem_ap_write_u32(ap, address, value);
248
249 if (retval != ERROR_OK)
250 return retval;
251
252 return dap_run(ap->dap);
253 }
254
255 /**
256 * Synchronous write of a block of memory, using a specific access size.
257 *
258 * @param ap The MEM-AP to access.
259 * @param buffer The data buffer to write. No particular alignment is assumed.
260 * @param size Which access size to use, in bytes. 1, 2 or 4.
261 * @param count The number of writes to do (in size units, not bytes).
262 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
263 * @param addrinc Whether the target address should be increased for each write or not. This
264 * should normally be true, except when writing to e.g. a FIFO.
265 * @return ERROR_OK on success, otherwise an error code.
266 */
267 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
268 uint32_t address, bool addrinc)
269 {
270 struct adiv5_dap *dap = ap->dap;
271 size_t nbytes = size * count;
272 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
273 uint32_t csw_size;
274 uint32_t addr_xor;
275 int retval;
276
277 /* TI BE-32 Quirks mode:
278 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
279 * size write address bytes written in order
280 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
281 * 2 TAR ^ 2 (val >> 8), (val)
282 * 1 TAR ^ 3 (val)
283 * For example, if you attempt to write a single byte to address 0, the processor
284 * will actually write a byte to address 3.
285 *
286 * To make writes of size < 4 work as expected, we xor a value with the address before
287 * setting the TAP, and we set the TAP after every transfer rather then relying on
288 * address increment. */
289
290 if (size == 4) {
291 csw_size = CSW_32BIT;
292 addr_xor = 0;
293 } else if (size == 2) {
294 csw_size = CSW_16BIT;
295 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
296 } else if (size == 1) {
297 csw_size = CSW_8BIT;
298 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
299 } else {
300 return ERROR_TARGET_UNALIGNED_ACCESS;
301 }
302
303 if (ap->unaligned_access_bad && (address % size != 0))
304 return ERROR_TARGET_UNALIGNED_ACCESS;
305
306 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
307 if (retval != ERROR_OK)
308 return retval;
309
310 while (nbytes > 0) {
311 uint32_t this_size = size;
312
313 /* Select packed transfer if possible */
314 if (addrinc && ap->packed_transfers && nbytes >= 4
315 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
316 this_size = 4;
317 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
318 } else {
319 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
320 }
321
322 if (retval != ERROR_OK)
323 break;
324
325 /* How many source bytes each transfer will consume, and their location in the DRW,
326 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
327 uint32_t outvalue = 0;
328 if (dap->ti_be_32_quirks) {
329 switch (this_size) {
330 case 4:
331 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
332 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
333 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
334 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
335 break;
336 case 2:
337 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
338 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
339 break;
340 case 1:
341 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
342 break;
343 }
344 } else {
345 switch (this_size) {
346 case 4:
347 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
348 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
349 case 2:
350 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
351 case 1:
352 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
353 }
354 }
355
356 nbytes -= this_size;
357
358 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
359 if (retval != ERROR_OK)
360 break;
361
362 /* Rewrite TAR if it wrapped or we're xoring addresses */
363 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
364 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
365 if (retval != ERROR_OK)
366 break;
367 }
368 }
369
370 /* REVISIT: Might want to have a queued version of this function that does not run. */
371 if (retval == ERROR_OK)
372 retval = dap_run(dap);
373
374 if (retval != ERROR_OK) {
375 uint32_t tar;
376 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
377 && dap_run(dap) == ERROR_OK)
378 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
379 else
380 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
381 }
382
383 return retval;
384 }
385
386 /**
387 * Synchronous read of a block of memory, using a specific access size.
388 *
389 * @param ap The MEM-AP to access.
390 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
391 * @param size Which access size to use, in bytes. 1, 2 or 4.
392 * @param count The number of reads to do (in size units, not bytes).
393 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
394 * @param addrinc Whether the target address should be increased after each read or not. This
395 * should normally be true, except when reading from e.g. a FIFO.
396 * @return ERROR_OK on success, otherwise an error code.
397 */
398 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
399 uint32_t adr, bool addrinc)
400 {
401 struct adiv5_dap *dap = ap->dap;
402 size_t nbytes = size * count;
403 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
404 uint32_t csw_size;
405 uint32_t address = adr;
406 int retval;
407
408 /* TI BE-32 Quirks mode:
409 * Reads on big-endian TMS570 behave strangely differently than writes.
410 * They read from the physical address requested, but with DRW byte-reversed.
411 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
412 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
413 * so avoid them. */
414
415 if (size == 4)
416 csw_size = CSW_32BIT;
417 else if (size == 2)
418 csw_size = CSW_16BIT;
419 else if (size == 1)
420 csw_size = CSW_8BIT;
421 else
422 return ERROR_TARGET_UNALIGNED_ACCESS;
423
424 if (ap->unaligned_access_bad && (adr % size != 0))
425 return ERROR_TARGET_UNALIGNED_ACCESS;
426
427 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
428 * over-allocation if packed transfers are going to be used, but determining the real need at
429 * this point would be messy. */
430 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
431 uint32_t *read_ptr = read_buf;
432 if (read_buf == NULL) {
433 LOG_ERROR("Failed to allocate read buffer");
434 return ERROR_FAIL;
435 }
436
437 retval = mem_ap_setup_tar(ap, address);
438 if (retval != ERROR_OK) {
439 free(read_buf);
440 return retval;
441 }
442
443 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
444 * useful bytes it contains, and their location in the word, depends on the type of transfer
445 * and alignment. */
446 while (nbytes > 0) {
447 uint32_t this_size = size;
448
449 /* Select packed transfer if possible */
450 if (addrinc && ap->packed_transfers && nbytes >= 4
451 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
452 this_size = 4;
453 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
454 } else {
455 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
456 }
457 if (retval != ERROR_OK)
458 break;
459
460 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
461 if (retval != ERROR_OK)
462 break;
463
464 nbytes -= this_size;
465 address += this_size;
466
467 /* Rewrite TAR if it wrapped */
468 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
469 retval = mem_ap_setup_tar(ap, address);
470 if (retval != ERROR_OK)
471 break;
472 }
473 }
474
475 if (retval == ERROR_OK)
476 retval = dap_run(dap);
477
478 /* Restore state */
479 address = adr;
480 nbytes = size * count;
481 read_ptr = read_buf;
482
483 /* If something failed, read TAR to find out how much data was successfully read, so we can
484 * at least give the caller what we have. */
485 if (retval != ERROR_OK) {
486 uint32_t tar;
487 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
488 && dap_run(dap) == ERROR_OK) {
489 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
490 if (nbytes > tar - address)
491 nbytes = tar - address;
492 } else {
493 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
494 nbytes = 0;
495 }
496 }
497
498 /* Replay loop to populate caller's buffer from the correct word and byte lane */
499 while (nbytes > 0) {
500 uint32_t this_size = size;
501
502 if (addrinc && ap->packed_transfers && nbytes >= 4
503 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
504 this_size = 4;
505 }
506
507 if (dap->ti_be_32_quirks) {
508 switch (this_size) {
509 case 4:
510 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
511 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
512 case 2:
513 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
514 case 1:
515 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
516 }
517 } else {
518 switch (this_size) {
519 case 4:
520 *buffer++ = *read_ptr >> 8 * (address++ & 3);
521 *buffer++ = *read_ptr >> 8 * (address++ & 3);
522 case 2:
523 *buffer++ = *read_ptr >> 8 * (address++ & 3);
524 case 1:
525 *buffer++ = *read_ptr >> 8 * (address++ & 3);
526 }
527 }
528
529 read_ptr++;
530 nbytes -= this_size;
531 }
532
533 free(read_buf);
534 return retval;
535 }
536
537 int mem_ap_read_buf(struct adiv5_ap *ap,
538 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
539 {
540 return mem_ap_read(ap, buffer, size, count, address, true);
541 }
542
543 int mem_ap_write_buf(struct adiv5_ap *ap,
544 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
545 {
546 return mem_ap_write(ap, buffer, size, count, address, true);
547 }
548
549 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
550 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
551 {
552 return mem_ap_read(ap, buffer, size, count, address, false);
553 }
554
555 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
556 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
557 {
558 return mem_ap_write(ap, buffer, size, count, address, false);
559 }
560
561 /*--------------------------------------------------------------------------*/
562
563
564 #define DAP_POWER_DOMAIN_TIMEOUT (10)
565
566 /* FIXME don't import ... just initialize as
567 * part of DAP transport setup
568 */
569 extern const struct dap_ops jtag_dp_ops;
570
571 /*--------------------------------------------------------------------------*/
572
573 /**
574 * Create a new DAP
575 */
576 struct adiv5_dap *dap_init(void)
577 {
578 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
579 int i;
580 /* Set up with safe defaults */
581 for (i = 0; i <= 255; i++) {
582 dap->ap[i].dap = dap;
583 dap->ap[i].ap_num = i;
584 /* memaccess_tck max is 255 */
585 dap->ap[i].memaccess_tck = 255;
586 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
587 dap->ap[i].tar_autoincr_block = (1<<10);
588 }
589 INIT_LIST_HEAD(&dap->cmd_journal);
590 return dap;
591 }
592
593 /**
594 * Initialize a DAP. This sets up the power domains, prepares the DP
595 * for further use and activates overrun checking.
596 *
597 * @param dap The DAP being initialized.
598 */
599 int dap_dp_init(struct adiv5_dap *dap)
600 {
601 int retval;
602
603 LOG_DEBUG(" ");
604 /* JTAG-DP or SWJ-DP, in JTAG mode
605 * ... for SWD mode this is patched as part
606 * of link switchover
607 * FIXME: This should already be setup by the respective transport specific DAP creation.
608 */
609 if (!dap->ops)
610 dap->ops = &jtag_dp_ops;
611
612 dap->select = DP_SELECT_INVALID;
613 dap->last_read = NULL;
614
615 for (size_t i = 0; i < 10; i++) {
616 /* DP initialization */
617
618 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
619 if (retval != ERROR_OK)
620 continue;
621
622 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
623 if (retval != ERROR_OK)
624 continue;
625
626 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
627 if (retval != ERROR_OK)
628 continue;
629
630 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
631 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
632 if (retval != ERROR_OK)
633 continue;
634
635 /* Check that we have debug power domains activated */
636 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
637 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
638 CDBGPWRUPACK, CDBGPWRUPACK,
639 DAP_POWER_DOMAIN_TIMEOUT);
640 if (retval != ERROR_OK)
641 continue;
642
643 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
644 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
645 CSYSPWRUPACK, CSYSPWRUPACK,
646 DAP_POWER_DOMAIN_TIMEOUT);
647 if (retval != ERROR_OK)
648 continue;
649
650 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
651 if (retval != ERROR_OK)
652 continue;
653
654 /* With debug power on we can activate OVERRUN checking */
655 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
656 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
657 if (retval != ERROR_OK)
658 continue;
659 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
660 if (retval != ERROR_OK)
661 continue;
662
663 retval = dap_run(dap);
664 if (retval != ERROR_OK)
665 continue;
666
667 break;
668 }
669
670 return retval;
671 }
672
673 /**
674 * Initialize a DAP. This sets up the power domains, prepares the DP
675 * for further use, and arranges to use AP #0 for all AP operations
676 * until dap_ap-select() changes that policy.
677 *
678 * @param ap The MEM-AP being initialized.
679 */
680 int mem_ap_init(struct adiv5_ap *ap)
681 {
682 /* check that we support packed transfers */
683 uint32_t csw, cfg;
684 int retval;
685 struct adiv5_dap *dap = ap->dap;
686
687 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
688 if (retval != ERROR_OK)
689 return retval;
690
691 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
692 if (retval != ERROR_OK)
693 return retval;
694
695 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
696 if (retval != ERROR_OK)
697 return retval;
698
699 retval = dap_run(dap);
700 if (retval != ERROR_OK)
701 return retval;
702
703 if (csw & CSW_ADDRINC_PACKED)
704 ap->packed_transfers = true;
705 else
706 ap->packed_transfers = false;
707
708 /* Packed transfers on TI BE-32 processors do not work correctly in
709 * many cases. */
710 if (dap->ti_be_32_quirks)
711 ap->packed_transfers = false;
712
713 LOG_DEBUG("MEM_AP Packed Transfers: %s",
714 ap->packed_transfers ? "enabled" : "disabled");
715
716 /* The ARM ADI spec leaves implementation-defined whether unaligned
717 * memory accesses work, only work partially, or cause a sticky error.
718 * On TI BE-32 processors, reads seem to return garbage in some bytes
719 * and unaligned writes seem to cause a sticky error.
720 * TODO: it would be nice to have a way to detect whether unaligned
721 * operations are supported on other processors. */
722 ap->unaligned_access_bad = dap->ti_be_32_quirks;
723
724 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
725 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
726
727 return ERROR_OK;
728 }
729
730 /* CID interpretation -- see ARM IHI 0029B section 3
731 * and ARM IHI 0031A table 13-3.
732 */
733 static const char *class_description[16] = {
734 "Reserved", "ROM table", "Reserved", "Reserved",
735 "Reserved", "Reserved", "Reserved", "Reserved",
736 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
737 "Reserved", "OptimoDE DESS",
738 "Generic IP component", "PrimeCell or System component"
739 };
740
741 static bool is_dap_cid_ok(uint32_t cid)
742 {
743 return (cid & 0xffff0fff) == 0xb105000d;
744 }
745
746 /*
747 * This function checks the ID for each access port to find the requested Access Port type
748 */
749 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
750 {
751 int ap_num;
752
753 /* Maximum AP number is 255 since the SELECT register is 8 bits */
754 for (ap_num = 0; ap_num <= 255; ap_num++) {
755
756 /* read the IDR register of the Access Port */
757 uint32_t id_val = 0;
758
759 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
760 if (retval != ERROR_OK)
761 return retval;
762
763 retval = dap_run(dap);
764
765 /* IDR bits:
766 * 31-28 : Revision
767 * 27-24 : JEDEC bank (0x4 for ARM)
768 * 23-17 : JEDEC code (0x3B for ARM)
769 * 16-13 : Class (0b1000=Mem-AP)
770 * 12-8 : Reserved
771 * 7-4 : AP Variant (non-zero for JTAG-AP)
772 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
773 */
774
775 /* Reading register for a non-existant AP should not cause an error,
776 * but just to be sure, try to continue searching if an error does happen.
777 */
778 if ((retval == ERROR_OK) && /* Register read success */
779 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
780 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
781
782 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
783 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
784 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
785 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
786 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
787 ap_num, id_val);
788
789 *ap_out = &dap->ap[ap_num];
790 return ERROR_OK;
791 }
792 }
793
794 LOG_DEBUG("No %s found",
795 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
796 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
797 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
798 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
799 return ERROR_FAIL;
800 }
801
802 int dap_get_debugbase(struct adiv5_ap *ap,
803 uint32_t *dbgbase, uint32_t *apid)
804 {
805 struct adiv5_dap *dap = ap->dap;
806 int retval;
807
808 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
809 if (retval != ERROR_OK)
810 return retval;
811 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
812 if (retval != ERROR_OK)
813 return retval;
814 retval = dap_run(dap);
815 if (retval != ERROR_OK)
816 return retval;
817
818 return ERROR_OK;
819 }
820
821 int dap_lookup_cs_component(struct adiv5_ap *ap,
822 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
823 {
824 uint32_t romentry, entry_offset = 0, component_base, devtype;
825 int retval;
826
827 *addr = 0;
828
829 do {
830 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
831 entry_offset, &romentry);
832 if (retval != ERROR_OK)
833 return retval;
834
835 component_base = (dbgbase & 0xFFFFF000)
836 + (romentry & 0xFFFFF000);
837
838 if (romentry & 0x1) {
839 uint32_t c_cid1;
840 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
841 if (retval != ERROR_OK) {
842 LOG_ERROR("Can't read component with base address 0x%" PRIx32
843 ", the corresponding core might be turned off", component_base);
844 return retval;
845 }
846 if (((c_cid1 >> 4) & 0x0f) == 1) {
847 retval = dap_lookup_cs_component(ap, component_base,
848 type, addr, idx);
849 if (retval == ERROR_OK)
850 break;
851 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
852 return retval;
853 }
854
855 retval = mem_ap_read_atomic_u32(ap,
856 (component_base & 0xfffff000) | 0xfcc,
857 &devtype);
858 if (retval != ERROR_OK)
859 return retval;
860 if ((devtype & 0xff) == type) {
861 if (!*idx) {
862 *addr = component_base;
863 break;
864 } else
865 (*idx)--;
866 }
867 }
868 entry_offset += 4;
869 } while (romentry > 0);
870
871 if (!*addr)
872 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
873
874 return ERROR_OK;
875 }
876
877 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
878 {
879 assert((component_base & 0xFFF) == 0);
880 assert(ap != NULL && cid != NULL && pid != NULL);
881
882 uint32_t cid0, cid1, cid2, cid3;
883 uint32_t pid0, pid1, pid2, pid3, pid4;
884 int retval;
885
886 /* IDs are in last 4K section */
887 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
888 if (retval != ERROR_OK)
889 return retval;
890 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
891 if (retval != ERROR_OK)
892 return retval;
893 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
894 if (retval != ERROR_OK)
895 return retval;
896 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
897 if (retval != ERROR_OK)
898 return retval;
899 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
900 if (retval != ERROR_OK)
901 return retval;
902 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
903 if (retval != ERROR_OK)
904 return retval;
905 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
906 if (retval != ERROR_OK)
907 return retval;
908 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
909 if (retval != ERROR_OK)
910 return retval;
911 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
912 if (retval != ERROR_OK)
913 return retval;
914
915 retval = dap_run(ap->dap);
916 if (retval != ERROR_OK)
917 return retval;
918
919 *cid = (cid3 & 0xff) << 24
920 | (cid2 & 0xff) << 16
921 | (cid1 & 0xff) << 8
922 | (cid0 & 0xff);
923 *pid = (uint64_t)(pid4 & 0xff) << 32
924 | (pid3 & 0xff) << 24
925 | (pid2 & 0xff) << 16
926 | (pid1 & 0xff) << 8
927 | (pid0 & 0xff);
928
929 return ERROR_OK;
930 }
931
932 /* The designer identity code is encoded as:
933 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
934 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
935 * a legacy ASCII Identity Code.
936 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
937 * JEP106 is a standard available from jedec.org
938 */
939
940 /* Part number interpretations are from Cortex
941 * core specs, the CoreSight components TRM
942 * (ARM DDI 0314H), CoreSight System Design
943 * Guide (ARM DGI 0012D) and ETM specs; also
944 * from chip observation (e.g. TI SDTI).
945 */
946
947 /* The legacy code only used the part number field to identify CoreSight peripherals.
948 * This meant that the same part number from two different manufacturers looked the same.
949 * It is desirable for all future additions to identify with both part number and JEP106.
950 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
951 */
952
953 #define ANY_ID 0x1000
954
955 #define ARM_ID 0x4BB
956
957 static const struct {
958 uint16_t designer_id;
959 uint16_t part_num;
960 const char *type;
961 const char *full;
962 } dap_partnums[] = {
963 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
964 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
965 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
966 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
967 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
968 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
969 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
970 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
971 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
972 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
973 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
974 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
975 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
976 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
977 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
978 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
979 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
980 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
981 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
982 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
983 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
984 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
985 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
986 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
987 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
988 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
989 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
990 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
991 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
992 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
993 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
994 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
995 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
996 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
997 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
998 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
999 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1000 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1001 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1002 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1003 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1004 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1005 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1006 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1007 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1008 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1009 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1010 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1011 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1012 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1013 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1014 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1015 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1016 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1017 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1018 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1019 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1020 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1021 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1022 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1023 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1024 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1025 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1026 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1027 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1028 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1029 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1030 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1031 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1032 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1033 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1034 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1035 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1036 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1037 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1038 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1039 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1040 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1041 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1042 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1043 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1044 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1045 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1046 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1047 /* legacy comment: 0x113: what? */
1048 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1049 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1050 };
1051
1052 static int dap_rom_display(struct command_context *cmd_ctx,
1053 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1054 {
1055 int retval;
1056 uint64_t pid;
1057 uint32_t cid;
1058 char tabs[7] = "";
1059
1060 if (depth > 16) {
1061 command_print(cmd_ctx, "\tTables too deep");
1062 return ERROR_FAIL;
1063 }
1064
1065 if (depth)
1066 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1067
1068 uint32_t base_addr = dbgbase & 0xFFFFF000;
1069 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1070
1071 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1072 if (retval != ERROR_OK) {
1073 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1074 return ERROR_OK; /* Don't abort recursion */
1075 }
1076
1077 if (!is_dap_cid_ok(cid)) {
1078 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1079 return ERROR_OK; /* Don't abort recursion */
1080 }
1081
1082 /* component may take multiple 4K pages */
1083 uint32_t size = (pid >> 36) & 0xf;
1084 if (size > 0)
1085 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1086
1087 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1088
1089 uint8_t class = (cid >> 12) & 0xf;
1090 uint16_t part_num = pid & 0xfff;
1091 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1092
1093 if (designer_id & 0x80) {
1094 /* JEP106 code */
1095 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1096 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1097 } else {
1098 /* Legacy ASCII ID, clear invalid bits */
1099 designer_id &= 0x7f;
1100 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1101 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1102 }
1103
1104 /* default values to be overwritten upon finding a match */
1105 const char *type = "Unrecognized";
1106 const char *full = "";
1107
1108 /* search dap_partnums[] array for a match */
1109 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1110
1111 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1112 continue;
1113
1114 if (dap_partnums[entry].part_num != part_num)
1115 continue;
1116
1117 type = dap_partnums[entry].type;
1118 full = dap_partnums[entry].full;
1119 break;
1120 }
1121
1122 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1123 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1124
1125 if (class == 1) { /* ROM Table */
1126 uint32_t memtype;
1127 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1128 if (retval != ERROR_OK)
1129 return retval;
1130
1131 if (memtype & 0x01)
1132 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1133 else
1134 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1135
1136 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1137 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1138 uint32_t romentry;
1139 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1140 if (retval != ERROR_OK)
1141 return retval;
1142 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1143 tabs, entry_offset, romentry);
1144 if (romentry & 0x01) {
1145 /* Recurse */
1146 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1147 if (retval != ERROR_OK)
1148 return retval;
1149 } else if (romentry != 0) {
1150 command_print(cmd_ctx, "\t\tComponent not present");
1151 } else {
1152 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1153 break;
1154 }
1155 }
1156 } else if (class == 9) { /* CoreSight component */
1157 const char *major = "Reserved", *subtype = "Reserved";
1158
1159 uint32_t devtype;
1160 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1161 if (retval != ERROR_OK)
1162 return retval;
1163 unsigned minor = (devtype >> 4) & 0x0f;
1164 switch (devtype & 0x0f) {
1165 case 0:
1166 major = "Miscellaneous";
1167 switch (minor) {
1168 case 0:
1169 subtype = "other";
1170 break;
1171 case 4:
1172 subtype = "Validation component";
1173 break;
1174 }
1175 break;
1176 case 1:
1177 major = "Trace Sink";
1178 switch (minor) {
1179 case 0:
1180 subtype = "other";
1181 break;
1182 case 1:
1183 subtype = "Port";
1184 break;
1185 case 2:
1186 subtype = "Buffer";
1187 break;
1188 case 3:
1189 subtype = "Router";
1190 break;
1191 }
1192 break;
1193 case 2:
1194 major = "Trace Link";
1195 switch (minor) {
1196 case 0:
1197 subtype = "other";
1198 break;
1199 case 1:
1200 subtype = "Funnel, router";
1201 break;
1202 case 2:
1203 subtype = "Filter";
1204 break;
1205 case 3:
1206 subtype = "FIFO, buffer";
1207 break;
1208 }
1209 break;
1210 case 3:
1211 major = "Trace Source";
1212 switch (minor) {
1213 case 0:
1214 subtype = "other";
1215 break;
1216 case 1:
1217 subtype = "Processor";
1218 break;
1219 case 2:
1220 subtype = "DSP";
1221 break;
1222 case 3:
1223 subtype = "Engine/Coprocessor";
1224 break;
1225 case 4:
1226 subtype = "Bus";
1227 break;
1228 case 6:
1229 subtype = "Software";
1230 break;
1231 }
1232 break;
1233 case 4:
1234 major = "Debug Control";
1235 switch (minor) {
1236 case 0:
1237 subtype = "other";
1238 break;
1239 case 1:
1240 subtype = "Trigger Matrix";
1241 break;
1242 case 2:
1243 subtype = "Debug Auth";
1244 break;
1245 case 3:
1246 subtype = "Power Requestor";
1247 break;
1248 }
1249 break;
1250 case 5:
1251 major = "Debug Logic";
1252 switch (minor) {
1253 case 0:
1254 subtype = "other";
1255 break;
1256 case 1:
1257 subtype = "Processor";
1258 break;
1259 case 2:
1260 subtype = "DSP";
1261 break;
1262 case 3:
1263 subtype = "Engine/Coprocessor";
1264 break;
1265 case 4:
1266 subtype = "Bus";
1267 break;
1268 case 5:
1269 subtype = "Memory";
1270 break;
1271 }
1272 break;
1273 case 6:
1274 major = "Perfomance Monitor";
1275 switch (minor) {
1276 case 0:
1277 subtype = "other";
1278 break;
1279 case 1:
1280 subtype = "Processor";
1281 break;
1282 case 2:
1283 subtype = "DSP";
1284 break;
1285 case 3:
1286 subtype = "Engine/Coprocessor";
1287 break;
1288 case 4:
1289 subtype = "Bus";
1290 break;
1291 case 5:
1292 subtype = "Memory";
1293 break;
1294 }
1295 break;
1296 }
1297 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1298 (uint8_t)(devtype & 0xff),
1299 major, subtype);
1300 /* REVISIT also show 0xfc8 DevId */
1301 }
1302
1303 return ERROR_OK;
1304 }
1305
1306 static int dap_info_command(struct command_context *cmd_ctx,
1307 struct adiv5_ap *ap)
1308 {
1309 int retval;
1310 uint32_t dbgbase, apid;
1311 uint8_t mem_ap;
1312
1313 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1314 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1315 if (retval != ERROR_OK)
1316 return retval;
1317
1318 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1319 if (apid == 0) {
1320 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1321 return ERROR_FAIL;
1322 }
1323
1324 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1325 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1326 command_print(cmd_ctx, "\tType is JTAG-AP");
1327 break;
1328 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1329 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1330 break;
1331 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1332 command_print(cmd_ctx, "\tType is MEM-AP APB");
1333 break;
1334 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1335 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1336 break;
1337 default:
1338 command_print(cmd_ctx, "\tUnknown AP type");
1339 break;
1340 }
1341
1342 /* NOTE: a MEM-AP may have a single CoreSight component that's
1343 * not a ROM table ... or have no such components at all.
1344 */
1345 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1346 if (mem_ap) {
1347 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1348
1349 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1350 command_print(cmd_ctx, "\tNo ROM table present");
1351 } else {
1352 if (dbgbase & 0x01)
1353 command_print(cmd_ctx, "\tValid ROM table present");
1354 else
1355 command_print(cmd_ctx, "\tROM table in legacy format");
1356
1357 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1358 }
1359 }
1360
1361 return ERROR_OK;
1362 }
1363
1364 COMMAND_HANDLER(handle_dap_info_command)
1365 {
1366 struct target *target = get_current_target(CMD_CTX);
1367 struct arm *arm = target_to_arm(target);
1368 struct adiv5_dap *dap = arm->dap;
1369 uint32_t apsel;
1370
1371 switch (CMD_ARGC) {
1372 case 0:
1373 apsel = dap->apsel;
1374 break;
1375 case 1:
1376 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1377 if (apsel >= 256)
1378 return ERROR_COMMAND_SYNTAX_ERROR;
1379 break;
1380 default:
1381 return ERROR_COMMAND_SYNTAX_ERROR;
1382 }
1383
1384 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1385 }
1386
1387 COMMAND_HANDLER(dap_baseaddr_command)
1388 {
1389 struct target *target = get_current_target(CMD_CTX);
1390 struct arm *arm = target_to_arm(target);
1391 struct adiv5_dap *dap = arm->dap;
1392
1393 uint32_t apsel, baseaddr;
1394 int retval;
1395
1396 switch (CMD_ARGC) {
1397 case 0:
1398 apsel = dap->apsel;
1399 break;
1400 case 1:
1401 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1402 /* AP address is in bits 31:24 of DP_SELECT */
1403 if (apsel >= 256)
1404 return ERROR_COMMAND_SYNTAX_ERROR;
1405 break;
1406 default:
1407 return ERROR_COMMAND_SYNTAX_ERROR;
1408 }
1409
1410 /* NOTE: assumes we're talking to a MEM-AP, which
1411 * has a base address. There are other kinds of AP,
1412 * though they're not common for now. This should
1413 * use the ID register to verify it's a MEM-AP.
1414 */
1415 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1416 if (retval != ERROR_OK)
1417 return retval;
1418 retval = dap_run(dap);
1419 if (retval != ERROR_OK)
1420 return retval;
1421
1422 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1423
1424 return retval;
1425 }
1426
1427 COMMAND_HANDLER(dap_memaccess_command)
1428 {
1429 struct target *target = get_current_target(CMD_CTX);
1430 struct arm *arm = target_to_arm(target);
1431 struct adiv5_dap *dap = arm->dap;
1432
1433 uint32_t memaccess_tck;
1434
1435 switch (CMD_ARGC) {
1436 case 0:
1437 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1438 break;
1439 case 1:
1440 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1441 break;
1442 default:
1443 return ERROR_COMMAND_SYNTAX_ERROR;
1444 }
1445 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1446
1447 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1448 dap->ap[dap->apsel].memaccess_tck);
1449
1450 return ERROR_OK;
1451 }
1452
1453 COMMAND_HANDLER(dap_apsel_command)
1454 {
1455 struct target *target = get_current_target(CMD_CTX);
1456 struct arm *arm = target_to_arm(target);
1457 struct adiv5_dap *dap = arm->dap;
1458
1459 uint32_t apsel, apid;
1460 int retval;
1461
1462 switch (CMD_ARGC) {
1463 case 0:
1464 apsel = dap->apsel;
1465 break;
1466 case 1:
1467 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1468 /* AP address is in bits 31:24 of DP_SELECT */
1469 if (apsel >= 256)
1470 return ERROR_COMMAND_SYNTAX_ERROR;
1471 break;
1472 default:
1473 return ERROR_COMMAND_SYNTAX_ERROR;
1474 }
1475
1476 dap->apsel = apsel;
1477
1478 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1479 if (retval != ERROR_OK)
1480 return retval;
1481 retval = dap_run(dap);
1482 if (retval != ERROR_OK)
1483 return retval;
1484
1485 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1486 apsel, apid);
1487
1488 return retval;
1489 }
1490
1491 COMMAND_HANDLER(dap_apcsw_command)
1492 {
1493 struct target *target = get_current_target(CMD_CTX);
1494 struct arm *arm = target_to_arm(target);
1495 struct adiv5_dap *dap = arm->dap;
1496
1497 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1498
1499 switch (CMD_ARGC) {
1500 case 0:
1501 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1502 (dap->apsel), apcsw);
1503 break;
1504 case 1:
1505 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1506 /* AP address is in bits 31:24 of DP_SELECT */
1507 if (sprot > 1)
1508 return ERROR_COMMAND_SYNTAX_ERROR;
1509 if (sprot)
1510 apcsw |= CSW_SPROT;
1511 else
1512 apcsw &= ~CSW_SPROT;
1513 break;
1514 default:
1515 return ERROR_COMMAND_SYNTAX_ERROR;
1516 }
1517 dap->ap[dap->apsel].csw_default = apcsw;
1518
1519 return 0;
1520 }
1521
1522
1523
1524 COMMAND_HANDLER(dap_apid_command)
1525 {
1526 struct target *target = get_current_target(CMD_CTX);
1527 struct arm *arm = target_to_arm(target);
1528 struct adiv5_dap *dap = arm->dap;
1529
1530 uint32_t apsel, apid;
1531 int retval;
1532
1533 switch (CMD_ARGC) {
1534 case 0:
1535 apsel = dap->apsel;
1536 break;
1537 case 1:
1538 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1539 /* AP address is in bits 31:24 of DP_SELECT */
1540 if (apsel >= 256)
1541 return ERROR_COMMAND_SYNTAX_ERROR;
1542 break;
1543 default:
1544 return ERROR_COMMAND_SYNTAX_ERROR;
1545 }
1546
1547 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1548 if (retval != ERROR_OK)
1549 return retval;
1550 retval = dap_run(dap);
1551 if (retval != ERROR_OK)
1552 return retval;
1553
1554 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1555
1556 return retval;
1557 }
1558
1559 COMMAND_HANDLER(dap_apreg_command)
1560 {
1561 struct target *target = get_current_target(CMD_CTX);
1562 struct arm *arm = target_to_arm(target);
1563 struct adiv5_dap *dap = arm->dap;
1564
1565 uint32_t apsel, reg, value;
1566 int retval;
1567
1568 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1569 return ERROR_COMMAND_SYNTAX_ERROR;
1570
1571 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1572 /* AP address is in bits 31:24 of DP_SELECT */
1573 if (apsel >= 256)
1574 return ERROR_COMMAND_SYNTAX_ERROR;
1575
1576 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1577 if (reg >= 256 || (reg & 3))
1578 return ERROR_COMMAND_SYNTAX_ERROR;
1579
1580 if (CMD_ARGC == 3) {
1581 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1582 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1583 } else {
1584 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1585 }
1586 if (retval == ERROR_OK)
1587 retval = dap_run(dap);
1588
1589 if (retval != ERROR_OK)
1590 return retval;
1591
1592 if (CMD_ARGC == 2)
1593 command_print(CMD_CTX, "0x%08" PRIx32, value);
1594
1595 return retval;
1596 }
1597
1598 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1599 {
1600 struct target *target = get_current_target(CMD_CTX);
1601 struct arm *arm = target_to_arm(target);
1602 struct adiv5_dap *dap = arm->dap;
1603
1604 uint32_t enable = dap->ti_be_32_quirks;
1605
1606 switch (CMD_ARGC) {
1607 case 0:
1608 break;
1609 case 1:
1610 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1611 if (enable > 1)
1612 return ERROR_COMMAND_SYNTAX_ERROR;
1613 break;
1614 default:
1615 return ERROR_COMMAND_SYNTAX_ERROR;
1616 }
1617 dap->ti_be_32_quirks = enable;
1618 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1619 enable ? "enabled" : "disabled");
1620
1621 return 0;
1622 }
1623
1624 static const struct command_registration dap_commands[] = {
1625 {
1626 .name = "info",
1627 .handler = handle_dap_info_command,
1628 .mode = COMMAND_EXEC,
1629 .help = "display ROM table for MEM-AP "
1630 "(default currently selected AP)",
1631 .usage = "[ap_num]",
1632 },
1633 {
1634 .name = "apsel",
1635 .handler = dap_apsel_command,
1636 .mode = COMMAND_EXEC,
1637 .help = "Set the currently selected AP (default 0) "
1638 "and display the result",
1639 .usage = "[ap_num]",
1640 },
1641 {
1642 .name = "apcsw",
1643 .handler = dap_apcsw_command,
1644 .mode = COMMAND_EXEC,
1645 .help = "Set csw access bit ",
1646 .usage = "[sprot]",
1647 },
1648
1649 {
1650 .name = "apid",
1651 .handler = dap_apid_command,
1652 .mode = COMMAND_EXEC,
1653 .help = "return ID register from AP "
1654 "(default currently selected AP)",
1655 .usage = "[ap_num]",
1656 },
1657 {
1658 .name = "apreg",
1659 .handler = dap_apreg_command,
1660 .mode = COMMAND_EXEC,
1661 .help = "read/write a register from AP "
1662 "(reg is byte address of a word register, like 0 4 8...)",
1663 .usage = "ap_num reg [value]",
1664 },
1665 {
1666 .name = "baseaddr",
1667 .handler = dap_baseaddr_command,
1668 .mode = COMMAND_EXEC,
1669 .help = "return debug base address from MEM-AP "
1670 "(default currently selected AP)",
1671 .usage = "[ap_num]",
1672 },
1673 {
1674 .name = "memaccess",
1675 .handler = dap_memaccess_command,
1676 .mode = COMMAND_EXEC,
1677 .help = "set/get number of extra tck for MEM-AP memory "
1678 "bus access [0-255]",
1679 .usage = "[cycles]",
1680 },
1681 {
1682 .name = "ti_be_32_quirks",
1683 .handler = dap_ti_be_32_quirks_command,
1684 .mode = COMMAND_CONFIG,
1685 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1686 .usage = "[enable]",
1687 },
1688 COMMAND_REGISTRATION_DONE
1689 };
1690
1691 const struct command_registration dap_command_handlers[] = {
1692 {
1693 .name = "dap",
1694 .mode = COMMAND_EXEC,
1695 .help = "DAP command group",
1696 .usage = "",
1697 .chain = dap_commands,
1698 },
1699 COMMAND_REGISTRATION_DONE
1700 };
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