1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
32 #include <helper/list.h>
34 #include "helper/bits.h"
36 /* JEP106 ID for ARM */
39 /* three-bit ACK values for SWD access (sent LSB first) */
40 #define SWD_ACK_OK 0x1
41 #define SWD_ACK_WAIT 0x2
42 #define SWD_ACK_FAULT 0x4
47 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
49 /* A[3:0] for DP registers; A[1:0] are always zero.
50 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
51 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
52 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
54 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
55 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
56 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
57 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
58 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
59 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
60 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
61 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
62 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
63 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
64 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
66 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
68 /* Fields of DP_DPIDR register */
69 #define DP_DPIDR_VERSION_SHIFT 12
70 #define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
72 /* Fields of the DP's AP ABORT register */
73 #define DAPABORT (1UL << 0)
74 #define STKCMPCLR (1UL << 1) /* SWD-only */
75 #define STKERRCLR (1UL << 2) /* SWD-only */
76 #define WDERRCLR (1UL << 3) /* SWD-only */
77 #define ORUNERRCLR (1UL << 4) /* SWD-only */
79 /* Fields of the DP's CTRL/STAT register */
80 #define CORUNDETECT (1UL << 0)
81 #define SSTICKYORUN (1UL << 1)
82 /* 3:2 - transaction mode (e.g. pushed compare) */
83 #define SSTICKYCMP (1UL << 4)
84 #define SSTICKYERR (1UL << 5)
85 #define READOK (1UL << 6) /* SWD-only */
86 #define WDATAERR (1UL << 7) /* SWD-only */
87 /* 11:8 - mask lanes for pushed compare or verify ops */
88 /* 21:12 - transaction counter */
89 #define CDBGRSTREQ (1UL << 26)
90 #define CDBGRSTACK (1UL << 27)
91 #define CDBGPWRUPREQ (1UL << 28)
92 #define CDBGPWRUPACK (1UL << 29)
93 #define CSYSPWRUPREQ (1UL << 30)
94 #define CSYSPWRUPACK (1UL << 31)
96 #define DP_DLPIDR_PROTVSN 1u
98 #define DP_SELECT_APSEL 0xFF000000
99 #define DP_SELECT_APBANK 0x000000F0
100 #define DP_SELECT_DPBANK 0x0000000F
101 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
103 #define DP_APSEL_MAX (255)
104 #define DP_APSEL_INVALID (-1)
106 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
107 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
108 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
109 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
112 /* MEM-AP register addresses */
113 #define MEM_AP_REG_CSW 0x00
114 #define MEM_AP_REG_TAR 0x04
115 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
116 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
117 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
118 #define MEM_AP_REG_BD1 0x14
119 #define MEM_AP_REG_BD2 0x18
120 #define MEM_AP_REG_BD3 0x1C
121 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
122 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
123 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
124 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
125 /* Generic AP register address */
126 #define AP_REG_IDR 0xFC /* RO: Identification Register */
128 /* Fields of the MEM-AP's CSW register */
129 #define CSW_SIZE_MASK 7
133 #define CSW_ADDRINC_MASK (3UL << 4)
134 #define CSW_ADDRINC_OFF 0UL
135 #define CSW_ADDRINC_SINGLE (1UL << 4)
136 #define CSW_ADDRINC_PACKED (2UL << 4)
137 #define CSW_DEVICE_EN (1UL << 6)
138 #define CSW_TRIN_PROG (1UL << 7)
140 /* All fields in bits 12 and above are implementation-defined
141 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
142 * Some bits are shared between buses
144 #define CSW_SPIDEN (1UL << 23)
145 #define CSW_DBGSWENABLE (1UL << 31)
147 /* AHB: Privileged */
148 #define CSW_AHB_HPROT1 (1UL << 25)
149 /* AHB: set HMASTER signals to AHB-AP ID */
150 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
151 /* AHB5: non-secure access via HNONSEC
152 * AHB3: SBO, UNPREDICTABLE if zero */
153 #define CSW_AHB_SPROT (1UL << 30)
154 /* AHB: initial value of csw_default */
155 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
157 /* AXI: Privileged */
158 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
159 /* AXI: Non-secure */
160 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
161 /* AXI: initial value of csw_default */
162 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
164 /* APB: initial value of csw_default */
165 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
167 /* Fields of the MEM-AP's CFG register */
168 #define MEM_AP_REG_CFG_BE BIT(0)
169 #define MEM_AP_REG_CFG_LA BIT(1)
170 #define MEM_AP_REG_CFG_LD BIT(2)
171 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
173 /* Fields of the MEM-AP's IDR register */
174 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
175 #define AP_REG_IDR_REVISION_SHIFT (28)
176 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
177 #define AP_REG_IDR_DESIGNER_SHIFT (17)
178 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
179 #define AP_REG_IDR_CLASS_SHIFT (13)
180 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
181 #define AP_REG_IDR_VARIANT_SHIFT (4)
182 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
183 #define AP_REG_IDR_TYPE_SHIFT (0)
185 #define AP_REG_IDR_CLASS_NONE (0x0)
186 #define AP_REG_IDR_CLASS_COM (0x1)
187 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
189 #define AP_REG_IDR_VALUE(d, c, t) (\
190 (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
191 (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
192 (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
195 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
197 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
198 enum swd_special_seq
{
209 * This represents an ARM Debug Interface (v5) Access Port (AP).
210 * Most common is a MEM-AP, for memory access.
214 * DAP this AP belongs to.
216 struct adiv5_dap
*dap
;
224 * Default value for (MEM-AP) AP_REG_CSW register.
226 uint32_t csw_default
;
229 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
230 * configure an access mode, such as autoincrementing AP_REG_TAR during
231 * word access. "-1" indicates no cached value.
236 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
237 * configure the address being read or written
238 * "-1" indicates no cached value.
240 target_addr_t tar_value
;
243 * Configures how many extra tck clocks are added after starting a
244 * MEM-AP access before we try to read its status (and/or result).
246 uint32_t memaccess_tck
;
248 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
249 uint32_t tar_autoincr_block
;
251 /* true if packed transfers are supported by the MEM-AP */
252 bool packed_transfers
;
254 /* true if unaligned memory access is not supported by the MEM-AP */
255 bool unaligned_access_bad
;
257 /* true if tar_value is in sync with TAR register */
260 /* MEM AP configuration register indicating LPAE support */
266 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
267 * A DAP has two types of component: one Debug Port (DP), which is a
268 * transport agent; and at least one Access Port (AP), controlling
271 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
272 * Accordingly, this interface is responsible for hiding the transport
273 * differences so upper layer code can largely ignore them.
275 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
276 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
277 * a choice made at board design time (by only using the SWD pins), or
278 * as part of setting up a debug session (if all the dual-role JTAG/SWD
279 * signals are available).
282 const struct dap_ops
*ops
;
284 /* dap transaction list for WAIT support */
285 struct list_head cmd_journal
;
287 /* pool for dap_cmd objects */
288 struct list_head cmd_pool
;
290 /* number of dap_cmd objects in the pool */
291 size_t cmd_pool_size
;
293 struct jtag_tap
*tap
;
295 uint32_t dp_ctrl_stat
;
297 struct adiv5_ap ap
[DP_APSEL_MAX
+ 1];
299 /* The current manually selected AP by the "dap apsel" command */
303 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
304 * indicates no cached value and forces rewrite of the register.
308 /* information about current pending SWjDP-AHBAP transaction */
312 * Holds the pointer to the destination word for the last queued read,
313 * for use with posted AP read sequence optimization.
317 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
318 * despite lack of support in the ARMv7 architecture. Memory access through
319 * the AHB-AP has strange byte ordering these processors, and we need to
320 * swizzle appropriately. */
321 bool ti_be_32_quirks
;
324 * STLINK adapter need to know if last AP operation was read or write, and
325 * in case of write has to flush it with a dummy read from DP_RDBUFF
327 bool stlink_flush_ap_write
;
330 * Signals that an attempt to reestablish communication afresh
331 * should be performed before the next access.
335 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
336 * do not set this bit until later in the bringup sequence */
337 bool ignore_syspwrupack
;
339 /** Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID */
340 uint32_t multidrop_targetsel
;
341 /** TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured */
342 bool multidrop_dp_id_valid
;
343 /** TINSTANCE field of multidrop_targetsel has been configured */
344 bool multidrop_instance_id_valid
;
348 * Transport-neutral representation of queued DAP transactions, supporting
349 * both JTAG and SWD transports. All submitted transactions are logically
350 * queued, until the queue is executed by run(). Some implementations might
351 * execute transactions as soon as they're submitted, but no status is made
352 * available until run().
355 /** connect operation for SWD */
356 int (*connect
)(struct adiv5_dap
*dap
);
358 /** send a sequence to the DAP */
359 int (*send_sequence
)(struct adiv5_dap
*dap
, enum swd_special_seq seq
);
361 /** DP register read. */
362 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
364 /** DP register write. */
365 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
368 /** AP register read. */
369 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
371 /** AP register write. */
372 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
375 /** AP operation abort. */
376 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
378 /** Executes all queued DAP operations. */
379 int (*run
)(struct adiv5_dap
*dap
);
381 /** Executes all queued DAP operations but doesn't check
382 * sticky error conditions */
383 int (*sync
)(struct adiv5_dap
*dap
);
385 /** Optional; called at OpenOCD exit */
386 void (*quit
)(struct adiv5_dap
*dap
);
393 AP_TYPE_JTAG_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_NONE
, 0), /* JTAG-AP */
394 AP_TYPE_COM_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_COM
, 0), /* COM-AP */
395 AP_TYPE_AHB3_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 1), /* AHB3 Memory-AP */
396 AP_TYPE_APB_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 2), /* APB2 or APB3 Memory-AP */
397 AP_TYPE_AXI_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 4), /* AXI3 or AXI4 Memory-AP */
398 AP_TYPE_AHB5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 5), /* AHB5 Memory-AP */
399 AP_TYPE_APB4_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 6), /* APB4 Memory-AP */
400 AP_TYPE_AXI5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 7), /* AXI5 Memory-AP */
401 AP_TYPE_AHB5H_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 8), /* AHB5 with enhanced HPROT Memory-AP */
404 /* Check the ap->cfg_reg Long Address field (bit 1)
406 * 0b0: The AP only supports physical addresses 32 bits or smaller
407 * 0b1: The AP supports physical addresses larger than 32 bits
409 * @param ap The AP used for reading.
411 * @return true for 64 bit, false for 32 bit
413 static inline bool is_64bit_ap(struct adiv5_ap
*ap
)
415 return (ap
->cfg_reg
& MEM_AP_REG_CFG_LA
) != 0;
419 * Send an adi-v5 sequence to the DAP.
421 * @param dap The DAP used for reading.
422 * @param seq The sequence to send.
424 * @return ERROR_OK for success, else a fault code.
426 static inline int dap_send_sequence(struct adiv5_dap
*dap
,
427 enum swd_special_seq seq
)
430 return dap
->ops
->send_sequence(dap
, seq
);
434 * Queue a DP register read.
435 * Note that not all DP registers are readable; also, that JTAG and SWD
436 * have slight differences in DP register support.
438 * @param dap The DAP used for reading.
439 * @param reg The two-bit number of the DP register being read.
440 * @param data Pointer saying where to store the register's value
441 * (in host endianness).
443 * @return ERROR_OK for success, else a fault code.
445 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
446 unsigned reg
, uint32_t *data
)
449 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
453 * Queue a DP register write.
454 * Note that not all DP registers are writable; also, that JTAG and SWD
455 * have slight differences in DP register support.
457 * @param dap The DAP used for writing.
458 * @param reg The two-bit number of the DP register being written.
459 * @param data Value being written (host endianness)
461 * @return ERROR_OK for success, else a fault code.
463 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
464 unsigned reg
, uint32_t data
)
467 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
471 * Queue an AP register read.
473 * @param ap The AP used for reading.
474 * @param reg The number of the AP register being read.
475 * @param data Pointer saying where to store the register's value
476 * (in host endianness).
478 * @return ERROR_OK for success, else a fault code.
480 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
481 unsigned reg
, uint32_t *data
)
483 assert(ap
->dap
->ops
);
484 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
488 * Queue an AP register write.
490 * @param ap The AP used for writing.
491 * @param reg The number of the AP register being written.
492 * @param data Value being written (host endianness)
494 * @return ERROR_OK for success, else a fault code.
496 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
497 unsigned reg
, uint32_t data
)
499 assert(ap
->dap
->ops
);
500 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
504 * Queue an AP abort operation. The current AP transaction is aborted,
505 * including any update of the transaction counter. The AP is left in
506 * an unknown state (so it must be re-initialized). For use only after
507 * the AP has reported WAIT status for an extended period.
509 * @param dap The DAP used for writing.
510 * @param ack Pointer to where transaction status will be stored.
512 * @return ERROR_OK for success, else a fault code.
514 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
517 return dap
->ops
->queue_ap_abort(dap
, ack
);
521 * Perform all queued DAP operations, and clear any errors posted in the
522 * CTRL_STAT register when they are done. Note that if more than one AP
523 * operation will be queued, one of the first operations in the queue
524 * should probably enable CORUNDETECT in the CTRL/STAT register.
526 * @param dap The DAP used.
528 * @return ERROR_OK for success, else a fault code.
530 static inline int dap_run(struct adiv5_dap
*dap
)
533 return dap
->ops
->run(dap
);
536 static inline int dap_sync(struct adiv5_dap
*dap
)
540 return dap
->ops
->sync(dap
);
544 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
549 retval
= dap_queue_dp_read(dap
, reg
, value
);
550 if (retval
!= ERROR_OK
)
556 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
557 uint32_t mask
, uint32_t value
, int timeout
)
560 assert((value
& mask
) == value
);
564 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
567 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
571 if ((regval
& mask
) == value
)
578 LOG_DEBUG("DAP: poll %x timeout", reg
);
585 /* Queued MEM-AP memory mapped single word transfers. */
586 int mem_ap_read_u32(struct adiv5_ap
*ap
,
587 target_addr_t address
, uint32_t *value
);
588 int mem_ap_write_u32(struct adiv5_ap
*ap
,
589 target_addr_t address
, uint32_t value
);
591 /* Synchronous MEM-AP memory mapped single word transfers. */
592 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
593 target_addr_t address
, uint32_t *value
);
594 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
595 target_addr_t address
, uint32_t value
);
597 /* Synchronous MEM-AP memory mapped bus block transfers. */
598 int mem_ap_read_buf(struct adiv5_ap
*ap
,
599 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
600 int mem_ap_write_buf(struct adiv5_ap
*ap
,
601 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
603 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
604 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
605 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
606 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
607 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
609 /* Initialisation of the debug system, power domains and registers */
610 int dap_dp_init(struct adiv5_dap
*dap
);
611 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
);
612 int mem_ap_init(struct adiv5_ap
*ap
);
614 /* Invalidate cached DP select and cached TAR and CSW of all APs */
615 void dap_invalidate_cache(struct adiv5_dap
*dap
);
617 /* Probe the AP for ROM Table location */
618 int dap_get_debugbase(struct adiv5_ap
*ap
,
619 target_addr_t
*dbgbase
, uint32_t *apid
);
621 /* Probe Access Ports to find a particular type */
622 int dap_find_ap(struct adiv5_dap
*dap
,
623 enum ap_type type_to_find
,
624 struct adiv5_ap
**ap_out
);
626 static inline struct adiv5_ap
*dap_ap(struct adiv5_dap
*dap
, uint8_t ap_num
)
628 return &dap
->ap
[ap_num
];
631 /** Check if SWD multidrop configuration is valid */
632 static inline bool dap_is_multidrop(struct adiv5_dap
*dap
)
634 return dap
->multidrop_dp_id_valid
&& dap
->multidrop_instance_id_valid
;
637 /* Lookup CoreSight component */
638 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
639 target_addr_t dbgbase
, uint8_t type
, target_addr_t
*addr
, int32_t *idx
);
643 /* Put debug link into SWD mode */
644 int dap_to_swd(struct adiv5_dap
*dap
);
646 /* Put debug link into JTAG mode */
647 int dap_to_jtag(struct adiv5_dap
*dap
);
649 extern const struct command_registration dap_instance_commands
[];
651 struct arm_dap_object
;
652 extern struct adiv5_dap
*dap_instance_by_jim_obj(Jim_Interp
*interp
, Jim_Obj
*o
);
653 extern struct adiv5_dap
*adiv5_get_dap(struct arm_dap_object
*obj
);
654 extern int dap_info_command(struct command_invocation
*cmd
,
655 struct adiv5_ap
*ap
);
656 extern int dap_register_commands(struct command_context
*cmd_ctx
);
657 extern const char *adiv5_dap_name(struct adiv5_dap
*self
);
658 extern const struct swd_driver
*adiv5_dap_swd_driver(struct adiv5_dap
*self
);
659 extern int dap_cleanup_all(void);
661 struct adiv5_private_config
{
663 struct adiv5_dap
*dap
;
666 extern int adiv5_verify_config(struct adiv5_private_config
*pc
);
667 extern int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
);
669 struct adiv5_mem_ap_spot
{
670 struct adiv5_dap
*dap
;
675 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
);
676 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
677 struct jim_getopt_info
*goi
);
679 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
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