1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
34 #include <helper/list.h>
37 /* three-bit ACK values for SWD access (sent LSB first) */
38 #define SWD_ACK_OK 0x1
39 #define SWD_ACK_WAIT 0x2
40 #define SWD_ACK_FAULT 0x4
45 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
47 /* A[3:0] for DP registers; A[1:0] are always zero.
48 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
49 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
50 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
52 #define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */
53 #define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */
54 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */
55 #define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */
56 #define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */
57 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */
58 #define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */
60 #define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
61 #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
63 /* Fields of the DP's AP ABORT register */
64 #define DAPABORT (1UL << 0)
65 #define STKCMPCLR (1UL << 1) /* SWD-only */
66 #define STKERRCLR (1UL << 2) /* SWD-only */
67 #define WDERRCLR (1UL << 3) /* SWD-only */
68 #define ORUNERRCLR (1UL << 4) /* SWD-only */
70 /* Fields of the DP's CTRL/STAT register */
71 #define CORUNDETECT (1UL << 0)
72 #define SSTICKYORUN (1UL << 1)
73 /* 3:2 - transaction mode (e.g. pushed compare) */
74 #define SSTICKYCMP (1UL << 4)
75 #define SSTICKYERR (1UL << 5)
76 #define READOK (1UL << 6) /* SWD-only */
77 #define WDATAERR (1UL << 7) /* SWD-only */
78 /* 11:8 - mask lanes for pushed compare or verify ops */
79 /* 21:12 - transaction counter */
80 #define CDBGRSTREQ (1UL << 26)
81 #define CDBGRSTACK (1UL << 27)
82 #define CDBGPWRUPREQ (1UL << 28)
83 #define CDBGPWRUPACK (1UL << 29)
84 #define CSYSPWRUPREQ (1UL << 30)
85 #define CSYSPWRUPACK (1UL << 31)
87 /* MEM-AP register addresses */
88 #define MEM_AP_REG_CSW 0x00
89 #define MEM_AP_REG_TAR 0x04
90 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
91 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
92 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
93 #define MEM_AP_REG_BD1 0x14
94 #define MEM_AP_REG_BD2 0x18
95 #define MEM_AP_REG_BD3 0x1C
96 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
97 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
98 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
99 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
100 /* Generic AP register address */
101 #define AP_REG_IDR 0xFC /* RO: Identification Register */
103 /* Fields of the MEM-AP's CSW register */
107 #define CSW_ADDRINC_MASK (3UL << 4)
108 #define CSW_ADDRINC_OFF 0UL
109 #define CSW_ADDRINC_SINGLE (1UL << 4)
110 #define CSW_ADDRINC_PACKED (2UL << 4)
111 #define CSW_DEVICE_EN (1UL << 6)
112 #define CSW_TRIN_PROG (1UL << 7)
113 #define CSW_SPIDEN (1UL << 23)
114 /* 30:24 - implementation-defined! */
115 #define CSW_HPROT (1UL << 25) /* ? */
116 #define CSW_MASTER_DEBUG (1UL << 29) /* ? */
117 #define CSW_SPROT (1UL << 30)
118 #define CSW_DBGSWENABLE (1UL << 31)
120 /* Fields of the MEM-AP's IDR register */
121 #define IDR_REV (0xFUL << 28)
122 #define IDR_JEP106 (0x7FFUL << 17)
123 #define IDR_CLASS (0xFUL << 13)
124 #define IDR_VARIANT (0xFUL << 4)
125 #define IDR_TYPE (0xFUL << 0)
127 #define IDR_JEP106_ARM 0x04760000
129 #define DP_SELECT_APSEL 0xFF000000
130 #define DP_SELECT_APBANK 0x000000F0
131 #define DP_SELECT_DPBANK 0x0000000F
132 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
135 * This represents an ARM Debug Interface (v5) Access Port (AP).
136 * Most common is a MEM-AP, for memory access.
140 * DAP this AP belongs to.
142 struct adiv5_dap
*dap
;
150 * Default value for (MEM-AP) AP_REG_CSW register.
152 uint32_t csw_default
;
155 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
156 * configure an access mode, such as autoincrementing AP_REG_TAR during
157 * word access. "-1" indicates no cached value.
162 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
163 * configure the address being read or written
164 * "-1" indicates no cached value.
169 * Configures how many extra tck clocks are added after starting a
170 * MEM-AP access before we try to read its status (and/or result).
172 uint32_t memaccess_tck
;
174 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
175 uint32_t tar_autoincr_block
;
177 /* true if packed transfers are supported by the MEM-AP */
178 bool packed_transfers
;
180 /* true if unaligned memory access is not supported by the MEM-AP */
181 bool unaligned_access_bad
;
186 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
187 * A DAP has two types of component: one Debug Port (DP), which is a
188 * transport agent; and at least one Access Port (AP), controlling
191 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
192 * Accordingly, this interface is responsible for hiding the transport
193 * differences so upper layer code can largely ignore them.
195 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
196 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
197 * a choice made at board design time (by only using the SWD pins), or
198 * as part of setting up a debug session (if all the dual-role JTAG/SWD
199 * signals are available).
202 const struct dap_ops
*ops
;
204 /* dap transaction list for WAIT support */
205 struct list_head cmd_journal
;
207 struct jtag_tap
*tap
;
209 uint32_t dp_ctrl_stat
;
211 struct adiv5_ap ap
[256];
213 /* The current manually selected AP by the "dap apsel" command */
217 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
218 * indicates no cached value and forces rewrite of the register.
222 /* information about current pending SWjDP-AHBAP transaction */
226 * Holds the pointer to the destination word for the last queued read,
227 * for use with posted AP read sequence optimization.
231 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
232 * despite lack of support in the ARMv7 architecture. Memory access through
233 * the AHB-AP has strange byte ordering these processors, and we need to
234 * swizzle appropriately. */
235 bool ti_be_32_quirks
;
238 * Signals that an attempt to reestablish communication afresh
239 * should be performed before the next access.
245 * Transport-neutral representation of queued DAP transactions, supporting
246 * both JTAG and SWD transports. All submitted transactions are logically
247 * queued, until the queue is executed by run(). Some implementations might
248 * execute transactions as soon as they're submitted, but no status is made
249 * available until run().
252 /** DP register read. */
253 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
255 /** DP register write. */
256 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
259 /** AP register read. */
260 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
262 /** AP register write. */
263 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
266 /** AP operation abort. */
267 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
269 /** Executes all queued DAP operations. */
270 int (*run
)(struct adiv5_dap
*dap
);
272 /** Executes all queued DAP operations but doesn't check
273 * sticky error conditions */
274 int (*sync
)(struct adiv5_dap
*dap
);
278 * Access Port classes
281 AP_CLASS_NONE
= 0x00000, /* No class defined */
282 AP_CLASS_MEM_AP
= 0x10000, /* MEM-AP */
289 AP_TYPE_JTAG_AP
= 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
290 AP_TYPE_AHB_AP
= 0x1, /* AHB Memory-AP */
291 AP_TYPE_APB_AP
= 0x2, /* APB Memory-AP */
292 AP_TYPE_AXI_AP
= 0x4, /* AXI Memory-AP */
296 * Queue a DP register read.
297 * Note that not all DP registers are readable; also, that JTAG and SWD
298 * have slight differences in DP register support.
300 * @param dap The DAP used for reading.
301 * @param reg The two-bit number of the DP register being read.
302 * @param data Pointer saying where to store the register's value
303 * (in host endianness).
305 * @return ERROR_OK for success, else a fault code.
307 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
308 unsigned reg
, uint32_t *data
)
310 assert(dap
->ops
!= NULL
);
311 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
315 * Queue a DP register write.
316 * Note that not all DP registers are writable; also, that JTAG and SWD
317 * have slight differences in DP register support.
319 * @param dap The DAP used for writing.
320 * @param reg The two-bit number of the DP register being written.
321 * @param data Value being written (host endianness)
323 * @return ERROR_OK for success, else a fault code.
325 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
326 unsigned reg
, uint32_t data
)
328 assert(dap
->ops
!= NULL
);
329 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
333 * Queue an AP register read.
335 * @param ap The AP used for reading.
336 * @param reg The number of the AP register being read.
337 * @param data Pointer saying where to store the register's value
338 * (in host endianness).
340 * @return ERROR_OK for success, else a fault code.
342 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
343 unsigned reg
, uint32_t *data
)
345 assert(ap
->dap
->ops
!= NULL
);
346 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
350 * Queue an AP register write.
352 * @param ap The AP used for writing.
353 * @param reg The number of the AP register being written.
354 * @param data Value being written (host endianness)
356 * @return ERROR_OK for success, else a fault code.
358 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
359 unsigned reg
, uint32_t data
)
361 assert(ap
->dap
->ops
!= NULL
);
362 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
366 * Queue an AP abort operation. The current AP transaction is aborted,
367 * including any update of the transaction counter. The AP is left in
368 * an unknown state (so it must be re-initialized). For use only after
369 * the AP has reported WAIT status for an extended period.
371 * @param dap The DAP used for writing.
372 * @param ack Pointer to where transaction status will be stored.
374 * @return ERROR_OK for success, else a fault code.
376 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
378 assert(dap
->ops
!= NULL
);
379 return dap
->ops
->queue_ap_abort(dap
, ack
);
383 * Perform all queued DAP operations, and clear any errors posted in the
384 * CTRL_STAT register when they are done. Note that if more than one AP
385 * operation will be queued, one of the first operations in the queue
386 * should probably enable CORUNDETECT in the CTRL/STAT register.
388 * @param dap The DAP used.
390 * @return ERROR_OK for success, else a fault code.
392 static inline int dap_run(struct adiv5_dap
*dap
)
394 assert(dap
->ops
!= NULL
);
395 return dap
->ops
->run(dap
);
398 static inline int dap_sync(struct adiv5_dap
*dap
)
400 assert(dap
->ops
!= NULL
);
402 return dap
->ops
->sync(dap
);
406 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
411 retval
= dap_queue_dp_read(dap
, reg
, value
);
412 if (retval
!= ERROR_OK
)
418 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
419 uint32_t mask
, uint32_t value
, int timeout
)
422 assert((value
& mask
) == value
);
426 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
429 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
433 if ((regval
& mask
) == value
)
440 LOG_DEBUG("DAP: poll %x timeout", reg
);
447 /* Queued MEM-AP memory mapped single word transfers. */
448 int mem_ap_read_u32(struct adiv5_ap
*ap
,
449 uint32_t address
, uint32_t *value
);
450 int mem_ap_write_u32(struct adiv5_ap
*ap
,
451 uint32_t address
, uint32_t value
);
453 /* Synchronous MEM-AP memory mapped single word transfers. */
454 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
455 uint32_t address
, uint32_t *value
);
456 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
457 uint32_t address
, uint32_t value
);
459 /* Synchronous MEM-AP memory mapped bus block transfers. */
460 int mem_ap_read_buf(struct adiv5_ap
*ap
,
461 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
462 int mem_ap_write_buf(struct adiv5_ap
*ap
,
463 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
465 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
466 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
467 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
468 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
469 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
471 /* Create DAP struct */
472 struct adiv5_dap
*dap_init(void);
474 /* Initialisation of the debug system, power domains and registers */
475 int dap_dp_init(struct adiv5_dap
*dap
);
476 int mem_ap_init(struct adiv5_ap
*ap
);
478 /* Probe the AP for ROM Table location */
479 int dap_get_debugbase(struct adiv5_ap
*ap
,
480 uint32_t *dbgbase
, uint32_t *apid
);
482 /* Probe Access Ports to find a particular type */
483 int dap_find_ap(struct adiv5_dap
*dap
,
484 enum ap_type type_to_find
,
485 struct adiv5_ap
**ap_out
);
487 static inline struct adiv5_ap
*dap_ap(struct adiv5_dap
*dap
, uint8_t ap_num
)
489 return &dap
->ap
[ap_num
];
492 /* Lookup CoreSight component */
493 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
494 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
);
498 /* Put debug link into SWD mode */
499 int dap_to_swd(struct target
*target
);
501 /* Put debug link into JTAG mode */
502 int dap_to_jtag(struct target
*target
);
504 extern const struct command_registration dap_command_handlers
[];
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)