1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
36 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
37 * is no longer JTAG-specific
39 #define JTAG_DP_DPACC 0xA
40 #define JTAG_DP_APACC 0xB
42 /* three-bit ACK values for SWD access (sent LSB first) */
43 #define SWD_ACK_OK 0x4
44 #define SWD_ACK_WAIT 0x2
45 #define SWD_ACK_FAULT 0x1
50 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
52 /* A[3:0] for DP registers; A[1:0] are always zero.
53 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
54 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
55 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
57 #define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */
58 #define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */
59 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */
60 #define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */
61 #define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */
62 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */
63 #define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */
65 #define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
66 #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
68 /* Fields of the DP's AP ABORT register */
69 #define DAPABORT (1 << 0)
70 #define STKCMPCLR (1 << 1) /* SWD-only */
71 #define STKERRCLR (1 << 2) /* SWD-only */
72 #define WDERRCLR (1 << 3) /* SWD-only */
73 #define ORUNERRCLR (1 << 4) /* SWD-only */
75 /* Fields of the DP's CTRL/STAT register */
76 #define CORUNDETECT (1 << 0)
77 #define SSTICKYORUN (1 << 1)
78 /* 3:2 - transaction mode (e.g. pushed compare) */
79 #define SSTICKYCMP (1 << 4)
80 #define SSTICKYERR (1 << 5)
81 #define READOK (1 << 6) /* SWD-only */
82 #define WDATAERR (1 << 7) /* SWD-only */
83 /* 11:8 - mask lanes for pushed compare or verify ops */
84 /* 21:12 - transaction counter */
85 #define CDBGRSTREQ (1 << 26)
86 #define CDBGRSTACK (1 << 27)
87 #define CDBGPWRUPREQ (1 << 28)
88 #define CDBGPWRUPACK (1 << 29)
89 #define CSYSPWRUPREQ (1 << 30)
90 #define CSYSPWRUPACK (1 << 31)
92 /* MEM-AP register addresses */
93 /* TODO: rename as MEM_AP_REG_* */
94 #define AP_REG_CSW 0x00
95 #define AP_REG_TAR 0x04
96 #define AP_REG_DRW 0x0C
97 #define AP_REG_BD0 0x10
98 #define AP_REG_BD1 0x14
99 #define AP_REG_BD2 0x18
100 #define AP_REG_BD3 0x1C
101 #define AP_REG_CFG 0xF4 /* big endian? */
102 #define AP_REG_BASE 0xF8
104 /* Generic AP register address */
105 #define AP_REG_IDR 0xFC
107 /* Fields of the MEM-AP's CSW register */
111 #define CSW_ADDRINC_MASK (3 << 4)
112 #define CSW_ADDRINC_OFF 0
113 #define CSW_ADDRINC_SINGLE (1 << 4)
114 #define CSW_ADDRINC_PACKED (2 << 4)
115 #define CSW_DEVICE_EN (1 << 6)
116 #define CSW_TRIN_PROG (1 << 7)
117 #define CSW_SPIDEN (1 << 23)
118 /* 30:24 - implementation-defined! */
119 #define CSW_HPROT (1 << 25) /* ? */
120 #define CSW_MASTER_DEBUG (1 << 29) /* ? */
121 #define CSW_SPROT (1 << 30)
122 #define CSW_DBGSWENABLE (1 << 31)
125 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
126 * A DAP has two types of component: one Debug Port (DP), which is a
127 * transport agent; and at least one Access Port (AP), controlling
128 * resource access. Most common is a MEM-AP, for memory access.
130 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
131 * Accordingly, this interface is responsible for hiding the transport
132 * differences so upper layer code can largely ignore them.
134 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
135 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
136 * a choice made at board design time (by only using the SWD pins), or
137 * as part of setting up a debug session (if all the dual-role JTAG/SWD
138 * signals are available).
141 const struct dap_ops
*ops
;
143 struct arm_jtag
*jtag_info
;
145 uint32_t dp_ctrl_stat
;
151 * Cache for DP_SELECT bits identifying the current AP. A DAP may
152 * connect to multiple APs, such as one MEM-AP for general access,
153 * another reserved for accessing debug modules, and a JTAG-DP.
154 * "-1" indicates no cached value.
159 * Cache for DP_SELECT bits identifying the current four-word AP
160 * register bank. This caches AP register addresss bits 7:4; JTAG
161 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
162 * "-1" indicates no cached value.
164 uint32_t ap_bank_value
;
167 * Cache for DP_SELECT bits identifying the current four-word DP
168 * register bank. This caches DP register addresss bits 7:4; JTAG
169 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
171 uint32_t dp_bank_value
;
174 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
175 * configure an access mode, such as autoincrementing AP_REG_TAR during
176 * word access. "-1" indicates no cached value.
178 uint32_t ap_csw_value
;
181 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
182 * configure the address being read or written
183 * "-1" indicates no cached value.
185 uint32_t ap_tar_value
;
187 /* information about current pending SWjDP-AHBAP transaction */
191 * Configures how many extra tck clocks are added after starting a
192 * MEM-AP access before we try to read its status (and/or result).
194 uint32_t memaccess_tck
;
196 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
197 uint32_t tar_autoincr_block
;
199 /* true if packed transfers are supported by the MEM-AP */
200 bool packed_transfers
;
202 /* true if unaligned memory access is not supported by the MEM-AP */
203 bool unaligned_access_bad
;
205 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
206 * despite lack of support in the ARMv7 architecture. Memory access through
207 * the AHB-AP has strange byte ordering these processors, and we need to
208 * swizzle appropriately. */
209 bool ti_be_32_quirks
;
213 * Transport-neutral representation of queued DAP transactions, supporting
214 * both JTAG and SWD transports. All submitted transactions are logically
215 * queued, until the queue is executed by run(). Some implementations might
216 * execute transactions as soon as they're submitted, but no status is made
217 * availablue until run().
220 /** If the DAP transport isn't SWD, it must be JTAG. Upper level
221 * code may need to care about the difference in some cases.
225 /** Reads the DAP's IDCODe register. */
226 int (*queue_idcode_read
)(struct adiv5_dap
*dap
,
227 uint8_t *ack
, uint32_t *data
);
229 /** DP register read. */
230 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
232 /** DP register write. */
233 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
236 /** AP register read. */
237 int (*queue_ap_read
)(struct adiv5_dap
*dap
, unsigned reg
,
239 /** AP register write. */
240 int (*queue_ap_write
)(struct adiv5_dap
*dap
, unsigned reg
,
242 /** AP read block. */
243 int (*queue_ap_read_block
)(struct adiv5_dap
*dap
, unsigned reg
,
244 uint32_t blocksize
, uint8_t *buffer
);
246 /** AP operation abort. */
247 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
249 /** Executes all queued DAP operations. */
250 int (*run
)(struct adiv5_dap
*dap
);
257 AP_TYPE_AHB_AP
= 0x01, /* AHB Memory-AP */
258 AP_TYPE_APB_AP
= 0x02, /* APB Memory-AP */
259 AP_TYPE_JTAG_AP
= 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
263 * Queue an IDCODE register read. This is primarily useful for SWD
264 * transports, where it is required as part of link initialization.
265 * (For JTAG, this register is read as part of scan chain setup.)
267 * @param dap The DAP used for reading.
268 * @param ack Pointer to where transaction status will be stored.
269 * @param data Pointer saying where to store the IDCODE value.
271 * @return ERROR_OK for success, else a fault code.
273 static inline int dap_queue_idcode_read(struct adiv5_dap
*dap
,
274 uint8_t *ack
, uint32_t *data
)
276 assert(dap
->ops
!= NULL
);
277 return dap
->ops
->queue_idcode_read(dap
, ack
, data
);
281 * Queue a DP register read.
282 * Note that not all DP registers are readable; also, that JTAG and SWD
283 * have slight differences in DP register support.
285 * @param dap The DAP used for reading.
286 * @param reg The two-bit number of the DP register being read.
287 * @param data Pointer saying where to store the register's value
288 * (in host endianness).
290 * @return ERROR_OK for success, else a fault code.
292 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
293 unsigned reg
, uint32_t *data
)
295 assert(dap
->ops
!= NULL
);
296 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
300 * Queue a DP register write.
301 * Note that not all DP registers are writable; also, that JTAG and SWD
302 * have slight differences in DP register support.
304 * @param dap The DAP used for writing.
305 * @param reg The two-bit number of the DP register being written.
306 * @param data Value being written (host endianness)
308 * @return ERROR_OK for success, else a fault code.
310 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
311 unsigned reg
, uint32_t data
)
313 assert(dap
->ops
!= NULL
);
314 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
318 * Queue an AP register read.
320 * @param dap The DAP used for reading.
321 * @param reg The number of the AP register being read.
322 * @param data Pointer saying where to store the register's value
323 * (in host endianness).
325 * @return ERROR_OK for success, else a fault code.
327 static inline int dap_queue_ap_read(struct adiv5_dap
*dap
,
328 unsigned reg
, uint32_t *data
)
330 assert(dap
->ops
!= NULL
);
331 return dap
->ops
->queue_ap_read(dap
, reg
, data
);
335 * Queue an AP register write.
337 * @param dap The DAP used for writing.
338 * @param reg The number of the AP register being written.
339 * @param data Value being written (host endianness)
341 * @return ERROR_OK for success, else a fault code.
343 static inline int dap_queue_ap_write(struct adiv5_dap
*dap
,
344 unsigned reg
, uint32_t data
)
346 assert(dap
->ops
!= NULL
);
347 return dap
->ops
->queue_ap_write(dap
, reg
, data
);
351 * Queue an AP block read.
353 * @param dap The DAP used for reading.
354 * @param reg The number of the AP register being read.
355 * @param blocksize The number of the AP register being read.
356 * @param buffer Pointer saying where to store the data
357 * (in host endianness).
359 * @return ERROR_OK for success, else a fault code.
361 static inline int dap_queue_ap_read_block(struct adiv5_dap
*dap
,
362 unsigned reg
, unsigned blocksize
, uint8_t *buffer
)
364 assert(dap
->ops
!= NULL
);
365 return dap
->ops
->queue_ap_read_block(dap
, reg
, blocksize
, buffer
);
369 * Queue an AP abort operation. The current AP transaction is aborted,
370 * including any update of the transaction counter. The AP is left in
371 * an unknown state (so it must be re-initialized). For use only after
372 * the AP has reported WAIT status for an extended period.
374 * @param dap The DAP used for writing.
375 * @param ack Pointer to where transaction status will be stored.
377 * @return ERROR_OK for success, else a fault code.
379 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
381 assert(dap
->ops
!= NULL
);
382 return dap
->ops
->queue_ap_abort(dap
, ack
);
386 * Perform all queued DAP operations, and clear any errors posted in the
387 * CTRL_STAT register when they are done. Note that if more than one AP
388 * operation will be queued, one of the first operations in the queue
389 * should probably enable CORUNDETECT in the CTRL/STAT register.
391 * @param dap The DAP used.
393 * @return ERROR_OK for success, else a fault code.
395 static inline int dap_run(struct adiv5_dap
*dap
)
397 assert(dap
->ops
!= NULL
);
398 return dap
->ops
->run(dap
);
401 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
406 retval
= dap_queue_dp_read(dap
, reg
, value
);
407 if (retval
!= ERROR_OK
)
413 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
414 uint32_t mask
, uint32_t value
, int timeout
)
417 assert((value
& mask
) == value
);
421 LOG_DEBUG("DAP: poll %x, mask 0x08%" PRIx32
", value 0x%08" PRIx32
,
424 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
428 if ((regval
& mask
) == value
)
435 LOG_DEBUG("DAP: poll %x timeout", reg
);
442 /** Accessor for currently selected DAP-AP number (0..255) */
443 static inline uint8_t dap_ap_get_select(struct adiv5_dap
*swjdp
)
445 return (uint8_t)(swjdp
->ap_current
>> 24);
448 /* AP selection applies to future AP transactions */
449 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
);
451 /* Queued AP transactions */
452 int dap_setup_accessport(struct adiv5_dap
*swjdp
,
453 uint32_t csw
, uint32_t tar
);
455 /* Queued MEM-AP memory mapped single word transfers */
456 int mem_ap_read_u32(struct adiv5_dap
*swjdp
, uint32_t address
, uint32_t *value
);
457 int mem_ap_write_u32(struct adiv5_dap
*swjdp
, uint32_t address
, uint32_t value
);
459 /* Synchronous MEM-AP memory mapped single word transfers */
460 int mem_ap_read_atomic_u32(struct adiv5_dap
*swjdp
,
461 uint32_t address
, uint32_t *value
);
462 int mem_ap_write_atomic_u32(struct adiv5_dap
*swjdp
,
463 uint32_t address
, uint32_t value
);
465 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
466 int mem_ap_sel_read_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
467 uint32_t address
, uint32_t *value
);
468 int mem_ap_sel_write_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
469 uint32_t address
, uint32_t value
);
471 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
472 int mem_ap_sel_read_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
473 uint32_t address
, uint32_t *value
);
474 int mem_ap_sel_write_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
475 uint32_t address
, uint32_t value
);
477 /* Synchronous MEM-AP memory mapped bus block transfers */
478 int mem_ap_read(struct adiv5_dap
*dap
, uint8_t *buffer
, uint32_t size
,
479 uint32_t count
, uint32_t address
, bool addrinc
);
480 int mem_ap_write(struct adiv5_dap
*dap
, const uint8_t *buffer
, uint32_t size
,
481 uint32_t count
, uint32_t address
, bool addrinc
);
483 /* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
484 int mem_ap_sel_read_buf(struct adiv5_dap
*swjdp
, uint8_t ap
,
485 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
486 int mem_ap_sel_write_buf(struct adiv5_dap
*swjdp
, uint8_t ap
,
487 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
489 /* Synchronous, non-incrementing buffer functions for accessing fifos, with
491 int mem_ap_sel_read_buf_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
492 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
493 int mem_ap_sel_write_buf_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
494 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
496 /* Initialisation of the debug system, power domains and registers */
497 int ahbap_debugport_init(struct adiv5_dap
*swjdp
);
499 /* Probe the AP for ROM Table location */
500 int dap_get_debugbase(struct adiv5_dap
*dap
, int ap
,
501 uint32_t *dbgbase
, uint32_t *apid
);
503 /* Probe Access Ports to find a particular type */
504 int dap_find_ap(struct adiv5_dap
*dap
,
505 enum ap_type type_to_find
,
506 uint8_t *ap_num_out
);
508 /* Lookup CoreSight component */
509 int dap_lookup_cs_component(struct adiv5_dap
*dap
, int ap
,
510 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
);
514 /* Put debug link into SWD mode */
515 int dap_to_swd(struct target
*target
);
517 /* Put debug link into JTAG mode */
518 int dap_to_jtag(struct target
*target
);
520 extern const struct command_registration dap_command_handlers
[];
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