src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARM_ADI_V5_H
  24 #define ARM_ADI_V5_H
  25
  26 /**
  27  * @file
  28  * This defines formats and data structures used to talk to ADIv5 entities.
  29  * Those include a DAP, different types of Debug Port (DP), and memory mapped
  30  * resources accessed through a MEM-AP.
  31  */
  32
  33 #include "arm_jtag.h"
  34
  35 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
  36  * is no longer JTAG-specific
  37  */
  38 #define JTAG_DP_DPACC           0xA
  39 #define JTAG_DP_APACC           0xB
  40
  41 /* three-bit ACK values for SWD access (sent LSB first) */
  42 #define SWD_ACK_OK              0x4
  43 #define SWD_ACK_WAIT            0x2
  44 #define SWD_ACK_FAULT           0x1
  45
  46 #define DPAP_WRITE              0
  47 #define DPAP_READ               1
  48
  49 /* A[3:0] for DP registers; A[1:0] are always zero.
  50  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  51  *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
  52  * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
  53  */
  54 #define DP_IDCODE               0               /* SWD: read */
  55 #define DP_ABORT                0               /* SWD: write */
  56 #define DP_CTRL_STAT            0x4             /* r/w */
  57 #define DP_WCR                  0x4             /* SWD: r/w (mux CTRLSEL) */
  58 #define DP_RESEND               0x8             /* SWD: read */
  59 #define DP_SELECT               0x8             /* JTAG: r/w; SWD: write */
  60 #define DP_RDBUFF               0xC             /* read-only */
  61
  62 #define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8))        /* 1..4 clocks */
  63 #define WCR_TO_PRESCALE(wcr) (7 & ((wcr)))              /* impl defined */
  64
  65 /* Fields of the DP's AP ABORT register */
  66 #define DAPABORT                (1 << 0)
  67 #define STKCMPCLR               (1 << 1)        /* SWD-only */
  68 #define STKERRCLR               (1 << 2)        /* SWD-only */
  69 #define WDERRCLR                (1 << 3)        /* SWD-only */
  70 #define ORUNERRCLR              (1 << 4)        /* SWD-only */
  71
  72 /* Fields of the DP's CTRL/STAT register */
  73 #define CORUNDETECT             (1 << 0)
  74 #define SSTICKYORUN             (1 << 1)
  75 /* 3:2 - transaction mode (e.g. pushed compare) */
  76 #define SSTICKYCMP              (1 << 4)
  77 #define SSTICKYERR              (1 << 5)
  78 #define READOK                  (1 << 6)        /* SWD-only */
  79 #define WDATAERR                (1 << 7)        /* SWD-only */
  80 /* 11:8 - mask lanes for pushed compare or verify ops */
  81 /* 21:12 - transaction counter */
  82 #define CDBGRSTREQ              (1 << 26)
  83 #define CDBGRSTACK              (1 << 27)
  84 #define CDBGPWRUPREQ    (1 << 28)
  85 #define CDBGPWRUPACK    (1 << 29)
  86 #define CSYSPWRUPREQ    (1 << 30)
  87 #define CSYSPWRUPACK    (1 << 31)
  88
  89 /* MEM-AP register addresses */
  90 /* TODO: rename as MEM_AP_REG_* */
  91 #define AP_REG_CSW              0x00
  92 #define AP_REG_TAR              0x04
  93 #define AP_REG_DRW              0x0C
  94 #define AP_REG_BD0              0x10
  95 #define AP_REG_BD1              0x14
  96 #define AP_REG_BD2              0x18
  97 #define AP_REG_BD3              0x1C
  98 #define AP_REG_CFG              0xF4            /* big endian? */
  99 #define AP_REG_BASE             0xF8
 100
 101 /* Generic AP register address */
 102 #define AP_REG_IDR              0xFC
 103
 104 /* Fields of the MEM-AP's CSW register */
 105 #define CSW_8BIT                0
 106 #define CSW_16BIT               1
 107 #define CSW_32BIT               2
 108 #define CSW_ADDRINC_MASK        (3 << 4)
 109 #define CSW_ADDRINC_OFF         0
 110 #define CSW_ADDRINC_SINGLE      (1 << 4)
 111 #define CSW_ADDRINC_PACKED      (2 << 4)
 112 #define CSW_DEVICE_EN           (1 << 6)
 113 #define CSW_TRIN_PROG           (1 << 7)
 114 #define CSW_SPIDEN                      (1 << 23)
 115 /* 30:24 - implementation-defined! */
 116 #define CSW_HPROT                       (1 << 25)               /* ? */
 117 #define CSW_MASTER_DEBUG        (1 << 29)               /* ? */
 118 #define CSW_DBGSWENABLE         (1 << 31)
 119
 120 /**
 121  * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
 122  * A DAP has two types of component:  one Debug Port (DP), which is a
 123  * transport agent; and at least one Access Port (AP), controlling
 124  * resource access.  Most common is a MEM-AP, for memory access.
 125  *
 126  * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
 127  * Accordingly, this interface is responsible for hiding the transport
 128  * differences so upper layer code can largely ignore them.
 129  *
 130  * When the chip is implemented with JTAG-DP or SW-DP, the transport is
 131  * fixed as JTAG or SWD, respectively.  Chips incorporating SWJ-DP permit
 132  * a choice made at board design time (by only using the SWD pins), or
 133  * as part of setting up a debug session (if all the dual-role JTAG/SWD
 134  * signals are available).
 135  */
 136 struct adiv5_dap
 137 {
 138         const struct dap_ops *ops;
 139
 140         struct arm_jtag *jtag_info;
 141         /* Control config */
 142         uint32_t dp_ctrl_stat;
 143
 144
 145         uint32_t apsel;
 146
 147         /**
 148          * Cache for DP_SELECT bits identifying the current AP.  A DAP may
 149          * connect to multiple APs, such as one MEM-AP for general access,
 150          * another reserved for accessing debug modules, and a JTAG-DP.
 151          * "-1" indicates no cached value.
 152          */
 153         uint32_t ap_current;
 154
 155         /**
 156          * Cache for DP_SELECT bits identifying the current four-word AP
 157          * register bank.  This caches AP register addresss bits 7:4; JTAG
 158          * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
 159          * "-1" indicates no cached value.
 160          */
 161         uint32_t ap_bank_value;
 162
 163         /**
 164          * Cache for (MEM-AP) AP_REG_CSW register value.  This is written to
 165          * configure an access mode, such as autoincrementing AP_REG_TAR during
 166          * word access.  "-1" indicates no cached value.
 167          */
 168         uint32_t ap_csw_value;
 169
 170         /**
 171          * Cache for (MEM-AP) AP_REG_TAR register value This is written to
 172          * configure the address being read or written
 173          * "-1" indicates no cached value.
 174          */
 175         uint32_t ap_tar_value;
 176
 177         /* information about current pending SWjDP-AHBAP transaction */
 178         uint8_t  ack;
 179
 180         /**
 181          * Configures how many extra tck clocks are added after starting a
 182          * MEM-AP access before we try to read its status (and/or result).
 183          */
 184         uint32_t        memaccess_tck;
 185         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 186         uint32_t tar_autoincr_block;
 187 };
 188
 189 /**
 190  * Transport-neutral representation of queued DAP transactions, supporting
 191  * both JTAG and SWD transports.  All submitted transactions are logically
 192  * queued, until the queue is executed by run().  Some implementations might
 193  * execute transactions as soon as they're submitted, but no status is made
 194  * availablue until run().
 195  */
 196 struct dap_ops {
 197         /** If the DAP transport isn't SWD, it must be JTAG.  Upper level
 198          * code may need to care about the difference in some cases.
 199          */
 200         bool    is_swd;
 201
 202         /** Reads the DAP's IDCODe register. */
 203         int (*queue_idcode_read)(struct adiv5_dap *dap,
 204                         uint8_t *ack, uint32_t *data);
 205
 206         /** DP register read. */
 207         int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
 208                         uint32_t *data);
 209         /** DP register write. */
 210         int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
 211                         uint32_t data);
 212
 213         /** AP register read. */
 214         int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
 215                         uint32_t *data);
 216         /** AP register write. */
 217         int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
 218                         uint32_t data);
 219         /** AP operation abort. */
 220         int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
 221
 222         /** Executes all queued DAP operations. */
 223         int (*run)(struct adiv5_dap *dap);
 224 };
 225
 226 /**
 227  * Queue an IDCODE register read.  This is primarily useful for SWD
 228  * transports, where it is required as part of link initialization.
 229  * (For JTAG, this register is read as part of scan chain setup.)
 230  *
 231  * @param dap The DAP used for reading.
 232  * @param ack Pointer to where transaction status will be stored.
 233  * @param data Pointer saying where to store the IDCODE value.
 234  *
 235  * @return ERROR_OK for success, else a fault code.
 236  */
 237 static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
 238                 uint8_t *ack, uint32_t *data)
 239 {
 240         assert(dap->ops != NULL);
 241         return dap->ops->queue_idcode_read(dap, ack, data);
 242 }
 243
 244 /**
 245  * Queue a DP register read.
 246  * Note that not all DP registers are readable; also, that JTAG and SWD
 247  * have slight differences in DP register support.
 248  *
 249  * @param dap The DAP used for reading.
 250  * @param reg The two-bit number of the DP register being read.
 251  * @param data Pointer saying where to store the register's value
 252  *      (in host endianness).
 253  *
 254  * @return ERROR_OK for success, else a fault code.
 255  */
 256 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
 257                 unsigned reg, uint32_t *data)
 258 {
 259         assert(dap->ops != NULL);
 260         return dap->ops->queue_dp_read(dap, reg, data);
 261 }
 262
 263 /**
 264  * Queue a DP register write.
 265  * Note that not all DP registers are writable; also, that JTAG and SWD
 266  * have slight differences in DP register support.
 267  *
 268  * @param dap The DAP used for writing.
 269  * @param reg The two-bit number of the DP register being written.
 270  * @param data Value being written (host endianness)
 271  *
 272  * @return ERROR_OK for success, else a fault code.
 273  */
 274 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
 275                 unsigned reg, uint32_t data)
 276 {
 277         assert(dap->ops != NULL);
 278         return dap->ops->queue_dp_write(dap, reg, data);
 279 }
 280
 281 /**
 282  * Queue an AP register read.
 283  *
 284  * @param dap The DAP used for reading.
 285  * @param reg The number of the AP register being read.
 286  * @param data Pointer saying where to store the register's value
 287  *      (in host endianness).
 288  *
 289  * @return ERROR_OK for success, else a fault code.
 290  */
 291 static inline int dap_queue_ap_read(struct adiv5_dap *dap,
 292                 unsigned reg, uint32_t *data)
 293 {
 294         assert(dap->ops != NULL);
 295         return dap->ops->queue_ap_read(dap, reg, data);
 296 }
 297
 298 /**
 299  * Queue an AP register write.
 300  *
 301  * @param dap The DAP used for writing.
 302  * @param reg The number of the AP register being written.
 303  * @param data Value being written (host endianness)
 304  *
 305  * @return ERROR_OK for success, else a fault code.
 306  */
 307 static inline int dap_queue_ap_write(struct adiv5_dap *dap,
 308                 unsigned reg, uint32_t data)
 309 {
 310         assert(dap->ops != NULL);
 311         return dap->ops->queue_ap_write(dap, reg, data);
 312 }
 313
 314 /**
 315  * Queue an AP abort operation.  The current AP transaction is aborted,
 316  * including any update of the transaction counter.  The AP is left in
 317  * an unknown state (so it must be re-initialized).  For use only after
 318  * the AP has reported WAIT status for an extended period.
 319  *
 320  * @param dap The DAP used for writing.
 321  * @param ack Pointer to where transaction status will be stored.
 322  *
 323  * @return ERROR_OK for success, else a fault code.
 324  */
 325 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 326 {
 327         assert(dap->ops != NULL);
 328         return dap->ops->queue_ap_abort(dap, ack);
 329 }
 330
 331 /**
 332  * Perform all queued DAP operations, and clear any errors posted in the
 333  * CTRL_STAT register when they are done.  Note that if more than one AP
 334  * operation will be queued, one of the first operations in the queue
 335  * should probably enable CORUNDETECT in the CTRL/STAT register.
 336  *
 337  * @param dap The DAP used.
 338  *
 339  * @return ERROR_OK for success, else a fault code.
 340  */
 341 static inline int dap_run(struct adiv5_dap *dap)
 342 {
 343         assert(dap->ops != NULL);
 344         return dap->ops->run(dap);
 345 }
 346
 347 /** Accessor for currently selected DAP-AP number (0..255) */
 348 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
 349 {
 350         return (uint8_t)(swjdp ->ap_current >> 24);
 351 }
 352
 353 /* AP selection applies to future AP transactions */
 354 void dap_ap_select(struct adiv5_dap *dap,uint8_t ap);
 355
 356 /* Queued AP transactions */
 357 int dap_setup_accessport(struct adiv5_dap *swjdp,
 358                 uint32_t csw, uint32_t tar);
 359
 360 /* Queued MEM-AP memory mapped single word transfers */
 361 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
 362 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
 363
 364 /* Synchronous MEM-AP memory mapped single word transfers */
 365 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
 366                 uint32_t address, uint32_t *value);
 367 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
 368                 uint32_t address, uint32_t value);
 369
 370 /* MEM-AP memory mapped bus block transfers */
 371 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
 372                 uint8_t *buffer, int count, uint32_t address);
 373 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
 374                 uint8_t *buffer, int count, uint32_t address);
 375 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
 376                 uint8_t *buffer, int count, uint32_t address);
 377
 378 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
 379                 uint8_t *buffer, int count, uint32_t address);
 380 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
 381                 uint8_t *buffer, int count, uint32_t address);
 382 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
 383                 uint8_t *buffer, int count, uint32_t address);
 384
 385
 386
 387 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
 388 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 389                 uint32_t address, uint32_t *value);
 390 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 391                 uint32_t address, uint32_t value);
 392
 393 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
 394 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 395                 uint32_t address, uint32_t *value);
 396 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 397                 uint32_t address, uint32_t value);
 398
 399 /* MEM-AP memory mapped bus block transfers with selection of ap */
 400 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 401                 uint8_t *buffer, int count, uint32_t address);
 402 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 403                 uint8_t *buffer, int count, uint32_t address);
 404 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 405                 uint8_t *buffer, int count, uint32_t address);
 406
 407 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 408                 uint8_t *buffer, int count, uint32_t address);
 409 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 410                 uint8_t *buffer, int count, uint32_t address);
 411 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 412                 uint8_t *buffer, int count, uint32_t address);
 413
 414
 415
 416 /* Initialisation of the debug system, power domains and registers */
 417 int ahbap_debugport_init(struct adiv5_dap *swjdp);
 418
 419 /* Probe the AP for ROM Table location */
 420 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 421                         uint32_t *dbgbase, uint32_t *apid);
 422
 423 /* Lookup CoreSight component */
 424 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 425                         uint32_t dbgbase, uint8_t type, uint32_t *addr);
 426
 427 struct target;
 428
 429 /* Put debug link into SWD mode */
 430 int dap_to_swd(struct target *target);
 431
 432 /* Put debug link into JTAG mode */
 433 int dap_to_jtag(struct target *target);
 434
 435 extern const struct command_registration dap_command_handlers[];
 436
 437 #endif