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[openocd.git] / src / target / armv4_5.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "arm.h"
32 #include "armv4_5.h"
33 #include "arm_jtag.h"
34 #include "breakpoints.h"
35 #include "arm_disassembler.h"
36 #include <helper/binarybuffer.h>
37 #include "algorithm.h"
38 #include "register.h"
39
40 /* offsets into armv4_5 core register cache */
41 enum {
42 /* ARMV4_5_CPSR = 31, */
43 ARMV4_5_SPSR_FIQ = 32,
44 ARMV4_5_SPSR_IRQ = 33,
45 ARMV4_5_SPSR_SVC = 34,
46 ARMV4_5_SPSR_ABT = 35,
47 ARMV4_5_SPSR_UND = 36,
48 ARM_SPSR_MON = 39,
49 };
50
51 static const uint8_t arm_usr_indices[17] = {
52 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
53 };
54
55 static const uint8_t arm_fiq_indices[8] = {
56 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
57 };
58
59 static const uint8_t arm_irq_indices[3] = {
60 23, 24, ARMV4_5_SPSR_IRQ,
61 };
62
63 static const uint8_t arm_svc_indices[3] = {
64 25, 26, ARMV4_5_SPSR_SVC,
65 };
66
67 static const uint8_t arm_abt_indices[3] = {
68 27, 28, ARMV4_5_SPSR_ABT,
69 };
70
71 static const uint8_t arm_und_indices[3] = {
72 29, 30, ARMV4_5_SPSR_UND,
73 };
74
75 static const uint8_t arm_mon_indices[3] = {
76 37, 38, ARM_SPSR_MON,
77 };
78
79 static const struct {
80 const char *name;
81 unsigned short psr;
82 /* For user and system modes, these list indices for all registers.
83 * otherwise they're just indices for the shadow registers and SPSR.
84 */
85 unsigned short n_indices;
86 const uint8_t *indices;
87 } arm_mode_data[] = {
88 /* Seven modes are standard from ARM7 on. "System" and "User" share
89 * the same registers; other modes shadow from 3 to 8 registers.
90 */
91 {
92 .name = "User",
93 .psr = ARM_MODE_USR,
94 .n_indices = ARRAY_SIZE(arm_usr_indices),
95 .indices = arm_usr_indices,
96 },
97 {
98 .name = "FIQ",
99 .psr = ARM_MODE_FIQ,
100 .n_indices = ARRAY_SIZE(arm_fiq_indices),
101 .indices = arm_fiq_indices,
102 },
103 {
104 .name = "Supervisor",
105 .psr = ARM_MODE_SVC,
106 .n_indices = ARRAY_SIZE(arm_svc_indices),
107 .indices = arm_svc_indices,
108 },
109 {
110 .name = "Abort",
111 .psr = ARM_MODE_ABT,
112 .n_indices = ARRAY_SIZE(arm_abt_indices),
113 .indices = arm_abt_indices,
114 },
115 {
116 .name = "IRQ",
117 .psr = ARM_MODE_IRQ,
118 .n_indices = ARRAY_SIZE(arm_irq_indices),
119 .indices = arm_irq_indices,
120 },
121 {
122 .name = "Undefined instruction",
123 .psr = ARM_MODE_UND,
124 .n_indices = ARRAY_SIZE(arm_und_indices),
125 .indices = arm_und_indices,
126 },
127 {
128 .name = "System",
129 .psr = ARM_MODE_SYS,
130 .n_indices = ARRAY_SIZE(arm_usr_indices),
131 .indices = arm_usr_indices,
132 },
133 /* TrustZone "Security Extensions" add a secure monitor mode.
134 * This is distinct from a "debug monitor" which can support
135 * non-halting debug, in conjunction with some debuggers.
136 */
137 {
138 .name = "Secure Monitor",
139 .psr = ARM_MODE_MON,
140 .n_indices = ARRAY_SIZE(arm_mon_indices),
141 .indices = arm_mon_indices,
142 },
143 };
144
145 /** Map PSR mode bits to the name of an ARM processor operating mode. */
146 const char *arm_mode_name(unsigned psr_mode)
147 {
148 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
149 if (arm_mode_data[i].psr == psr_mode)
150 return arm_mode_data[i].name;
151 }
152 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
153 return "UNRECOGNIZED";
154 }
155
156 /** Return true iff the parameter denotes a valid ARM processor mode. */
157 bool is_arm_mode(unsigned psr_mode)
158 {
159 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
160 if (arm_mode_data[i].psr == psr_mode)
161 return true;
162 }
163 return false;
164 }
165
166 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
167 int arm_mode_to_number(enum arm_mode mode)
168 {
169 switch (mode) {
170 case ARM_MODE_ANY:
171 /* map MODE_ANY to user mode */
172 case ARM_MODE_USR:
173 return 0;
174 case ARM_MODE_FIQ:
175 return 1;
176 case ARM_MODE_IRQ:
177 return 2;
178 case ARM_MODE_SVC:
179 return 3;
180 case ARM_MODE_ABT:
181 return 4;
182 case ARM_MODE_UND:
183 return 5;
184 case ARM_MODE_SYS:
185 return 6;
186 case ARM_MODE_MON:
187 return 7;
188 default:
189 LOG_ERROR("invalid mode value encountered %d", mode);
190 return -1;
191 }
192 }
193
194 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
195 enum arm_mode armv4_5_number_to_mode(int number)
196 {
197 switch (number) {
198 case 0:
199 return ARM_MODE_USR;
200 case 1:
201 return ARM_MODE_FIQ;
202 case 2:
203 return ARM_MODE_IRQ;
204 case 3:
205 return ARM_MODE_SVC;
206 case 4:
207 return ARM_MODE_ABT;
208 case 5:
209 return ARM_MODE_UND;
210 case 6:
211 return ARM_MODE_SYS;
212 case 7:
213 return ARM_MODE_MON;
214 default:
215 LOG_ERROR("mode index out of bounds %d", number);
216 return ARM_MODE_ANY;
217 }
218 }
219
220 static const char *arm_state_strings[] = {
221 "ARM", "Thumb", "Jazelle", "ThumbEE",
222 };
223
224 /* Templates for ARM core registers.
225 *
226 * NOTE: offsets in this table are coupled to the arm_mode_data
227 * table above, the armv4_5_core_reg_map array below, and also to
228 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
229 */
230 static const struct {
231 /* The name is used for e.g. the "regs" command. */
232 const char *name;
233
234 /* The {cookie, mode} tuple uniquely identifies one register.
235 * In a given mode, cookies 0..15 map to registers R0..R15,
236 * with R13..R15 usually called SP, LR, PC.
237 *
238 * MODE_ANY is used as *input* to the mapping, and indicates
239 * various special cases (sigh) and errors.
240 *
241 * Cookie 16 is (currently) confusing, since it indicates
242 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
243 * (Exception modes have both CPSR and SPSR registers ...)
244 */
245 unsigned cookie;
246 enum arm_mode mode;
247 } arm_core_regs[] = {
248 /* IMPORTANT: we guarantee that the first eight cached registers
249 * correspond to r0..r7, and the fifteenth to PC, so that callers
250 * don't need to map them.
251 */
252 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
253 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
254 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
255 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
256 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
257 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
258 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
259 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
260
261 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
262 * them as MODE_ANY creates special cases. (ANY means
263 * "not mapped" elsewhere; here it's "everything but FIQ".)
264 */
265 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
266 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
267 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
268 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
269 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
270
271 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
272 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
273 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
274
275 /* guaranteed to be at index 15 */
276 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
277
278 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
279 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
280 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
281 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
282 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
283
284 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
285 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
286
287 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
288 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
289
290 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
291 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
292
293 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
294 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
295
296 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
297 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
298
299 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
300 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
301 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
302 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
303 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
304 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
305
306 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
307 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
308 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
309 };
310
311 /* map core mode (USR, FIQ, ...) and register number to
312 * indices into the register cache
313 */
314 const int armv4_5_core_reg_map[8][17] = {
315 { /* USR */
316 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
317 },
318 { /* FIQ (8 shadows of USR, vs normal 3) */
319 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
320 },
321 { /* IRQ */
322 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
323 },
324 { /* SVC */
325 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
326 },
327 { /* ABT */
328 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
329 },
330 { /* UND */
331 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
332 },
333 { /* SYS (same registers as USR) */
334 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
335 },
336 { /* MON */
337 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
338 }
339 };
340
341 /**
342 * Configures host-side ARM records to reflect the specified CPSR.
343 * Later, code can use arm_reg_current() to map register numbers
344 * according to how they are exposed by this mode.
345 */
346 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
347 {
348 enum arm_mode mode = cpsr & 0x1f;
349 int num;
350
351 /* NOTE: this may be called very early, before the register
352 * cache is set up. We can't defend against many errors, in
353 * particular against CPSRs that aren't valid *here* ...
354 */
355 if (arm->cpsr) {
356 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
357 arm->cpsr->valid = 1;
358 arm->cpsr->dirty = 0;
359 }
360
361 arm->core_mode = mode;
362
363 /* mode_to_number() warned; set up a somewhat-sane mapping */
364 num = arm_mode_to_number(mode);
365 if (num < 0) {
366 mode = ARM_MODE_USR;
367 num = 0;
368 }
369
370 arm->map = &armv4_5_core_reg_map[num][0];
371 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
372 ? NULL
373 : arm->core_cache->reg_list + arm->map[16];
374
375 /* Older ARMs won't have the J bit */
376 enum arm_state state;
377
378 if (cpsr & (1 << 5)) { /* T */
379 if (cpsr & (1 << 24)) { /* J */
380 LOG_WARNING("ThumbEE -- incomplete support");
381 state = ARM_STATE_THUMB_EE;
382 } else
383 state = ARM_STATE_THUMB;
384 } else {
385 if (cpsr & (1 << 24)) { /* J */
386 LOG_ERROR("Jazelle state handling is BROKEN!");
387 state = ARM_STATE_JAZELLE;
388 } else
389 state = ARM_STATE_ARM;
390 }
391 arm->core_state = state;
392
393 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
394 arm_mode_name(mode),
395 arm_state_strings[arm->core_state]);
396 }
397
398 /**
399 * Returns handle to the register currently mapped to a given number.
400 * Someone must have called arm_set_cpsr() before.
401 *
402 * \param arm This core's state and registers are used.
403 * \param regnum From 0..15 corresponding to R0..R14 and PC.
404 * Note that R0..R7 don't require mapping; you may access those
405 * as the first eight entries in the register cache. Likewise
406 * R15 (PC) doesn't need mapping; you may also access it directly.
407 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
408 * CPSR (arm->cpsr) is also not mapped.
409 */
410 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
411 {
412 struct reg *r;
413
414 if (regnum > 16)
415 return NULL;
416
417 r = arm->core_cache->reg_list + arm->map[regnum];
418
419 /* e.g. invalid CPSR said "secure monitor" mode on a core
420 * that doesn't support it...
421 */
422 if (!r) {
423 LOG_ERROR("Invalid CPSR mode");
424 r = arm->core_cache->reg_list + regnum;
425 }
426
427 return r;
428 }
429
430 static const uint8_t arm_gdb_dummy_fp_value[12];
431
432 /**
433 * Dummy FPA registers are required to support GDB on ARM.
434 * Register packets require eight obsolete FPA register values.
435 * Modern ARM cores use Vector Floating Point (VFP), if they
436 * have any floating point support. VFP is not FPA-compatible.
437 */
438 struct reg arm_gdb_dummy_fp_reg = {
439 .name = "GDB dummy FPA register",
440 .value = (uint8_t *) arm_gdb_dummy_fp_value,
441 .valid = 1,
442 .size = 96,
443 };
444
445 static const uint8_t arm_gdb_dummy_fps_value[4];
446
447 /**
448 * Dummy FPA status registers are required to support GDB on ARM.
449 * Register packets require an obsolete FPA status register.
450 */
451 struct reg arm_gdb_dummy_fps_reg = {
452 .name = "GDB dummy FPA status register",
453 .value = (uint8_t *) arm_gdb_dummy_fps_value,
454 .valid = 1,
455 .size = 32,
456 };
457
458 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
459
460 static void arm_gdb_dummy_init(void)
461 {
462 register_init_dummy(&arm_gdb_dummy_fp_reg);
463 register_init_dummy(&arm_gdb_dummy_fps_reg);
464 }
465
466 static int armv4_5_get_core_reg(struct reg *reg)
467 {
468 int retval;
469 struct arm_reg *reg_arch_info = reg->arch_info;
470 struct target *target = reg_arch_info->target;
471
472 if (target->state != TARGET_HALTED) {
473 LOG_ERROR("Target not halted");
474 return ERROR_TARGET_NOT_HALTED;
475 }
476
477 retval = reg_arch_info->arm->read_core_reg(target, reg,
478 reg_arch_info->num, reg_arch_info->mode);
479 if (retval == ERROR_OK) {
480 reg->valid = 1;
481 reg->dirty = 0;
482 }
483
484 return retval;
485 }
486
487 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
488 {
489 struct arm_reg *reg_arch_info = reg->arch_info;
490 struct target *target = reg_arch_info->target;
491 struct arm *armv4_5_target = target_to_arm(target);
492 uint32_t value = buf_get_u32(buf, 0, 32);
493
494 if (target->state != TARGET_HALTED) {
495 LOG_ERROR("Target not halted");
496 return ERROR_TARGET_NOT_HALTED;
497 }
498
499 /* Except for CPSR, the "reg" command exposes a writeback model
500 * for the register cache.
501 */
502 if (reg == armv4_5_target->cpsr) {
503 arm_set_cpsr(armv4_5_target, value);
504
505 /* Older cores need help to be in ARM mode during halt
506 * mode debug, so we clear the J and T bits if we flush.
507 * For newer cores (v6/v7a/v7r) we don't need that, but
508 * it won't hurt since CPSR is always flushed anyway.
509 */
510 if (armv4_5_target->core_mode !=
511 (enum arm_mode)(value & 0x1f)) {
512 LOG_DEBUG("changing ARM core mode to '%s'",
513 arm_mode_name(value & 0x1f));
514 value &= ~((1 << 24) | (1 << 5));
515 armv4_5_target->write_core_reg(target, reg,
516 16, ARM_MODE_ANY, value);
517 }
518 } else {
519 buf_set_u32(reg->value, 0, 32, value);
520 reg->valid = 1;
521 }
522 reg->dirty = 1;
523
524 return ERROR_OK;
525 }
526
527 static const struct reg_arch_type arm_reg_type = {
528 .get = armv4_5_get_core_reg,
529 .set = armv4_5_set_core_reg,
530 };
531
532 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
533 {
534 int num_regs = ARRAY_SIZE(arm_core_regs);
535 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
536 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
537 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
538 int i;
539
540 if (!cache || !reg_list || !reg_arch_info) {
541 free(cache);
542 free(reg_list);
543 free(reg_arch_info);
544 return NULL;
545 }
546
547 cache->name = "ARM registers";
548 cache->next = NULL;
549 cache->reg_list = reg_list;
550 cache->num_regs = 0;
551
552 for (i = 0; i < num_regs; i++) {
553 /* Skip registers this core doesn't expose */
554 if (arm_core_regs[i].mode == ARM_MODE_MON
555 && arm->core_type != ARM_MODE_MON)
556 continue;
557
558 /* REVISIT handle Cortex-M, which only shadows R13/SP */
559
560 reg_arch_info[i].num = arm_core_regs[i].cookie;
561 reg_arch_info[i].mode = arm_core_regs[i].mode;
562 reg_arch_info[i].target = target;
563 reg_arch_info[i].arm = arm;
564
565 reg_list[i].name = (char *) arm_core_regs[i].name;
566 reg_list[i].size = 32;
567 reg_list[i].value = &reg_arch_info[i].value;
568 reg_list[i].type = &arm_reg_type;
569 reg_list[i].arch_info = &reg_arch_info[i];
570
571 cache->num_regs++;
572 }
573
574 arm->pc = reg_list + 15;
575 arm->cpsr = reg_list + ARMV4_5_CPSR;
576 arm->core_cache = cache;
577 return cache;
578 }
579
580 int arm_arch_state(struct target *target)
581 {
582 struct arm *arm = target_to_arm(target);
583
584 if (arm->common_magic != ARM_COMMON_MAGIC) {
585 LOG_ERROR("BUG: called for a non-ARM target");
586 return ERROR_FAIL;
587 }
588
589 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
590 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
591 arm_state_strings[arm->core_state],
592 debug_reason_name(target),
593 arm_mode_name(arm->core_mode),
594 buf_get_u32(arm->cpsr->value, 0, 32),
595 buf_get_u32(arm->pc->value, 0, 32),
596 arm->is_semihosting ? ", semihosting" : "");
597
598 return ERROR_OK;
599 }
600
601 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
602 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
603
604 COMMAND_HANDLER(handle_armv4_5_reg_command)
605 {
606 struct target *target = get_current_target(CMD_CTX);
607 struct arm *arm = target_to_arm(target);
608 struct reg *regs;
609
610 if (!is_arm(arm)) {
611 command_print(CMD_CTX, "current target isn't an ARM");
612 return ERROR_FAIL;
613 }
614
615 if (target->state != TARGET_HALTED) {
616 command_print(CMD_CTX, "error: target must be halted for register accesses");
617 return ERROR_FAIL;
618 }
619
620 if (arm->core_type != ARM_MODE_ANY) {
621 command_print(CMD_CTX,
622 "Microcontroller Profile not supported - use standard reg cmd");
623 return ERROR_OK;
624 }
625
626 if (!is_arm_mode(arm->core_mode)) {
627 LOG_ERROR("not a valid arm core mode - communication failure?");
628 return ERROR_FAIL;
629 }
630
631 if (!arm->full_context) {
632 command_print(CMD_CTX, "error: target doesn't support %s",
633 CMD_NAME);
634 return ERROR_FAIL;
635 }
636
637 regs = arm->core_cache->reg_list;
638
639 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
640 const char *name;
641 char *sep = "\n";
642 char *shadow = "";
643
644 /* label this bank of registers (or shadows) */
645 switch (arm_mode_data[mode].psr) {
646 case ARM_MODE_SYS:
647 continue;
648 case ARM_MODE_USR:
649 name = "System and User";
650 sep = "";
651 break;
652 case ARM_MODE_MON:
653 if (arm->core_type != ARM_MODE_MON)
654 continue;
655 /* FALLTHROUGH */
656 default:
657 name = arm_mode_data[mode].name;
658 shadow = "shadow ";
659 break;
660 }
661 command_print(CMD_CTX, "%s%s mode %sregisters",
662 sep, name, shadow);
663
664 /* display N rows of up to 4 registers each */
665 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
666 char output[80];
667 int output_len = 0;
668
669 for (unsigned j = 0; j < 4; j++, i++) {
670 uint32_t value;
671 struct reg *reg = regs;
672
673 if (i >= arm_mode_data[mode].n_indices)
674 break;
675
676 reg += arm_mode_data[mode].indices[i];
677
678 /* REVISIT be smarter about faults... */
679 if (!reg->valid)
680 arm->full_context(target);
681
682 value = buf_get_u32(reg->value, 0, 32);
683 output_len += snprintf(output + output_len,
684 sizeof(output) - output_len,
685 "%8s: %8.8" PRIx32 " ",
686 reg->name, value);
687 }
688 command_print(CMD_CTX, "%s", output);
689 }
690 }
691
692 return ERROR_OK;
693 }
694
695 COMMAND_HANDLER(handle_armv4_5_core_state_command)
696 {
697 struct target *target = get_current_target(CMD_CTX);
698 struct arm *arm = target_to_arm(target);
699
700 if (!is_arm(arm)) {
701 command_print(CMD_CTX, "current target isn't an ARM");
702 return ERROR_FAIL;
703 }
704
705 if (arm->core_type == ARM_MODE_THREAD) {
706 /* armv7m not supported */
707 command_print(CMD_CTX, "Unsupported Command");
708 return ERROR_OK;
709 }
710
711 if (CMD_ARGC > 0) {
712 if (strcmp(CMD_ARGV[0], "arm") == 0)
713 arm->core_state = ARM_STATE_ARM;
714 if (strcmp(CMD_ARGV[0], "thumb") == 0)
715 arm->core_state = ARM_STATE_THUMB;
716 }
717
718 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
719
720 return ERROR_OK;
721 }
722
723 COMMAND_HANDLER(handle_arm_disassemble_command)
724 {
725 int retval = ERROR_OK;
726 struct target *target = get_current_target(CMD_CTX);
727
728 if (target == NULL) {
729 LOG_ERROR("No target selected");
730 return ERROR_FAIL;
731 }
732
733 struct arm *arm = target_to_arm(target);
734 uint32_t address;
735 int count = 1;
736 int thumb = 0;
737
738 if (!is_arm(arm)) {
739 command_print(CMD_CTX, "current target isn't an ARM");
740 return ERROR_FAIL;
741 }
742
743 if (arm->core_type == ARM_MODE_THREAD) {
744 /* armv7m is always thumb mode */
745 thumb = 1;
746 }
747
748 switch (CMD_ARGC) {
749 case 3:
750 if (strcmp(CMD_ARGV[2], "thumb") != 0)
751 goto usage;
752 thumb = 1;
753 /* FALL THROUGH */
754 case 2:
755 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
756 /* FALL THROUGH */
757 case 1:
758 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
759 if (address & 0x01) {
760 if (!thumb) {
761 command_print(CMD_CTX, "Disassemble as Thumb");
762 thumb = 1;
763 }
764 address &= ~1;
765 }
766 break;
767 default:
768 usage:
769 count = 0;
770 retval = ERROR_COMMAND_SYNTAX_ERROR;
771 }
772
773 while (count-- > 0) {
774 struct arm_instruction cur_instruction;
775
776 if (thumb) {
777 /* Always use Thumb2 disassembly for best handling
778 * of 32-bit BL/BLX, and to work with newer cores
779 * (some ARMv6, all ARMv7) that use Thumb2.
780 */
781 retval = thumb2_opcode(target, address,
782 &cur_instruction);
783 if (retval != ERROR_OK)
784 break;
785 } else {
786 uint32_t opcode;
787
788 retval = target_read_u32(target, address, &opcode);
789 if (retval != ERROR_OK)
790 break;
791 retval = arm_evaluate_opcode(opcode, address,
792 &cur_instruction) != ERROR_OK;
793 if (retval != ERROR_OK)
794 break;
795 }
796 command_print(CMD_CTX, "%s", cur_instruction.text);
797 address += cur_instruction.instruction_size;
798 }
799
800 return retval;
801 }
802
803 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
804 {
805 struct command_context *context;
806 struct target *target;
807 struct arm *arm;
808 int retval;
809
810 context = current_command_context(interp);
811 assert(context != NULL);
812
813 target = get_current_target(context);
814 if (target == NULL) {
815 LOG_ERROR("%s: no current target", __func__);
816 return JIM_ERR;
817 }
818 if (!target_was_examined(target)) {
819 LOG_ERROR("%s: not yet examined", target_name(target));
820 return JIM_ERR;
821 }
822 arm = target_to_arm(target);
823 if (!is_arm(arm)) {
824 LOG_ERROR("%s: not an ARM", target_name(target));
825 return JIM_ERR;
826 }
827
828 if ((argc < 6) || (argc > 7)) {
829 /* FIXME use the command name to verify # params... */
830 LOG_ERROR("%s: wrong number of arguments", __func__);
831 return JIM_ERR;
832 }
833
834 int cpnum;
835 uint32_t op1;
836 uint32_t op2;
837 uint32_t CRn;
838 uint32_t CRm;
839 uint32_t value;
840 long l;
841
842 /* NOTE: parameter sequence matches ARM instruction set usage:
843 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
844 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
845 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
846 */
847 retval = Jim_GetLong(interp, argv[1], &l);
848 if (retval != JIM_OK)
849 return retval;
850 if (l & ~0xf) {
851 LOG_ERROR("%s: %s %d out of range", __func__,
852 "coprocessor", (int) l);
853 return JIM_ERR;
854 }
855 cpnum = l;
856
857 retval = Jim_GetLong(interp, argv[2], &l);
858 if (retval != JIM_OK)
859 return retval;
860 if (l & ~0x7) {
861 LOG_ERROR("%s: %s %d out of range", __func__,
862 "op1", (int) l);
863 return JIM_ERR;
864 }
865 op1 = l;
866
867 retval = Jim_GetLong(interp, argv[3], &l);
868 if (retval != JIM_OK)
869 return retval;
870 if (l & ~0xf) {
871 LOG_ERROR("%s: %s %d out of range", __func__,
872 "CRn", (int) l);
873 return JIM_ERR;
874 }
875 CRn = l;
876
877 retval = Jim_GetLong(interp, argv[4], &l);
878 if (retval != JIM_OK)
879 return retval;
880 if (l & ~0xf) {
881 LOG_ERROR("%s: %s %d out of range", __func__,
882 "CRm", (int) l);
883 return JIM_ERR;
884 }
885 CRm = l;
886
887 retval = Jim_GetLong(interp, argv[5], &l);
888 if (retval != JIM_OK)
889 return retval;
890 if (l & ~0x7) {
891 LOG_ERROR("%s: %s %d out of range", __func__,
892 "op2", (int) l);
893 return JIM_ERR;
894 }
895 op2 = l;
896
897 value = 0;
898
899 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
900 * that could easily be a typo! Check both...
901 *
902 * FIXME change the call syntax here ... simplest to just pass
903 * the MRC() or MCR() instruction to be executed. That will also
904 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
905 * if that's ever needed.
906 */
907 if (argc == 7) {
908 retval = Jim_GetLong(interp, argv[6], &l);
909 if (retval != JIM_OK)
910 return retval;
911 value = l;
912
913 /* NOTE: parameters reordered! */
914 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
915 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
916 if (retval != ERROR_OK)
917 return JIM_ERR;
918 } else {
919 /* NOTE: parameters reordered! */
920 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
921 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
922 if (retval != ERROR_OK)
923 return JIM_ERR;
924
925 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
926 }
927
928 return JIM_OK;
929 }
930
931 COMMAND_HANDLER(handle_arm_semihosting_command)
932 {
933 struct target *target = get_current_target(CMD_CTX);
934
935 if (target == NULL) {
936 LOG_ERROR("No target selected");
937 return ERROR_FAIL;
938 }
939
940 struct arm *arm = target_to_arm(target);
941
942 if (!is_arm(arm)) {
943 command_print(CMD_CTX, "current target isn't an ARM");
944 return ERROR_FAIL;
945 }
946
947 if (!arm->setup_semihosting) {
948 command_print(CMD_CTX, "semihosting not supported for current target");
949 return ERROR_FAIL;
950 }
951
952 if (CMD_ARGC > 0) {
953 int semihosting;
954
955 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
956
957 if (!target_was_examined(target)) {
958 LOG_ERROR("Target not examined yet");
959 return ERROR_FAIL;
960 }
961
962 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
963 LOG_ERROR("Failed to Configure semihosting");
964 return ERROR_FAIL;
965 }
966
967 /* FIXME never let that "catch" be dropped! */
968 arm->is_semihosting = semihosting;
969 }
970
971 command_print(CMD_CTX, "semihosting is %s",
972 arm->is_semihosting
973 ? "enabled" : "disabled");
974
975 return ERROR_OK;
976 }
977
978 static const struct command_registration arm_exec_command_handlers[] = {
979 {
980 .name = "reg",
981 .handler = handle_armv4_5_reg_command,
982 .mode = COMMAND_EXEC,
983 .help = "display ARM core registers",
984 .usage = "",
985 },
986 {
987 .name = "core_state",
988 .handler = handle_armv4_5_core_state_command,
989 .mode = COMMAND_EXEC,
990 .usage = "['arm'|'thumb']",
991 .help = "display/change ARM core state",
992 },
993 {
994 .name = "disassemble",
995 .handler = handle_arm_disassemble_command,
996 .mode = COMMAND_EXEC,
997 .usage = "address [count ['thumb']]",
998 .help = "disassemble instructions ",
999 },
1000 {
1001 .name = "mcr",
1002 .mode = COMMAND_EXEC,
1003 .jim_handler = &jim_mcrmrc,
1004 .help = "write coprocessor register",
1005 .usage = "cpnum op1 CRn op2 CRm value",
1006 },
1007 {
1008 .name = "mrc",
1009 .jim_handler = &jim_mcrmrc,
1010 .help = "read coprocessor register",
1011 .usage = "cpnum op1 CRn op2 CRm",
1012 },
1013 {
1014 "semihosting",
1015 .handler = handle_arm_semihosting_command,
1016 .mode = COMMAND_EXEC,
1017 .usage = "['enable'|'disable']",
1018 .help = "activate support for semihosting operations",
1019 },
1020
1021 COMMAND_REGISTRATION_DONE
1022 };
1023 const struct command_registration arm_command_handlers[] = {
1024 {
1025 .name = "arm",
1026 .mode = COMMAND_ANY,
1027 .help = "ARM command group",
1028 .usage = "",
1029 .chain = arm_exec_command_handlers,
1030 },
1031 COMMAND_REGISTRATION_DONE
1032 };
1033
1034 int arm_get_gdb_reg_list(struct target *target,
1035 struct reg **reg_list[], int *reg_list_size)
1036 {
1037 struct arm *arm = target_to_arm(target);
1038 int i;
1039
1040 if (!is_arm_mode(arm->core_mode)) {
1041 LOG_ERROR("not a valid arm core mode - communication failure?");
1042 return ERROR_FAIL;
1043 }
1044
1045 *reg_list_size = 26;
1046 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1047
1048 for (i = 0; i < 16; i++)
1049 (*reg_list)[i] = arm_reg_current(arm, i);
1050
1051 for (i = 16; i < 24; i++)
1052 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1053
1054 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1055 (*reg_list)[25] = arm->cpsr;
1056
1057 return ERROR_OK;
1058 }
1059
1060 /* wait for execution to complete and check exit point */
1061 static int armv4_5_run_algorithm_completion(struct target *target,
1062 uint32_t exit_point,
1063 int timeout_ms,
1064 void *arch_info)
1065 {
1066 int retval;
1067 struct arm *arm = target_to_arm(target);
1068
1069 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1070 if (retval != ERROR_OK)
1071 return retval;
1072 if (target->state != TARGET_HALTED) {
1073 retval = target_halt(target);
1074 if (retval != ERROR_OK)
1075 return retval;
1076 retval = target_wait_state(target, TARGET_HALTED, 500);
1077 if (retval != ERROR_OK)
1078 return retval;
1079 return ERROR_TARGET_TIMEOUT;
1080 }
1081
1082 /* fast exit: ARMv5+ code can use BKPT */
1083 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1084 LOG_WARNING(
1085 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1086 buf_get_u32(arm->pc->value, 0, 32));
1087 return ERROR_TARGET_TIMEOUT;
1088 }
1089
1090 return ERROR_OK;
1091 }
1092
1093 int armv4_5_run_algorithm_inner(struct target *target,
1094 int num_mem_params, struct mem_param *mem_params,
1095 int num_reg_params, struct reg_param *reg_params,
1096 uint32_t entry_point, uint32_t exit_point,
1097 int timeout_ms, void *arch_info,
1098 int (*run_it)(struct target *target, uint32_t exit_point,
1099 int timeout_ms, void *arch_info))
1100 {
1101 struct arm *arm = target_to_arm(target);
1102 struct arm_algorithm *arm_algorithm_info = arch_info;
1103 enum arm_state core_state = arm->core_state;
1104 uint32_t context[17];
1105 uint32_t cpsr;
1106 int exit_breakpoint_size = 0;
1107 int i;
1108 int retval = ERROR_OK;
1109
1110 LOG_DEBUG("Running algorithm");
1111
1112 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1113 LOG_ERROR("current target isn't an ARMV4/5 target");
1114 return ERROR_TARGET_INVALID;
1115 }
1116
1117 if (target->state != TARGET_HALTED) {
1118 LOG_WARNING("target not halted");
1119 return ERROR_TARGET_NOT_HALTED;
1120 }
1121
1122 if (!is_arm_mode(arm->core_mode)) {
1123 LOG_ERROR("not a valid arm core mode - communication failure?");
1124 return ERROR_FAIL;
1125 }
1126
1127 /* armv5 and later can terminate with BKPT instruction; less overhead */
1128 if (!exit_point && arm->is_armv4) {
1129 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1130 return ERROR_FAIL;
1131 }
1132
1133 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1134 * they'll be restored later.
1135 */
1136 for (i = 0; i <= 16; i++) {
1137 struct reg *r;
1138
1139 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1140 arm_algorithm_info->core_mode, i);
1141 if (!r->valid)
1142 arm->read_core_reg(target, r, i,
1143 arm_algorithm_info->core_mode);
1144 context[i] = buf_get_u32(r->value, 0, 32);
1145 }
1146 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1147
1148 for (i = 0; i < num_mem_params; i++) {
1149 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1150 mem_params[i].value);
1151 if (retval != ERROR_OK)
1152 return retval;
1153 }
1154
1155 for (i = 0; i < num_reg_params; i++) {
1156 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1157 if (!reg) {
1158 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1159 return ERROR_COMMAND_SYNTAX_ERROR;
1160 }
1161
1162 if (reg->size != reg_params[i].size) {
1163 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1164 reg_params[i].reg_name);
1165 return ERROR_COMMAND_SYNTAX_ERROR;
1166 }
1167
1168 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1169 if (retval != ERROR_OK)
1170 return retval;
1171 }
1172
1173 arm->core_state = arm_algorithm_info->core_state;
1174 if (arm->core_state == ARM_STATE_ARM)
1175 exit_breakpoint_size = 4;
1176 else if (arm->core_state == ARM_STATE_THUMB)
1177 exit_breakpoint_size = 2;
1178 else {
1179 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1180 return ERROR_COMMAND_SYNTAX_ERROR;
1181 }
1182
1183 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1184 LOG_DEBUG("setting core_mode: 0x%2.2x",
1185 arm_algorithm_info->core_mode);
1186 buf_set_u32(arm->cpsr->value, 0, 5,
1187 arm_algorithm_info->core_mode);
1188 arm->cpsr->dirty = 1;
1189 arm->cpsr->valid = 1;
1190 }
1191
1192 /* terminate using a hardware or (ARMv5+) software breakpoint */
1193 if (exit_point) {
1194 retval = breakpoint_add(target, exit_point,
1195 exit_breakpoint_size, BKPT_HARD);
1196 if (retval != ERROR_OK) {
1197 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1198 return ERROR_TARGET_FAILURE;
1199 }
1200 }
1201
1202 retval = target_resume(target, 0, entry_point, 1, 1);
1203 if (retval != ERROR_OK)
1204 return retval;
1205 retval = run_it(target, exit_point, timeout_ms, arch_info);
1206
1207 if (exit_point)
1208 breakpoint_remove(target, exit_point);
1209
1210 if (retval != ERROR_OK)
1211 return retval;
1212
1213 for (i = 0; i < num_mem_params; i++) {
1214 if (mem_params[i].direction != PARAM_OUT) {
1215 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1216 mem_params[i].size,
1217 mem_params[i].value);
1218 if (retvaltemp != ERROR_OK)
1219 retval = retvaltemp;
1220 }
1221 }
1222
1223 for (i = 0; i < num_reg_params; i++) {
1224 if (reg_params[i].direction != PARAM_OUT) {
1225
1226 struct reg *reg = register_get_by_name(arm->core_cache,
1227 reg_params[i].reg_name,
1228 0);
1229 if (!reg) {
1230 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1231 retval = ERROR_COMMAND_SYNTAX_ERROR;
1232 continue;
1233 }
1234
1235 if (reg->size != reg_params[i].size) {
1236 LOG_ERROR(
1237 "BUG: register '%s' size doesn't match reg_params[i].size",
1238 reg_params[i].reg_name);
1239 retval = ERROR_COMMAND_SYNTAX_ERROR;
1240 continue;
1241 }
1242
1243 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1244 }
1245 }
1246
1247 /* restore everything we saved before (17 or 18 registers) */
1248 for (i = 0; i <= 16; i++) {
1249 uint32_t regvalue;
1250 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1251 arm_algorithm_info->core_mode, i).value, 0, 32);
1252 if (regvalue != context[i]) {
1253 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1254 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1255 arm_algorithm_info->core_mode, i).name, context[i]);
1256 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1257 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1258 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1259 i).valid = 1;
1260 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1261 i).dirty = 1;
1262 }
1263 }
1264
1265 arm_set_cpsr(arm, cpsr);
1266 arm->cpsr->dirty = 1;
1267
1268 arm->core_state = core_state;
1269
1270 return retval;
1271 }
1272
1273 int armv4_5_run_algorithm(struct target *target,
1274 int num_mem_params,
1275 struct mem_param *mem_params,
1276 int num_reg_params,
1277 struct reg_param *reg_params,
1278 uint32_t entry_point,
1279 uint32_t exit_point,
1280 int timeout_ms,
1281 void *arch_info)
1282 {
1283 return armv4_5_run_algorithm_inner(target,
1284 num_mem_params,
1285 mem_params,
1286 num_reg_params,
1287 reg_params,
1288 entry_point,
1289 exit_point,
1290 timeout_ms,
1291 arch_info,
1292 armv4_5_run_algorithm_completion);
1293 }
1294
1295 /**
1296 * Runs ARM code in the target to calculate a CRC32 checksum.
1297 *
1298 */
1299 int arm_checksum_memory(struct target *target,
1300 uint32_t address, uint32_t count, uint32_t *checksum)
1301 {
1302 struct working_area *crc_algorithm;
1303 struct arm_algorithm arm_algo;
1304 struct arm *arm = target_to_arm(target);
1305 struct reg_param reg_params[2];
1306 int retval;
1307 uint32_t i;
1308 uint32_t exit_var = 0;
1309
1310 /* see contrib/loaders/checksum/armv4_5_crc.s for src */
1311
1312 static const uint32_t arm_crc_code[] = {
1313 0xE1A02000, /* mov r2, r0 */
1314 0xE3E00000, /* mov r0, #0xffffffff */
1315 0xE1A03001, /* mov r3, r1 */
1316 0xE3A04000, /* mov r4, #0 */
1317 0xEA00000B, /* b ncomp */
1318 /* nbyte: */
1319 0xE7D21004, /* ldrb r1, [r2, r4] */
1320 0xE59F7030, /* ldr r7, CRC32XOR */
1321 0xE0200C01, /* eor r0, r0, r1, asl 24 */
1322 0xE3A05000, /* mov r5, #0 */
1323 /* loop: */
1324 0xE3500000, /* cmp r0, #0 */
1325 0xE1A06080, /* mov r6, r0, asl #1 */
1326 0xE2855001, /* add r5, r5, #1 */
1327 0xE1A00006, /* mov r0, r6 */
1328 0xB0260007, /* eorlt r0, r6, r7 */
1329 0xE3550008, /* cmp r5, #8 */
1330 0x1AFFFFF8, /* bne loop */
1331 0xE2844001, /* add r4, r4, #1 */
1332 /* ncomp: */
1333 0xE1540003, /* cmp r4, r3 */
1334 0x1AFFFFF1, /* bne nbyte */
1335 /* end: */
1336 0xe1200070, /* bkpt #0 */
1337 /* CRC32XOR: */
1338 0x04C11DB7 /* .word 0x04C11DB7 */
1339 };
1340
1341 retval = target_alloc_working_area(target,
1342 sizeof(arm_crc_code), &crc_algorithm);
1343 if (retval != ERROR_OK)
1344 return retval;
1345
1346 /* convert code into a buffer in target endianness */
1347 for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
1348 retval = target_write_u32(target,
1349 crc_algorithm->address + i * sizeof(uint32_t),
1350 arm_crc_code[i]);
1351 if (retval != ERROR_OK)
1352 return retval;
1353 }
1354
1355 arm_algo.common_magic = ARM_COMMON_MAGIC;
1356 arm_algo.core_mode = ARM_MODE_SVC;
1357 arm_algo.core_state = ARM_STATE_ARM;
1358
1359 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1360 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1361
1362 buf_set_u32(reg_params[0].value, 0, 32, address);
1363 buf_set_u32(reg_params[1].value, 0, 32, count);
1364
1365 /* 20 second timeout/megabyte */
1366 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1367
1368 /* armv4 must exit using a hardware breakpoint */
1369 if (arm->is_armv4)
1370 exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
1371
1372 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1373 crc_algorithm->address,
1374 exit_var,
1375 timeout, &arm_algo);
1376 if (retval != ERROR_OK) {
1377 LOG_ERROR("error executing ARM crc algorithm");
1378 destroy_reg_param(&reg_params[0]);
1379 destroy_reg_param(&reg_params[1]);
1380 target_free_working_area(target, crc_algorithm);
1381 return retval;
1382 }
1383
1384 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1385
1386 destroy_reg_param(&reg_params[0]);
1387 destroy_reg_param(&reg_params[1]);
1388
1389 target_free_working_area(target, crc_algorithm);
1390
1391 return ERROR_OK;
1392 }
1393
1394 /**
1395 * Runs ARM code in the target to check whether a memory block holds
1396 * all ones. NOR flash which has been erased, and thus may be written,
1397 * holds all ones.
1398 *
1399 */
1400 int arm_blank_check_memory(struct target *target,
1401 uint32_t address, uint32_t count, uint32_t *blank)
1402 {
1403 struct working_area *check_algorithm;
1404 struct reg_param reg_params[3];
1405 struct arm_algorithm arm_algo;
1406 struct arm *arm = target_to_arm(target);
1407 int retval;
1408 uint32_t i;
1409 uint32_t exit_var = 0;
1410
1411 /* see contrib/loaders/erase_check/armv4_5_erase_check.s for src */
1412
1413 static const uint32_t check_code[] = {
1414 /* loop: */
1415 0xe4d03001, /* ldrb r3, [r0], #1 */
1416 0xe0022003, /* and r2, r2, r3 */
1417 0xe2511001, /* subs r1, r1, #1 */
1418 0x1afffffb, /* bne loop */
1419 /* end: */
1420 0xe1200070, /* bkpt #0 */
1421 };
1422
1423 /* make sure we have a working area */
1424 retval = target_alloc_working_area(target,
1425 sizeof(check_code), &check_algorithm);
1426 if (retval != ERROR_OK)
1427 return retval;
1428
1429 /* convert code into a buffer in target endianness */
1430 for (i = 0; i < ARRAY_SIZE(check_code); i++) {
1431 retval = target_write_u32(target,
1432 check_algorithm->address
1433 + i * sizeof(uint32_t),
1434 check_code[i]);
1435 if (retval != ERROR_OK)
1436 return retval;
1437 }
1438
1439 arm_algo.common_magic = ARM_COMMON_MAGIC;
1440 arm_algo.core_mode = ARM_MODE_SVC;
1441 arm_algo.core_state = ARM_STATE_ARM;
1442
1443 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1444 buf_set_u32(reg_params[0].value, 0, 32, address);
1445
1446 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1447 buf_set_u32(reg_params[1].value, 0, 32, count);
1448
1449 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1450 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1451
1452 /* armv4 must exit using a hardware breakpoint */
1453 if (arm->is_armv4)
1454 exit_var = check_algorithm->address + sizeof(check_code) - 4;
1455
1456 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1457 check_algorithm->address,
1458 exit_var,
1459 10000, &arm_algo);
1460 if (retval != ERROR_OK) {
1461 destroy_reg_param(&reg_params[0]);
1462 destroy_reg_param(&reg_params[1]);
1463 destroy_reg_param(&reg_params[2]);
1464 target_free_working_area(target, check_algorithm);
1465 return retval;
1466 }
1467
1468 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1469
1470 destroy_reg_param(&reg_params[0]);
1471 destroy_reg_param(&reg_params[1]);
1472 destroy_reg_param(&reg_params[2]);
1473
1474 target_free_working_area(target, check_algorithm);
1475
1476 return ERROR_OK;
1477 }
1478
1479 static int arm_full_context(struct target *target)
1480 {
1481 struct arm *arm = target_to_arm(target);
1482 unsigned num_regs = arm->core_cache->num_regs;
1483 struct reg *reg = arm->core_cache->reg_list;
1484 int retval = ERROR_OK;
1485
1486 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1487 if (reg->valid)
1488 continue;
1489 retval = armv4_5_get_core_reg(reg);
1490 }
1491 return retval;
1492 }
1493
1494 static int arm_default_mrc(struct target *target, int cpnum,
1495 uint32_t op1, uint32_t op2,
1496 uint32_t CRn, uint32_t CRm,
1497 uint32_t *value)
1498 {
1499 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1500 return ERROR_FAIL;
1501 }
1502
1503 static int arm_default_mcr(struct target *target, int cpnum,
1504 uint32_t op1, uint32_t op2,
1505 uint32_t CRn, uint32_t CRm,
1506 uint32_t value)
1507 {
1508 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1509 return ERROR_FAIL;
1510 }
1511
1512 int arm_init_arch_info(struct target *target, struct arm *arm)
1513 {
1514 target->arch_info = arm;
1515 arm->target = target;
1516
1517 arm->common_magic = ARM_COMMON_MAGIC;
1518
1519 /* core_type may be overridden by subtype logic */
1520 if (arm->core_type != ARM_MODE_THREAD) {
1521 arm->core_type = ARM_MODE_ANY;
1522 arm_set_cpsr(arm, ARM_MODE_USR);
1523 }
1524
1525 /* default full_context() has no core-specific optimizations */
1526 if (!arm->full_context && arm->read_core_reg)
1527 arm->full_context = arm_full_context;
1528
1529 if (!arm->mrc)
1530 arm->mrc = arm_default_mrc;
1531 if (!arm->mcr)
1532 arm->mcr = arm_default_mcr;
1533
1534 return ERROR_OK;
1535 }
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