Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
armv7m: add FPU registers support
[openocd.git] / src / target / armv4_5.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "arm.h"
32 #include "armv4_5.h"
33 #include "arm_jtag.h"
34 #include "breakpoints.h"
35 #include "arm_disassembler.h"
36 #include <helper/binarybuffer.h>
37 #include "algorithm.h"
38 #include "register.h"
39
40 /* offsets into armv4_5 core register cache */
41 enum {
42 /* ARMV4_5_CPSR = 31, */
43 ARMV4_5_SPSR_FIQ = 32,
44 ARMV4_5_SPSR_IRQ = 33,
45 ARMV4_5_SPSR_SVC = 34,
46 ARMV4_5_SPSR_ABT = 35,
47 ARMV4_5_SPSR_UND = 36,
48 ARM_SPSR_MON = 41,
49 };
50
51 static const uint8_t arm_usr_indices[17] = {
52 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
53 };
54
55 static const uint8_t arm_fiq_indices[8] = {
56 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
57 };
58
59 static const uint8_t arm_irq_indices[3] = {
60 23, 24, ARMV4_5_SPSR_IRQ,
61 };
62
63 static const uint8_t arm_svc_indices[3] = {
64 25, 26, ARMV4_5_SPSR_SVC,
65 };
66
67 static const uint8_t arm_abt_indices[3] = {
68 27, 28, ARMV4_5_SPSR_ABT,
69 };
70
71 static const uint8_t arm_und_indices[3] = {
72 29, 30, ARMV4_5_SPSR_UND,
73 };
74
75 static const uint8_t arm_mon_indices[3] = {
76 39, 40, ARM_SPSR_MON,
77 };
78
79 static const struct {
80 const char *name;
81 unsigned short psr;
82 /* For user and system modes, these list indices for all registers.
83 * otherwise they're just indices for the shadow registers and SPSR.
84 */
85 unsigned short n_indices;
86 const uint8_t *indices;
87 } arm_mode_data[] = {
88 /* Seven modes are standard from ARM7 on. "System" and "User" share
89 * the same registers; other modes shadow from 3 to 8 registers.
90 */
91 {
92 .name = "User",
93 .psr = ARM_MODE_USR,
94 .n_indices = ARRAY_SIZE(arm_usr_indices),
95 .indices = arm_usr_indices,
96 },
97 {
98 .name = "FIQ",
99 .psr = ARM_MODE_FIQ,
100 .n_indices = ARRAY_SIZE(arm_fiq_indices),
101 .indices = arm_fiq_indices,
102 },
103 {
104 .name = "Supervisor",
105 .psr = ARM_MODE_SVC,
106 .n_indices = ARRAY_SIZE(arm_svc_indices),
107 .indices = arm_svc_indices,
108 },
109 {
110 .name = "Abort",
111 .psr = ARM_MODE_ABT,
112 .n_indices = ARRAY_SIZE(arm_abt_indices),
113 .indices = arm_abt_indices,
114 },
115 {
116 .name = "IRQ",
117 .psr = ARM_MODE_IRQ,
118 .n_indices = ARRAY_SIZE(arm_irq_indices),
119 .indices = arm_irq_indices,
120 },
121 {
122 .name = "Undefined instruction",
123 .psr = ARM_MODE_UND,
124 .n_indices = ARRAY_SIZE(arm_und_indices),
125 .indices = arm_und_indices,
126 },
127 {
128 .name = "System",
129 .psr = ARM_MODE_SYS,
130 .n_indices = ARRAY_SIZE(arm_usr_indices),
131 .indices = arm_usr_indices,
132 },
133 /* TrustZone "Security Extensions" add a secure monitor mode.
134 * This is distinct from a "debug monitor" which can support
135 * non-halting debug, in conjunction with some debuggers.
136 */
137 {
138 .name = "Secure Monitor",
139 .psr = ARM_MODE_MON,
140 .n_indices = ARRAY_SIZE(arm_mon_indices),
141 .indices = arm_mon_indices,
142 },
143
144 /* These special modes are currently only supported
145 * by ARMv6M and ARMv7M profiles */
146 {
147 .name = "Thread",
148 .psr = ARM_MODE_THREAD,
149 },
150 {
151 .name = "Thread (User)",
152 .psr = ARM_MODE_USER_THREAD,
153 },
154 {
155 .name = "Handler",
156 .psr = ARM_MODE_HANDLER,
157 },
158 };
159
160 /** Map PSR mode bits to the name of an ARM processor operating mode. */
161 const char *arm_mode_name(unsigned psr_mode)
162 {
163 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
164 if (arm_mode_data[i].psr == psr_mode)
165 return arm_mode_data[i].name;
166 }
167 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
168 return "UNRECOGNIZED";
169 }
170
171 /** Return true iff the parameter denotes a valid ARM processor mode. */
172 bool is_arm_mode(unsigned psr_mode)
173 {
174 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
175 if (arm_mode_data[i].psr == psr_mode)
176 return true;
177 }
178 return false;
179 }
180
181 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
182 int arm_mode_to_number(enum arm_mode mode)
183 {
184 switch (mode) {
185 case ARM_MODE_ANY:
186 /* map MODE_ANY to user mode */
187 case ARM_MODE_USR:
188 return 0;
189 case ARM_MODE_FIQ:
190 return 1;
191 case ARM_MODE_IRQ:
192 return 2;
193 case ARM_MODE_SVC:
194 return 3;
195 case ARM_MODE_ABT:
196 return 4;
197 case ARM_MODE_UND:
198 return 5;
199 case ARM_MODE_SYS:
200 return 6;
201 case ARM_MODE_MON:
202 return 7;
203 default:
204 LOG_ERROR("invalid mode value encountered %d", mode);
205 return -1;
206 }
207 }
208
209 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
210 enum arm_mode armv4_5_number_to_mode(int number)
211 {
212 switch (number) {
213 case 0:
214 return ARM_MODE_USR;
215 case 1:
216 return ARM_MODE_FIQ;
217 case 2:
218 return ARM_MODE_IRQ;
219 case 3:
220 return ARM_MODE_SVC;
221 case 4:
222 return ARM_MODE_ABT;
223 case 5:
224 return ARM_MODE_UND;
225 case 6:
226 return ARM_MODE_SYS;
227 case 7:
228 return ARM_MODE_MON;
229 default:
230 LOG_ERROR("mode index out of bounds %d", number);
231 return ARM_MODE_ANY;
232 }
233 }
234
235 static const char *arm_state_strings[] = {
236 "ARM", "Thumb", "Jazelle", "ThumbEE",
237 };
238
239 /* Templates for ARM core registers.
240 *
241 * NOTE: offsets in this table are coupled to the arm_mode_data
242 * table above, the armv4_5_core_reg_map array below, and also to
243 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
244 */
245 static const struct {
246 /* The name is used for e.g. the "regs" command. */
247 const char *name;
248
249 /* The {cookie, mode} tuple uniquely identifies one register.
250 * In a given mode, cookies 0..15 map to registers R0..R15,
251 * with R13..R15 usually called SP, LR, PC.
252 *
253 * MODE_ANY is used as *input* to the mapping, and indicates
254 * various special cases (sigh) and errors.
255 *
256 * Cookie 16 is (currently) confusing, since it indicates
257 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
258 * (Exception modes have both CPSR and SPSR registers ...)
259 */
260 unsigned cookie;
261 unsigned gdb_index;
262 enum arm_mode mode;
263 } arm_core_regs[] = {
264 /* IMPORTANT: we guarantee that the first eight cached registers
265 * correspond to r0..r7, and the fifteenth to PC, so that callers
266 * don't need to map them.
267 */
268 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
269 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
270 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
271 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
272 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
273 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
274 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
275 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
276
277 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
278 * them as MODE_ANY creates special cases. (ANY means
279 * "not mapped" elsewhere; here it's "everything but FIQ".)
280 */
281 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
282 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
283 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
284 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
285 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
286
287 /* Historical GDB mapping of indices:
288 * - 13-14 are sp and lr, but banked counterparts are used
289 * - 16-24 are left for deprecated 8 FPA + 1 FPS
290 * - 25 is the cpsr
291 */
292
293 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
294 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
295 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
296
297 /* guaranteed to be at index 15 */
298 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
299 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
300 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
301 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
302 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
303 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
304
305 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
306 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
307
308 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
309 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
310
311 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
312 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
313
314 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
315 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
316
317 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
318 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
319
320 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
321 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
322 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
323 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
324 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
325 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
326
327 /* These are only used for GDB target description, banked registers are accessed instead */
328 { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
329 { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
330
331 /* These exist only when the Security Extension (TrustZone) is present */
332 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
333 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
334 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
335
336 };
337
338 /* map core mode (USR, FIQ, ...) and register number to
339 * indices into the register cache
340 */
341 const int armv4_5_core_reg_map[8][17] = {
342 { /* USR */
343 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
344 },
345 { /* FIQ (8 shadows of USR, vs normal 3) */
346 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
347 },
348 { /* IRQ */
349 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
350 },
351 { /* SVC */
352 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
353 },
354 { /* ABT */
355 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
356 },
357 { /* UND */
358 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
359 },
360 { /* SYS (same registers as USR) */
361 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
362 },
363 { /* MON */
364 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
365 }
366 };
367
368 /**
369 * Configures host-side ARM records to reflect the specified CPSR.
370 * Later, code can use arm_reg_current() to map register numbers
371 * according to how they are exposed by this mode.
372 */
373 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
374 {
375 enum arm_mode mode = cpsr & 0x1f;
376 int num;
377
378 /* NOTE: this may be called very early, before the register
379 * cache is set up. We can't defend against many errors, in
380 * particular against CPSRs that aren't valid *here* ...
381 */
382 if (arm->cpsr) {
383 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
384 arm->cpsr->valid = 1;
385 arm->cpsr->dirty = 0;
386 }
387
388 arm->core_mode = mode;
389
390 /* mode_to_number() warned; set up a somewhat-sane mapping */
391 num = arm_mode_to_number(mode);
392 if (num < 0) {
393 mode = ARM_MODE_USR;
394 num = 0;
395 }
396
397 arm->map = &armv4_5_core_reg_map[num][0];
398 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
399 ? NULL
400 : arm->core_cache->reg_list + arm->map[16];
401
402 /* Older ARMs won't have the J bit */
403 enum arm_state state;
404
405 if (cpsr & (1 << 5)) { /* T */
406 if (cpsr & (1 << 24)) { /* J */
407 LOG_WARNING("ThumbEE -- incomplete support");
408 state = ARM_STATE_THUMB_EE;
409 } else
410 state = ARM_STATE_THUMB;
411 } else {
412 if (cpsr & (1 << 24)) { /* J */
413 LOG_ERROR("Jazelle state handling is BROKEN!");
414 state = ARM_STATE_JAZELLE;
415 } else
416 state = ARM_STATE_ARM;
417 }
418 arm->core_state = state;
419
420 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
421 arm_mode_name(mode),
422 arm_state_strings[arm->core_state]);
423 }
424
425 /**
426 * Returns handle to the register currently mapped to a given number.
427 * Someone must have called arm_set_cpsr() before.
428 *
429 * \param arm This core's state and registers are used.
430 * \param regnum From 0..15 corresponding to R0..R14 and PC.
431 * Note that R0..R7 don't require mapping; you may access those
432 * as the first eight entries in the register cache. Likewise
433 * R15 (PC) doesn't need mapping; you may also access it directly.
434 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
435 * CPSR (arm->cpsr) is also not mapped.
436 */
437 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
438 {
439 struct reg *r;
440
441 if (regnum > 16)
442 return NULL;
443
444 if (!arm->map) {
445 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
446 r = arm->core_cache->reg_list + regnum;
447 } else
448 r = arm->core_cache->reg_list + arm->map[regnum];
449
450 /* e.g. invalid CPSR said "secure monitor" mode on a core
451 * that doesn't support it...
452 */
453 if (!r) {
454 LOG_ERROR("Invalid CPSR mode");
455 r = arm->core_cache->reg_list + regnum;
456 }
457
458 return r;
459 }
460
461 static const uint8_t arm_gdb_dummy_fp_value[12];
462
463 static struct reg_feature arm_gdb_dummy_fp_features = {
464 .name = "net.sourceforge.openocd.fake_fpa"
465 };
466
467 /**
468 * Dummy FPA registers are required to support GDB on ARM.
469 * Register packets require eight obsolete FPA register values.
470 * Modern ARM cores use Vector Floating Point (VFP), if they
471 * have any floating point support. VFP is not FPA-compatible.
472 */
473 struct reg arm_gdb_dummy_fp_reg = {
474 .name = "GDB dummy FPA register",
475 .value = (uint8_t *) arm_gdb_dummy_fp_value,
476 .valid = 1,
477 .size = 96,
478 .exist = false,
479 .number = 16,
480 .feature = &arm_gdb_dummy_fp_features,
481 .group = "fake_fpa",
482 };
483
484 static const uint8_t arm_gdb_dummy_fps_value[4];
485
486 /**
487 * Dummy FPA status registers are required to support GDB on ARM.
488 * Register packets require an obsolete FPA status register.
489 */
490 struct reg arm_gdb_dummy_fps_reg = {
491 .name = "GDB dummy FPA status register",
492 .value = (uint8_t *) arm_gdb_dummy_fps_value,
493 .valid = 1,
494 .size = 32,
495 .exist = false,
496 .number = 24,
497 .feature = &arm_gdb_dummy_fp_features,
498 .group = "fake_fpa",
499 };
500
501 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
502
503 static void arm_gdb_dummy_init(void)
504 {
505 register_init_dummy(&arm_gdb_dummy_fp_reg);
506 register_init_dummy(&arm_gdb_dummy_fps_reg);
507 }
508
509 static int armv4_5_get_core_reg(struct reg *reg)
510 {
511 int retval;
512 struct arm_reg *reg_arch_info = reg->arch_info;
513 struct target *target = reg_arch_info->target;
514
515 if (target->state != TARGET_HALTED) {
516 LOG_ERROR("Target not halted");
517 return ERROR_TARGET_NOT_HALTED;
518 }
519
520 retval = reg_arch_info->arm->read_core_reg(target, reg,
521 reg_arch_info->num, reg_arch_info->mode);
522 if (retval == ERROR_OK) {
523 reg->valid = 1;
524 reg->dirty = 0;
525 }
526
527 return retval;
528 }
529
530 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
531 {
532 struct arm_reg *reg_arch_info = reg->arch_info;
533 struct target *target = reg_arch_info->target;
534 struct arm *armv4_5_target = target_to_arm(target);
535 uint32_t value = buf_get_u32(buf, 0, 32);
536
537 if (target->state != TARGET_HALTED) {
538 LOG_ERROR("Target not halted");
539 return ERROR_TARGET_NOT_HALTED;
540 }
541
542 /* Except for CPSR, the "reg" command exposes a writeback model
543 * for the register cache.
544 */
545 if (reg == armv4_5_target->cpsr) {
546 arm_set_cpsr(armv4_5_target, value);
547
548 /* Older cores need help to be in ARM mode during halt
549 * mode debug, so we clear the J and T bits if we flush.
550 * For newer cores (v6/v7a/v7r) we don't need that, but
551 * it won't hurt since CPSR is always flushed anyway.
552 */
553 if (armv4_5_target->core_mode !=
554 (enum arm_mode)(value & 0x1f)) {
555 LOG_DEBUG("changing ARM core mode to '%s'",
556 arm_mode_name(value & 0x1f));
557 value &= ~((1 << 24) | (1 << 5));
558 uint8_t t[4];
559 buf_set_u32(t, 0, 32, value);
560 armv4_5_target->write_core_reg(target, reg,
561 16, ARM_MODE_ANY, t);
562 }
563 } else {
564 buf_set_u32(reg->value, 0, 32, value);
565 reg->valid = 1;
566 }
567 reg->dirty = 1;
568
569 return ERROR_OK;
570 }
571
572 static const struct reg_arch_type arm_reg_type = {
573 .get = armv4_5_get_core_reg,
574 .set = armv4_5_set_core_reg,
575 };
576
577 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
578 {
579 int num_regs = ARRAY_SIZE(arm_core_regs);
580 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
581 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
582 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
583 int i;
584
585 if (!cache || !reg_list || !reg_arch_info) {
586 free(cache);
587 free(reg_list);
588 free(reg_arch_info);
589 return NULL;
590 }
591
592 cache->name = "ARM registers";
593 cache->next = NULL;
594 cache->reg_list = reg_list;
595 cache->num_regs = 0;
596
597 for (i = 0; i < num_regs; i++) {
598 /* Skip registers this core doesn't expose */
599 if (arm_core_regs[i].mode == ARM_MODE_MON
600 && arm->core_type != ARM_MODE_MON)
601 continue;
602
603 /* REVISIT handle Cortex-M, which only shadows R13/SP */
604
605 reg_arch_info[i].num = arm_core_regs[i].cookie;
606 reg_arch_info[i].mode = arm_core_regs[i].mode;
607 reg_arch_info[i].target = target;
608 reg_arch_info[i].arm = arm;
609
610 reg_list[i].name = arm_core_regs[i].name;
611 reg_list[i].number = arm_core_regs[i].gdb_index;
612 reg_list[i].size = 32;
613 reg_list[i].value = reg_arch_info[i].value;
614 reg_list[i].type = &arm_reg_type;
615 reg_list[i].arch_info = &reg_arch_info[i];
616 reg_list[i].exist = true;
617
618 /* This really depends on the calling convention in use */
619 reg_list[i].caller_save = false;
620
621 /* Registers data type, as used by GDB target description */
622 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
623 switch (arm_core_regs[i].cookie) {
624 case 13:
625 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
626 break;
627 case 14:
628 case 15:
629 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
630 break;
631 default:
632 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
633 break;
634 }
635
636 /* let GDB shows banked registers only in "info all-reg" */
637 reg_list[i].feature = malloc(sizeof(struct reg_feature));
638 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
639 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
640 reg_list[i].group = "general";
641 } else {
642 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
643 reg_list[i].group = "banked";
644 }
645
646 cache->num_regs++;
647 }
648
649 arm->pc = reg_list + 15;
650 arm->cpsr = reg_list + ARMV4_5_CPSR;
651 arm->core_cache = cache;
652 return cache;
653 }
654
655 int arm_arch_state(struct target *target)
656 {
657 struct arm *arm = target_to_arm(target);
658
659 if (arm->common_magic != ARM_COMMON_MAGIC) {
660 LOG_ERROR("BUG: called for a non-ARM target");
661 return ERROR_FAIL;
662 }
663
664 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
665 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
666 arm_state_strings[arm->core_state],
667 debug_reason_name(target),
668 arm_mode_name(arm->core_mode),
669 buf_get_u32(arm->cpsr->value, 0, 32),
670 buf_get_u32(arm->pc->value, 0, 32),
671 arm->is_semihosting ? ", semihosting" : "");
672
673 return ERROR_OK;
674 }
675
676 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
677 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
678
679 COMMAND_HANDLER(handle_armv4_5_reg_command)
680 {
681 struct target *target = get_current_target(CMD_CTX);
682 struct arm *arm = target_to_arm(target);
683 struct reg *regs;
684
685 if (!is_arm(arm)) {
686 command_print(CMD_CTX, "current target isn't an ARM");
687 return ERROR_FAIL;
688 }
689
690 if (target->state != TARGET_HALTED) {
691 command_print(CMD_CTX, "error: target must be halted for register accesses");
692 return ERROR_FAIL;
693 }
694
695 if (arm->core_type != ARM_MODE_ANY) {
696 command_print(CMD_CTX,
697 "Microcontroller Profile not supported - use standard reg cmd");
698 return ERROR_OK;
699 }
700
701 if (!is_arm_mode(arm->core_mode)) {
702 LOG_ERROR("not a valid arm core mode - communication failure?");
703 return ERROR_FAIL;
704 }
705
706 if (!arm->full_context) {
707 command_print(CMD_CTX, "error: target doesn't support %s",
708 CMD_NAME);
709 return ERROR_FAIL;
710 }
711
712 regs = arm->core_cache->reg_list;
713
714 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
715 const char *name;
716 char *sep = "\n";
717 char *shadow = "";
718
719 /* label this bank of registers (or shadows) */
720 switch (arm_mode_data[mode].psr) {
721 case ARM_MODE_SYS:
722 continue;
723 case ARM_MODE_USR:
724 name = "System and User";
725 sep = "";
726 break;
727 case ARM_MODE_MON:
728 if (arm->core_type != ARM_MODE_MON)
729 continue;
730 /* FALLTHROUGH */
731 default:
732 name = arm_mode_data[mode].name;
733 shadow = "shadow ";
734 break;
735 }
736 command_print(CMD_CTX, "%s%s mode %sregisters",
737 sep, name, shadow);
738
739 /* display N rows of up to 4 registers each */
740 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
741 char output[80];
742 int output_len = 0;
743
744 for (unsigned j = 0; j < 4; j++, i++) {
745 uint32_t value;
746 struct reg *reg = regs;
747
748 if (i >= arm_mode_data[mode].n_indices)
749 break;
750
751 reg += arm_mode_data[mode].indices[i];
752
753 /* REVISIT be smarter about faults... */
754 if (!reg->valid)
755 arm->full_context(target);
756
757 value = buf_get_u32(reg->value, 0, 32);
758 output_len += snprintf(output + output_len,
759 sizeof(output) - output_len,
760 "%8s: %8.8" PRIx32 " ",
761 reg->name, value);
762 }
763 command_print(CMD_CTX, "%s", output);
764 }
765 }
766
767 return ERROR_OK;
768 }
769
770 COMMAND_HANDLER(handle_armv4_5_core_state_command)
771 {
772 struct target *target = get_current_target(CMD_CTX);
773 struct arm *arm = target_to_arm(target);
774
775 if (!is_arm(arm)) {
776 command_print(CMD_CTX, "current target isn't an ARM");
777 return ERROR_FAIL;
778 }
779
780 if (arm->core_type == ARM_MODE_THREAD) {
781 /* armv7m not supported */
782 command_print(CMD_CTX, "Unsupported Command");
783 return ERROR_OK;
784 }
785
786 if (CMD_ARGC > 0) {
787 if (strcmp(CMD_ARGV[0], "arm") == 0)
788 arm->core_state = ARM_STATE_ARM;
789 if (strcmp(CMD_ARGV[0], "thumb") == 0)
790 arm->core_state = ARM_STATE_THUMB;
791 }
792
793 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
794
795 return ERROR_OK;
796 }
797
798 COMMAND_HANDLER(handle_arm_disassemble_command)
799 {
800 int retval = ERROR_OK;
801 struct target *target = get_current_target(CMD_CTX);
802
803 if (target == NULL) {
804 LOG_ERROR("No target selected");
805 return ERROR_FAIL;
806 }
807
808 struct arm *arm = target_to_arm(target);
809 uint32_t address;
810 int count = 1;
811 int thumb = 0;
812
813 if (!is_arm(arm)) {
814 command_print(CMD_CTX, "current target isn't an ARM");
815 return ERROR_FAIL;
816 }
817
818 if (arm->core_type == ARM_MODE_THREAD) {
819 /* armv7m is always thumb mode */
820 thumb = 1;
821 }
822
823 switch (CMD_ARGC) {
824 case 3:
825 if (strcmp(CMD_ARGV[2], "thumb") != 0)
826 goto usage;
827 thumb = 1;
828 /* FALL THROUGH */
829 case 2:
830 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
831 /* FALL THROUGH */
832 case 1:
833 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
834 if (address & 0x01) {
835 if (!thumb) {
836 command_print(CMD_CTX, "Disassemble as Thumb");
837 thumb = 1;
838 }
839 address &= ~1;
840 }
841 break;
842 default:
843 usage:
844 count = 0;
845 retval = ERROR_COMMAND_SYNTAX_ERROR;
846 }
847
848 while (count-- > 0) {
849 struct arm_instruction cur_instruction;
850
851 if (thumb) {
852 /* Always use Thumb2 disassembly for best handling
853 * of 32-bit BL/BLX, and to work with newer cores
854 * (some ARMv6, all ARMv7) that use Thumb2.
855 */
856 retval = thumb2_opcode(target, address,
857 &cur_instruction);
858 if (retval != ERROR_OK)
859 break;
860 } else {
861 uint32_t opcode;
862
863 retval = target_read_u32(target, address, &opcode);
864 if (retval != ERROR_OK)
865 break;
866 retval = arm_evaluate_opcode(opcode, address,
867 &cur_instruction) != ERROR_OK;
868 if (retval != ERROR_OK)
869 break;
870 }
871 command_print(CMD_CTX, "%s", cur_instruction.text);
872 address += cur_instruction.instruction_size;
873 }
874
875 return retval;
876 }
877
878 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
879 {
880 struct command_context *context;
881 struct target *target;
882 struct arm *arm;
883 int retval;
884
885 context = current_command_context(interp);
886 assert(context != NULL);
887
888 target = get_current_target(context);
889 if (target == NULL) {
890 LOG_ERROR("%s: no current target", __func__);
891 return JIM_ERR;
892 }
893 if (!target_was_examined(target)) {
894 LOG_ERROR("%s: not yet examined", target_name(target));
895 return JIM_ERR;
896 }
897 arm = target_to_arm(target);
898 if (!is_arm(arm)) {
899 LOG_ERROR("%s: not an ARM", target_name(target));
900 return JIM_ERR;
901 }
902
903 if ((argc < 6) || (argc > 7)) {
904 /* FIXME use the command name to verify # params... */
905 LOG_ERROR("%s: wrong number of arguments", __func__);
906 return JIM_ERR;
907 }
908
909 int cpnum;
910 uint32_t op1;
911 uint32_t op2;
912 uint32_t CRn;
913 uint32_t CRm;
914 uint32_t value;
915 long l;
916
917 /* NOTE: parameter sequence matches ARM instruction set usage:
918 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
919 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
920 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
921 */
922 retval = Jim_GetLong(interp, argv[1], &l);
923 if (retval != JIM_OK)
924 return retval;
925 if (l & ~0xf) {
926 LOG_ERROR("%s: %s %d out of range", __func__,
927 "coprocessor", (int) l);
928 return JIM_ERR;
929 }
930 cpnum = l;
931
932 retval = Jim_GetLong(interp, argv[2], &l);
933 if (retval != JIM_OK)
934 return retval;
935 if (l & ~0x7) {
936 LOG_ERROR("%s: %s %d out of range", __func__,
937 "op1", (int) l);
938 return JIM_ERR;
939 }
940 op1 = l;
941
942 retval = Jim_GetLong(interp, argv[3], &l);
943 if (retval != JIM_OK)
944 return retval;
945 if (l & ~0xf) {
946 LOG_ERROR("%s: %s %d out of range", __func__,
947 "CRn", (int) l);
948 return JIM_ERR;
949 }
950 CRn = l;
951
952 retval = Jim_GetLong(interp, argv[4], &l);
953 if (retval != JIM_OK)
954 return retval;
955 if (l & ~0xf) {
956 LOG_ERROR("%s: %s %d out of range", __func__,
957 "CRm", (int) l);
958 return JIM_ERR;
959 }
960 CRm = l;
961
962 retval = Jim_GetLong(interp, argv[5], &l);
963 if (retval != JIM_OK)
964 return retval;
965 if (l & ~0x7) {
966 LOG_ERROR("%s: %s %d out of range", __func__,
967 "op2", (int) l);
968 return JIM_ERR;
969 }
970 op2 = l;
971
972 value = 0;
973
974 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
975 * that could easily be a typo! Check both...
976 *
977 * FIXME change the call syntax here ... simplest to just pass
978 * the MRC() or MCR() instruction to be executed. That will also
979 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
980 * if that's ever needed.
981 */
982 if (argc == 7) {
983 retval = Jim_GetLong(interp, argv[6], &l);
984 if (retval != JIM_OK)
985 return retval;
986 value = l;
987
988 /* NOTE: parameters reordered! */
989 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
990 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
991 if (retval != ERROR_OK)
992 return JIM_ERR;
993 } else {
994 /* NOTE: parameters reordered! */
995 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
996 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
997 if (retval != ERROR_OK)
998 return JIM_ERR;
999
1000 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1001 }
1002
1003 return JIM_OK;
1004 }
1005
1006 COMMAND_HANDLER(handle_arm_semihosting_command)
1007 {
1008 struct target *target = get_current_target(CMD_CTX);
1009
1010 if (target == NULL) {
1011 LOG_ERROR("No target selected");
1012 return ERROR_FAIL;
1013 }
1014
1015 struct arm *arm = target_to_arm(target);
1016
1017 if (!is_arm(arm)) {
1018 command_print(CMD_CTX, "current target isn't an ARM");
1019 return ERROR_FAIL;
1020 }
1021
1022 if (!arm->setup_semihosting) {
1023 command_print(CMD_CTX, "semihosting not supported for current target");
1024 return ERROR_FAIL;
1025 }
1026
1027 if (CMD_ARGC > 0) {
1028 int semihosting;
1029
1030 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
1031
1032 if (!target_was_examined(target)) {
1033 LOG_ERROR("Target not examined yet");
1034 return ERROR_FAIL;
1035 }
1036
1037 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
1038 LOG_ERROR("Failed to Configure semihosting");
1039 return ERROR_FAIL;
1040 }
1041
1042 /* FIXME never let that "catch" be dropped! */
1043 arm->is_semihosting = semihosting;
1044 }
1045
1046 command_print(CMD_CTX, "semihosting is %s",
1047 arm->is_semihosting
1048 ? "enabled" : "disabled");
1049
1050 return ERROR_OK;
1051 }
1052
1053 static const struct command_registration arm_exec_command_handlers[] = {
1054 {
1055 .name = "reg",
1056 .handler = handle_armv4_5_reg_command,
1057 .mode = COMMAND_EXEC,
1058 .help = "display ARM core registers",
1059 .usage = "",
1060 },
1061 {
1062 .name = "core_state",
1063 .handler = handle_armv4_5_core_state_command,
1064 .mode = COMMAND_EXEC,
1065 .usage = "['arm'|'thumb']",
1066 .help = "display/change ARM core state",
1067 },
1068 {
1069 .name = "disassemble",
1070 .handler = handle_arm_disassemble_command,
1071 .mode = COMMAND_EXEC,
1072 .usage = "address [count ['thumb']]",
1073 .help = "disassemble instructions ",
1074 },
1075 {
1076 .name = "mcr",
1077 .mode = COMMAND_EXEC,
1078 .jim_handler = &jim_mcrmrc,
1079 .help = "write coprocessor register",
1080 .usage = "cpnum op1 CRn CRm op2 value",
1081 },
1082 {
1083 .name = "mrc",
1084 .jim_handler = &jim_mcrmrc,
1085 .help = "read coprocessor register",
1086 .usage = "cpnum op1 CRn CRm op2",
1087 },
1088 {
1089 "semihosting",
1090 .handler = handle_arm_semihosting_command,
1091 .mode = COMMAND_EXEC,
1092 .usage = "['enable'|'disable']",
1093 .help = "activate support for semihosting operations",
1094 },
1095
1096 COMMAND_REGISTRATION_DONE
1097 };
1098 const struct command_registration arm_command_handlers[] = {
1099 {
1100 .name = "arm",
1101 .mode = COMMAND_ANY,
1102 .help = "ARM command group",
1103 .usage = "",
1104 .chain = arm_exec_command_handlers,
1105 },
1106 COMMAND_REGISTRATION_DONE
1107 };
1108
1109 int arm_get_gdb_reg_list(struct target *target,
1110 struct reg **reg_list[], int *reg_list_size,
1111 enum target_register_class reg_class)
1112 {
1113 struct arm *arm = target_to_arm(target);
1114 unsigned int i;
1115
1116 if (!is_arm_mode(arm->core_mode)) {
1117 LOG_ERROR("not a valid arm core mode - communication failure?");
1118 return ERROR_FAIL;
1119 }
1120
1121 switch (reg_class) {
1122 case REG_CLASS_GENERAL:
1123 *reg_list_size = 26;
1124 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1125
1126 for (i = 0; i < 16; i++)
1127 (*reg_list)[i] = arm_reg_current(arm, i);
1128
1129 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1130 for (i = 16; i < 24; i++)
1131 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1132 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1133
1134 (*reg_list)[25] = arm->cpsr;
1135
1136 return ERROR_OK;
1137 break;
1138
1139 case REG_CLASS_ALL:
1140 *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
1141 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1142
1143 for (i = 0; i < 16; i++)
1144 (*reg_list)[i] = arm_reg_current(arm, i);
1145
1146 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1147 int reg_index = arm->core_cache->reg_list[i].number;
1148 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1149 && arm->core_type != ARM_MODE_MON))
1150 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1151 }
1152
1153 /* When we supply the target description, there is no need for fake FPA */
1154 for (i = 16; i < 24; i++) {
1155 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1156 (*reg_list)[i]->size = 0;
1157 }
1158 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1159 (*reg_list)[24]->size = 0;
1160
1161 return ERROR_OK;
1162 break;
1163
1164 default:
1165 LOG_ERROR("not a valid register class type in query.");
1166 return ERROR_FAIL;
1167 break;
1168 }
1169 }
1170
1171 /* wait for execution to complete and check exit point */
1172 static int armv4_5_run_algorithm_completion(struct target *target,
1173 uint32_t exit_point,
1174 int timeout_ms,
1175 void *arch_info)
1176 {
1177 int retval;
1178 struct arm *arm = target_to_arm(target);
1179
1180 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1181 if (retval != ERROR_OK)
1182 return retval;
1183 if (target->state != TARGET_HALTED) {
1184 retval = target_halt(target);
1185 if (retval != ERROR_OK)
1186 return retval;
1187 retval = target_wait_state(target, TARGET_HALTED, 500);
1188 if (retval != ERROR_OK)
1189 return retval;
1190 return ERROR_TARGET_TIMEOUT;
1191 }
1192
1193 /* fast exit: ARMv5+ code can use BKPT */
1194 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1195 LOG_WARNING(
1196 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1197 buf_get_u32(arm->pc->value, 0, 32));
1198 return ERROR_TARGET_TIMEOUT;
1199 }
1200
1201 return ERROR_OK;
1202 }
1203
1204 int armv4_5_run_algorithm_inner(struct target *target,
1205 int num_mem_params, struct mem_param *mem_params,
1206 int num_reg_params, struct reg_param *reg_params,
1207 uint32_t entry_point, uint32_t exit_point,
1208 int timeout_ms, void *arch_info,
1209 int (*run_it)(struct target *target, uint32_t exit_point,
1210 int timeout_ms, void *arch_info))
1211 {
1212 struct arm *arm = target_to_arm(target);
1213 struct arm_algorithm *arm_algorithm_info = arch_info;
1214 enum arm_state core_state = arm->core_state;
1215 uint32_t context[17];
1216 uint32_t cpsr;
1217 int exit_breakpoint_size = 0;
1218 int i;
1219 int retval = ERROR_OK;
1220
1221 LOG_DEBUG("Running algorithm");
1222
1223 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1224 LOG_ERROR("current target isn't an ARMV4/5 target");
1225 return ERROR_TARGET_INVALID;
1226 }
1227
1228 if (target->state != TARGET_HALTED) {
1229 LOG_WARNING("target not halted");
1230 return ERROR_TARGET_NOT_HALTED;
1231 }
1232
1233 if (!is_arm_mode(arm->core_mode)) {
1234 LOG_ERROR("not a valid arm core mode - communication failure?");
1235 return ERROR_FAIL;
1236 }
1237
1238 /* armv5 and later can terminate with BKPT instruction; less overhead */
1239 if (!exit_point && arm->is_armv4) {
1240 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1241 return ERROR_FAIL;
1242 }
1243
1244 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1245 * they'll be restored later.
1246 */
1247 for (i = 0; i <= 16; i++) {
1248 struct reg *r;
1249
1250 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1251 arm_algorithm_info->core_mode, i);
1252 if (!r->valid)
1253 arm->read_core_reg(target, r, i,
1254 arm_algorithm_info->core_mode);
1255 context[i] = buf_get_u32(r->value, 0, 32);
1256 }
1257 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1258
1259 for (i = 0; i < num_mem_params; i++) {
1260 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1261 mem_params[i].value);
1262 if (retval != ERROR_OK)
1263 return retval;
1264 }
1265
1266 for (i = 0; i < num_reg_params; i++) {
1267 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1268 if (!reg) {
1269 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1270 return ERROR_COMMAND_SYNTAX_ERROR;
1271 }
1272
1273 if (reg->size != reg_params[i].size) {
1274 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1275 reg_params[i].reg_name);
1276 return ERROR_COMMAND_SYNTAX_ERROR;
1277 }
1278
1279 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1280 if (retval != ERROR_OK)
1281 return retval;
1282 }
1283
1284 arm->core_state = arm_algorithm_info->core_state;
1285 if (arm->core_state == ARM_STATE_ARM)
1286 exit_breakpoint_size = 4;
1287 else if (arm->core_state == ARM_STATE_THUMB)
1288 exit_breakpoint_size = 2;
1289 else {
1290 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1291 return ERROR_COMMAND_SYNTAX_ERROR;
1292 }
1293
1294 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1295 LOG_DEBUG("setting core_mode: 0x%2.2x",
1296 arm_algorithm_info->core_mode);
1297 buf_set_u32(arm->cpsr->value, 0, 5,
1298 arm_algorithm_info->core_mode);
1299 arm->cpsr->dirty = 1;
1300 arm->cpsr->valid = 1;
1301 }
1302
1303 /* terminate using a hardware or (ARMv5+) software breakpoint */
1304 if (exit_point) {
1305 retval = breakpoint_add(target, exit_point,
1306 exit_breakpoint_size, BKPT_HARD);
1307 if (retval != ERROR_OK) {
1308 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1309 return ERROR_TARGET_FAILURE;
1310 }
1311 }
1312
1313 retval = target_resume(target, 0, entry_point, 1, 1);
1314 if (retval != ERROR_OK)
1315 return retval;
1316 retval = run_it(target, exit_point, timeout_ms, arch_info);
1317
1318 if (exit_point)
1319 breakpoint_remove(target, exit_point);
1320
1321 if (retval != ERROR_OK)
1322 return retval;
1323
1324 for (i = 0; i < num_mem_params; i++) {
1325 if (mem_params[i].direction != PARAM_OUT) {
1326 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1327 mem_params[i].size,
1328 mem_params[i].value);
1329 if (retvaltemp != ERROR_OK)
1330 retval = retvaltemp;
1331 }
1332 }
1333
1334 for (i = 0; i < num_reg_params; i++) {
1335 if (reg_params[i].direction != PARAM_OUT) {
1336
1337 struct reg *reg = register_get_by_name(arm->core_cache,
1338 reg_params[i].reg_name,
1339 0);
1340 if (!reg) {
1341 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1342 retval = ERROR_COMMAND_SYNTAX_ERROR;
1343 continue;
1344 }
1345
1346 if (reg->size != reg_params[i].size) {
1347 LOG_ERROR(
1348 "BUG: register '%s' size doesn't match reg_params[i].size",
1349 reg_params[i].reg_name);
1350 retval = ERROR_COMMAND_SYNTAX_ERROR;
1351 continue;
1352 }
1353
1354 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1355 }
1356 }
1357
1358 /* restore everything we saved before (17 or 18 registers) */
1359 for (i = 0; i <= 16; i++) {
1360 uint32_t regvalue;
1361 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1362 arm_algorithm_info->core_mode, i).value, 0, 32);
1363 if (regvalue != context[i]) {
1364 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1365 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1366 arm_algorithm_info->core_mode, i).name, context[i]);
1367 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1368 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1369 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1370 i).valid = 1;
1371 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1372 i).dirty = 1;
1373 }
1374 }
1375
1376 arm_set_cpsr(arm, cpsr);
1377 arm->cpsr->dirty = 1;
1378
1379 arm->core_state = core_state;
1380
1381 return retval;
1382 }
1383
1384 int armv4_5_run_algorithm(struct target *target,
1385 int num_mem_params,
1386 struct mem_param *mem_params,
1387 int num_reg_params,
1388 struct reg_param *reg_params,
1389 uint32_t entry_point,
1390 uint32_t exit_point,
1391 int timeout_ms,
1392 void *arch_info)
1393 {
1394 return armv4_5_run_algorithm_inner(target,
1395 num_mem_params,
1396 mem_params,
1397 num_reg_params,
1398 reg_params,
1399 entry_point,
1400 exit_point,
1401 timeout_ms,
1402 arch_info,
1403 armv4_5_run_algorithm_completion);
1404 }
1405
1406 /**
1407 * Runs ARM code in the target to calculate a CRC32 checksum.
1408 *
1409 */
1410 int arm_checksum_memory(struct target *target,
1411 uint32_t address, uint32_t count, uint32_t *checksum)
1412 {
1413 struct working_area *crc_algorithm;
1414 struct arm_algorithm arm_algo;
1415 struct arm *arm = target_to_arm(target);
1416 struct reg_param reg_params[2];
1417 int retval;
1418 uint32_t i;
1419 uint32_t exit_var = 0;
1420
1421 /* see contrib/loaders/checksum/armv4_5_crc.s for src */
1422
1423 static const uint32_t arm_crc_code[] = {
1424 0xE1A02000, /* mov r2, r0 */
1425 0xE3E00000, /* mov r0, #0xffffffff */
1426 0xE1A03001, /* mov r3, r1 */
1427 0xE3A04000, /* mov r4, #0 */
1428 0xEA00000B, /* b ncomp */
1429 /* nbyte: */
1430 0xE7D21004, /* ldrb r1, [r2, r4] */
1431 0xE59F7030, /* ldr r7, CRC32XOR */
1432 0xE0200C01, /* eor r0, r0, r1, asl 24 */
1433 0xE3A05000, /* mov r5, #0 */
1434 /* loop: */
1435 0xE3500000, /* cmp r0, #0 */
1436 0xE1A06080, /* mov r6, r0, asl #1 */
1437 0xE2855001, /* add r5, r5, #1 */
1438 0xE1A00006, /* mov r0, r6 */
1439 0xB0260007, /* eorlt r0, r6, r7 */
1440 0xE3550008, /* cmp r5, #8 */
1441 0x1AFFFFF8, /* bne loop */
1442 0xE2844001, /* add r4, r4, #1 */
1443 /* ncomp: */
1444 0xE1540003, /* cmp r4, r3 */
1445 0x1AFFFFF1, /* bne nbyte */
1446 /* end: */
1447 0xe1200070, /* bkpt #0 */
1448 /* CRC32XOR: */
1449 0x04C11DB7 /* .word 0x04C11DB7 */
1450 };
1451
1452 retval = target_alloc_working_area(target,
1453 sizeof(arm_crc_code), &crc_algorithm);
1454 if (retval != ERROR_OK)
1455 return retval;
1456
1457 /* convert code into a buffer in target endianness */
1458 for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
1459 retval = target_write_u32(target,
1460 crc_algorithm->address + i * sizeof(uint32_t),
1461 arm_crc_code[i]);
1462 if (retval != ERROR_OK)
1463 return retval;
1464 }
1465
1466 arm_algo.common_magic = ARM_COMMON_MAGIC;
1467 arm_algo.core_mode = ARM_MODE_SVC;
1468 arm_algo.core_state = ARM_STATE_ARM;
1469
1470 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1471 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1472
1473 buf_set_u32(reg_params[0].value, 0, 32, address);
1474 buf_set_u32(reg_params[1].value, 0, 32, count);
1475
1476 /* 20 second timeout/megabyte */
1477 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1478
1479 /* armv4 must exit using a hardware breakpoint */
1480 if (arm->is_armv4)
1481 exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
1482
1483 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1484 crc_algorithm->address,
1485 exit_var,
1486 timeout, &arm_algo);
1487 if (retval != ERROR_OK) {
1488 LOG_ERROR("error executing ARM crc algorithm");
1489 destroy_reg_param(&reg_params[0]);
1490 destroy_reg_param(&reg_params[1]);
1491 target_free_working_area(target, crc_algorithm);
1492 return retval;
1493 }
1494
1495 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1496
1497 destroy_reg_param(&reg_params[0]);
1498 destroy_reg_param(&reg_params[1]);
1499
1500 target_free_working_area(target, crc_algorithm);
1501
1502 return ERROR_OK;
1503 }
1504
1505 /**
1506 * Runs ARM code in the target to check whether a memory block holds
1507 * all ones. NOR flash which has been erased, and thus may be written,
1508 * holds all ones.
1509 *
1510 */
1511 int arm_blank_check_memory(struct target *target,
1512 uint32_t address, uint32_t count, uint32_t *blank)
1513 {
1514 struct working_area *check_algorithm;
1515 struct reg_param reg_params[3];
1516 struct arm_algorithm arm_algo;
1517 struct arm *arm = target_to_arm(target);
1518 int retval;
1519 uint32_t i;
1520 uint32_t exit_var = 0;
1521
1522 /* see contrib/loaders/erase_check/armv4_5_erase_check.s for src */
1523
1524 static const uint32_t check_code[] = {
1525 /* loop: */
1526 0xe4d03001, /* ldrb r3, [r0], #1 */
1527 0xe0022003, /* and r2, r2, r3 */
1528 0xe2511001, /* subs r1, r1, #1 */
1529 0x1afffffb, /* bne loop */
1530 /* end: */
1531 0xe1200070, /* bkpt #0 */
1532 };
1533
1534 /* make sure we have a working area */
1535 retval = target_alloc_working_area(target,
1536 sizeof(check_code), &check_algorithm);
1537 if (retval != ERROR_OK)
1538 return retval;
1539
1540 /* convert code into a buffer in target endianness */
1541 for (i = 0; i < ARRAY_SIZE(check_code); i++) {
1542 retval = target_write_u32(target,
1543 check_algorithm->address
1544 + i * sizeof(uint32_t),
1545 check_code[i]);
1546 if (retval != ERROR_OK)
1547 return retval;
1548 }
1549
1550 arm_algo.common_magic = ARM_COMMON_MAGIC;
1551 arm_algo.core_mode = ARM_MODE_SVC;
1552 arm_algo.core_state = ARM_STATE_ARM;
1553
1554 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1555 buf_set_u32(reg_params[0].value, 0, 32, address);
1556
1557 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1558 buf_set_u32(reg_params[1].value, 0, 32, count);
1559
1560 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1561 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1562
1563 /* armv4 must exit using a hardware breakpoint */
1564 if (arm->is_armv4)
1565 exit_var = check_algorithm->address + sizeof(check_code) - 4;
1566
1567 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1568 check_algorithm->address,
1569 exit_var,
1570 10000, &arm_algo);
1571 if (retval != ERROR_OK) {
1572 destroy_reg_param(&reg_params[0]);
1573 destroy_reg_param(&reg_params[1]);
1574 destroy_reg_param(&reg_params[2]);
1575 target_free_working_area(target, check_algorithm);
1576 return retval;
1577 }
1578
1579 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1580
1581 destroy_reg_param(&reg_params[0]);
1582 destroy_reg_param(&reg_params[1]);
1583 destroy_reg_param(&reg_params[2]);
1584
1585 target_free_working_area(target, check_algorithm);
1586
1587 return ERROR_OK;
1588 }
1589
1590 static int arm_full_context(struct target *target)
1591 {
1592 struct arm *arm = target_to_arm(target);
1593 unsigned num_regs = arm->core_cache->num_regs;
1594 struct reg *reg = arm->core_cache->reg_list;
1595 int retval = ERROR_OK;
1596
1597 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1598 if (reg->valid)
1599 continue;
1600 retval = armv4_5_get_core_reg(reg);
1601 }
1602 return retval;
1603 }
1604
1605 static int arm_default_mrc(struct target *target, int cpnum,
1606 uint32_t op1, uint32_t op2,
1607 uint32_t CRn, uint32_t CRm,
1608 uint32_t *value)
1609 {
1610 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1611 return ERROR_FAIL;
1612 }
1613
1614 static int arm_default_mcr(struct target *target, int cpnum,
1615 uint32_t op1, uint32_t op2,
1616 uint32_t CRn, uint32_t CRm,
1617 uint32_t value)
1618 {
1619 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1620 return ERROR_FAIL;
1621 }
1622
1623 int arm_init_arch_info(struct target *target, struct arm *arm)
1624 {
1625 target->arch_info = arm;
1626 arm->target = target;
1627
1628 arm->common_magic = ARM_COMMON_MAGIC;
1629
1630 /* core_type may be overridden by subtype logic */
1631 if (arm->core_type != ARM_MODE_THREAD) {
1632 arm->core_type = ARM_MODE_ANY;
1633 arm_set_cpsr(arm, ARM_MODE_USR);
1634 }
1635
1636 /* default full_context() has no core-specific optimizations */
1637 if (!arm->full_context && arm->read_core_reg)
1638 arm->full_context = arm_full_context;
1639
1640 if (!arm->mrc)
1641 arm->mrc = arm_default_mrc;
1642 if (!arm->mcr)
1643 arm->mcr = arm_default_mcr;
1644
1645 return ERROR_OK;
1646 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)