ARM: move mode functions out of header
[openocd.git] / src / target / armv4_5.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by √ėyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV4_5_H
27 #define ARMV4_5_H
28
29 #include "target.h"
30 #include "log.h"
31
32 typedef enum armv4_5_mode
33 {
34 ARMV4_5_MODE_USR = 16,
35 ARMV4_5_MODE_FIQ = 17,
36 ARMV4_5_MODE_IRQ = 18,
37 ARMV4_5_MODE_SVC = 19,
38 ARMV4_5_MODE_ABT = 23,
39 ARMV4_5_MODE_UND = 27,
40 ARMV4_5_MODE_SYS = 31,
41 ARMV4_5_MODE_ANY = -1
42 } armv4_5_mode_t;
43
44 int armv4_5_mode_to_number(enum armv4_5_mode mode);
45 enum armv4_5_mode armv4_5_number_to_mode(int number);
46
47 extern const char **armv4_5_mode_strings;
48
49 typedef enum armv4_5_state
50 {
51 ARMV4_5_STATE_ARM,
52 ARMV4_5_STATE_THUMB,
53 ARMV4_5_STATE_JAZELLE,
54 } armv4_5_state_t;
55
56 extern char* armv4_5_state_strings[];
57
58 extern int armv4_5_core_reg_map[7][17];
59
60 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
61 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
62 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
63 cache->reg_list[armv4_5_core_reg_map[mode][num]]
64
65 /* offsets into armv4_5 core register cache */
66 enum
67 {
68 ARMV4_5_CPSR = 31,
69 ARMV4_5_SPSR_FIQ = 32,
70 ARMV4_5_SPSR_IRQ = 33,
71 ARMV4_5_SPSR_SVC = 34,
72 ARMV4_5_SPSR_ABT = 35,
73 ARMV4_5_SPSR_UND = 36
74 };
75
76 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
77
78 /* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
79 #define armv4_5_common_s arm
80
81 /**
82 * Represents a generic ARM core, with standard application registers.
83 *
84 * There are sixteen application registers (including PC, SP, LR) and a PSR.
85 * Cortex-M series cores do not support as many core states or shadowed
86 * registers as traditional ARM cores, and only support Thumb2 instructions.
87 */
88 struct arm
89 {
90 int common_magic;
91 struct reg_cache *core_cache;
92
93 int /* armv4_5_mode */ core_mode;
94 enum armv4_5_state core_state;
95
96 /** Flag reporting unavailability of the BKPT instruction. */
97 bool is_armv4;
98
99 /** Handle for the Embedded Trace Module, if one is present. */
100 struct etm_context *etm;
101
102 int (*full_context)(struct target *target);
103 int (*read_core_reg)(struct target *target,
104 int num, enum armv4_5_mode mode);
105 int (*write_core_reg)(struct target *target,
106 int num, enum armv4_5_mode mode, uint32_t value);
107 void *arch_info;
108 };
109
110 #define target_to_armv4_5 target_to_arm
111
112 /** Convert target handle to generic ARM target state handle. */
113 static inline struct arm *target_to_arm(struct target *target)
114 {
115 return target->arch_info;
116 }
117
118 static inline bool is_arm(struct arm *arm)
119 {
120 return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
121 }
122
123 struct armv4_5_algorithm
124 {
125 int common_magic;
126
127 enum armv4_5_mode core_mode;
128 enum armv4_5_state core_state;
129 };
130
131 struct armv4_5_core_reg
132 {
133 int num;
134 enum armv4_5_mode mode;
135 struct target *target;
136 struct arm *armv4_5_common;
137 };
138
139 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
140 struct arm *armv4_5_common);
141
142 int armv4_5_arch_state(struct target *target);
143 int armv4_5_get_gdb_reg_list(struct target *target,
144 struct reg **reg_list[], int *reg_list_size);
145
146 int armv4_5_register_commands(struct command_context *cmd_ctx);
147 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
148
149 int armv4_5_run_algorithm(struct target *target,
150 int num_mem_params, struct mem_param *mem_params,
151 int num_reg_params, struct reg_param *reg_params,
152 uint32_t entry_point, uint32_t exit_point,
153 int timeout_ms, void *arch_info);
154
155 int armv4_5_invalidate_core_regs(struct target *target);
156
157 int arm_checksum_memory(struct target *target,
158 uint32_t address, uint32_t count, uint32_t *checksum);
159 int arm_blank_check_memory(struct target *target,
160 uint32_t address, uint32_t count, uint32_t *blank);
161
162
163 /* ARM mode instructions
164 */
165
166 /* Store multiple increment after
167 * Rn: base register
168 * List: for each bit in list: store register
169 * S: in priviledged mode: store user-mode registers
170 * W = 1: update the base register. W = 0: leave the base register untouched
171 */
172 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
173
174 /* Load multiple increment after
175 * Rn: base register
176 * List: for each bit in list: store register
177 * S: in priviledged mode: store user-mode registers
178 * W = 1: update the base register. W = 0: leave the base register untouched
179 */
180 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
181
182 /* MOV r8, r8 */
183 #define ARMV4_5_NOP (0xe1a08008)
184
185 /* Move PSR to general purpose register
186 * R = 1: SPSR R = 0: CPSR
187 * Rn: target register
188 */
189 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
190
191 /* Store register
192 * Rd: register to store
193 * Rn: base register
194 */
195 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
196
197 /* Load register
198 * Rd: register to load
199 * Rn: base register
200 */
201 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
202
203 /* Move general purpose register to PSR
204 * R = 1: SPSR R = 0: CPSR
205 * Field: Field mask
206 * 1: control field 2: extension field 4: status field 8: flags field
207 * Rm: source register
208 */
209 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
210 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
211
212 /* Load Register Halfword Immediate Post-Index
213 * Rd: register to load
214 * Rn: base register
215 */
216 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
217
218 /* Load Register Byte Immediate Post-Index
219 * Rd: register to load
220 * Rn: base register
221 */
222 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
223
224 /* Store register Halfword Immediate Post-Index
225 * Rd: register to store
226 * Rn: base register
227 */
228 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
229
230 /* Store register Byte Immediate Post-Index
231 * Rd: register to store
232 * Rn: base register
233 */
234 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
235
236 /* Branch (and Link)
237 * Im: Branch target (left-shifted by 2 bits, added to PC)
238 * L: 1: branch and link 0: branch only
239 */
240 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
241
242 /* Branch and exchange (ARM state)
243 * Rm: register holding branch target address
244 */
245 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
246
247 /* Move to ARM register from coprocessor
248 * CP: Coprocessor number
249 * op1: Coprocessor opcode
250 * Rd: destination register
251 * CRn: first coprocessor operand
252 * CRm: second coprocessor operand
253 * op2: Second coprocessor opcode
254 */
255 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
256
257 /* Move to coprocessor from ARM register
258 * CP: Coprocessor number
259 * op1: Coprocessor opcode
260 * Rd: destination register
261 * CRn: first coprocessor operand
262 * CRm: second coprocessor operand
263 * op2: Second coprocessor opcode
264 */
265 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
266
267 /* Breakpoint instruction (ARMv5)
268 * Im: 16-bit immediate
269 */
270 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
271
272
273 /* Thumb mode instructions
274 */
275
276 /* Store register (Thumb mode)
277 * Rd: source register
278 * Rn: base register
279 */
280 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
281
282 /* Load register (Thumb state)
283 * Rd: destination register
284 * Rn: base register
285 */
286 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
287
288 /* Load multiple (Thumb state)
289 * Rn: base register
290 * List: for each bit in list: store register
291 */
292 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
293
294 /* Load register with PC relative addressing
295 * Rd: register to load
296 */
297 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
298
299 /* Move hi register (Thumb mode)
300 * Rd: destination register
301 * Rm: source register
302 */
303 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
304
305 /* No operation (Thumb mode)
306 */
307 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
308
309 /* Move immediate to register (Thumb state)
310 * Rd: destination register
311 * Im: 8-bit immediate value
312 */
313 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
314
315 /* Branch and Exchange
316 * Rm: register containing branch target
317 */
318 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
319
320 /* Branch (Thumb state)
321 * Imm: Branch target
322 */
323 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
324
325 /* Breakpoint instruction (ARMv5) (Thumb state)
326 * Im: 8-bit immediate
327 */
328 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
329
330 /* build basic mrc/mcr opcode */
331
332 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
333 {
334 uint32_t t = 0;
335 t|=op1<<21;
336 t|=op2<<5;
337 t|=CRn<<16;
338 t|=CRm<<0;
339 return t;
340 }
341
342 #endif /* ARMV4_5_H */

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