3c65069e024dde1e3ba25998065884ac3483f71f
[openocd.git] / src / target / armv4_5.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by √ėyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV4_5_H
27 #define ARMV4_5_H
28
29 #include "register.h"
30 #include "target.h"
31 #include "log.h"
32 #include "etm.h"
33
34 typedef enum armv4_5_mode
35 {
36 ARMV4_5_MODE_USR = 16,
37 ARMV4_5_MODE_FIQ = 17,
38 ARMV4_5_MODE_IRQ = 18,
39 ARMV4_5_MODE_SVC = 19,
40 ARMV4_5_MODE_ABT = 23,
41 ARMV4_5_MODE_UND = 27,
42 ARMV4_5_MODE_SYS = 31,
43 ARMV4_5_MODE_ANY = -1
44 } armv4_5_mode_t;
45
46 extern char** armv4_5_mode_strings;
47
48 typedef enum armv4_5_state
49 {
50 ARMV4_5_STATE_ARM,
51 ARMV4_5_STATE_THUMB,
52 ARMV4_5_STATE_JAZELLE,
53 } armv4_5_state_t;
54
55 extern char* armv4_5_state_strings[];
56
57 extern int armv4_5_core_reg_map[7][17];
58
59 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
60 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
61 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
62 cache->reg_list[armv4_5_core_reg_map[mode][num]]
63
64 /* offsets into armv4_5 core register cache */
65 enum
66 {
67 ARMV4_5_CPSR = 31,
68 ARMV4_5_SPSR_FIQ = 32,
69 ARMV4_5_SPSR_IRQ = 33,
70 ARMV4_5_SPSR_SVC = 34,
71 ARMV4_5_SPSR_ABT = 35,
72 ARMV4_5_SPSR_UND = 36
73 };
74
75 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
76
77 /* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
78 #define armv4_5_common_s arm
79
80 /**
81 * Represents a generic ARM core, with standard application registers.
82 *
83 * There are sixteen application registers (including PC, SP, LR) and a PSR.
84 * Cortex-M series cores do not support as many core states or shadowed
85 * registers as traditional ARM cores, and only support Thumb2 instructions.
86 */
87 typedef struct arm
88 {
89 int common_magic;
90 struct reg_cache *core_cache;
91
92 int /* armv4_5_mode */ core_mode;
93 enum armv4_5_state core_state;
94
95 /** Flag reporting unavailability of the BKPT instruction. */
96 bool is_armv4;
97
98 /** Handle for the Embedded Trace Module, if one is present. */
99 struct etm_context *etm;
100
101 int (*full_context)(struct target_s *target);
102 int (*read_core_reg)(struct target_s *target,
103 int num, enum armv4_5_mode mode);
104 int (*write_core_reg)(struct target_s *target,
105 int num, enum armv4_5_mode mode, uint32_t value);
106 void *arch_info;
107 } armv4_5_common_t;
108
109 #define target_to_armv4_5 target_to_arm
110
111 /** Convert target handle to generic ARM target state handle. */
112 static inline struct arm *target_to_arm(struct target_s *target)
113 {
114 return target->arch_info;
115 }
116
117 static inline bool is_arm(struct arm *arm)
118 {
119 return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
120 }
121
122 struct armv4_5_algorithm
123 {
124 int common_magic;
125
126 enum armv4_5_mode core_mode;
127 enum armv4_5_state core_state;
128 };
129
130 struct armv4_5_core_reg
131 {
132 int num;
133 enum armv4_5_mode mode;
134 target_t *target;
135 armv4_5_common_t *armv4_5_common;
136 };
137
138 struct reg_cache* armv4_5_build_reg_cache(target_t *target,
139 armv4_5_common_t *armv4_5_common);
140
141 /* map psr mode bits to linear number */
142 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
143 {
144 switch (mode)
145 {
146 case ARMV4_5_MODE_USR: return 0; break;
147 case ARMV4_5_MODE_FIQ: return 1; break;
148 case ARMV4_5_MODE_IRQ: return 2; break;
149 case ARMV4_5_MODE_SVC: return 3; break;
150 case ARMV4_5_MODE_ABT: return 4; break;
151 case ARMV4_5_MODE_UND: return 5; break;
152 case ARMV4_5_MODE_SYS: return 6; break;
153 case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
154 default:
155 LOG_ERROR("invalid mode value encountered %d", mode);
156 return -1;
157 }
158 }
159
160 /* map linear number to mode bits */
161 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
162 {
163 switch (number)
164 {
165 case 0: return ARMV4_5_MODE_USR; break;
166 case 1: return ARMV4_5_MODE_FIQ; break;
167 case 2: return ARMV4_5_MODE_IRQ; break;
168 case 3: return ARMV4_5_MODE_SVC; break;
169 case 4: return ARMV4_5_MODE_ABT; break;
170 case 5: return ARMV4_5_MODE_UND; break;
171 case 6: return ARMV4_5_MODE_SYS; break;
172 default:
173 LOG_ERROR("mode index out of bounds %d", number);
174 return ARMV4_5_MODE_ANY;
175 }
176 };
177
178 int armv4_5_arch_state(struct target_s *target);
179 int armv4_5_get_gdb_reg_list(target_t *target,
180 reg_t **reg_list[], int *reg_list_size);
181
182 int armv4_5_register_commands(struct command_context_s *cmd_ctx);
183 int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
184
185 int armv4_5_run_algorithm(struct target_s *target,
186 int num_mem_params, struct mem_param *mem_params,
187 int num_reg_params, struct reg_param *reg_params,
188 uint32_t entry_point, uint32_t exit_point,
189 int timeout_ms, void *arch_info);
190
191 int armv4_5_invalidate_core_regs(target_t *target);
192
193 /* ARM mode instructions
194 */
195
196 /* Store multiple increment after
197 * Rn: base register
198 * List: for each bit in list: store register
199 * S: in priviledged mode: store user-mode registers
200 * W = 1: update the base register. W = 0: leave the base register untouched
201 */
202 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
203
204 /* Load multiple increment after
205 * Rn: base register
206 * List: for each bit in list: store register
207 * S: in priviledged mode: store user-mode registers
208 * W = 1: update the base register. W = 0: leave the base register untouched
209 */
210 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
211
212 /* MOV r8, r8 */
213 #define ARMV4_5_NOP (0xe1a08008)
214
215 /* Move PSR to general purpose register
216 * R = 1: SPSR R = 0: CPSR
217 * Rn: target register
218 */
219 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
220
221 /* Store register
222 * Rd: register to store
223 * Rn: base register
224 */
225 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
226
227 /* Load register
228 * Rd: register to load
229 * Rn: base register
230 */
231 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
232
233 /* Move general purpose register to PSR
234 * R = 1: SPSR R = 0: CPSR
235 * Field: Field mask
236 * 1: control field 2: extension field 4: status field 8: flags field
237 * Rm: source register
238 */
239 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
240 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
241
242 /* Load Register Halfword Immediate Post-Index
243 * Rd: register to load
244 * Rn: base register
245 */
246 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
247
248 /* Load Register Byte Immediate Post-Index
249 * Rd: register to load
250 * Rn: base register
251 */
252 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
253
254 /* Store register Halfword Immediate Post-Index
255 * Rd: register to store
256 * Rn: base register
257 */
258 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
259
260 /* Store register Byte Immediate Post-Index
261 * Rd: register to store
262 * Rn: base register
263 */
264 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
265
266 /* Branch (and Link)
267 * Im: Branch target (left-shifted by 2 bits, added to PC)
268 * L: 1: branch and link 0: branch only
269 */
270 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
271
272 /* Branch and exchange (ARM state)
273 * Rm: register holding branch target address
274 */
275 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
276
277 /* Move to ARM register from coprocessor
278 * CP: Coprocessor number
279 * op1: Coprocessor opcode
280 * Rd: destination register
281 * CRn: first coprocessor operand
282 * CRm: second coprocessor operand
283 * op2: Second coprocessor opcode
284 */
285 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
286
287 /* Move to coprocessor from ARM register
288 * CP: Coprocessor number
289 * op1: Coprocessor opcode
290 * Rd: destination register
291 * CRn: first coprocessor operand
292 * CRm: second coprocessor operand
293 * op2: Second coprocessor opcode
294 */
295 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
296
297 /* Breakpoint instruction (ARMv5)
298 * Im: 16-bit immediate
299 */
300 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
301
302
303 /* Thumb mode instructions
304 */
305
306 /* Store register (Thumb mode)
307 * Rd: source register
308 * Rn: base register
309 */
310 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
311
312 /* Load register (Thumb state)
313 * Rd: destination register
314 * Rn: base register
315 */
316 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
317
318 /* Load multiple (Thumb state)
319 * Rn: base register
320 * List: for each bit in list: store register
321 */
322 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
323
324 /* Load register with PC relative addressing
325 * Rd: register to load
326 */
327 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
328
329 /* Move hi register (Thumb mode)
330 * Rd: destination register
331 * Rm: source register
332 */
333 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
334
335 /* No operation (Thumb mode)
336 */
337 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
338
339 /* Move immediate to register (Thumb state)
340 * Rd: destination register
341 * Im: 8-bit immediate value
342 */
343 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
344
345 /* Branch and Exchange
346 * Rm: register containing branch target
347 */
348 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
349
350 /* Branch (Thumb state)
351 * Imm: Branch target
352 */
353 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
354
355 /* Breakpoint instruction (ARMv5) (Thumb state)
356 * Im: 8-bit immediate
357 */
358 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
359
360 /* build basic mrc/mcr opcode */
361
362 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
363 {
364 uint32_t t = 0;
365 t|=op1<<21;
366 t|=op2<<5;
367 t|=CRn<<16;
368 t|=CRm<<0;
369 return t;
370 }
371
372
373
374
375 #endif /* ARMV4_5_H */

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