src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARMV4_5_H
  24 #define ARMV4_5_H
  25
  26 #include "register.h"
  27 #include "target.h"
  28 #include "log.h"
  29
  30 typedef enum armv4_5_mode
  31 {
  32         ARMV4_5_MODE_USR = 16,
  33         ARMV4_5_MODE_FIQ = 17,
  34         ARMV4_5_MODE_IRQ = 18,
  35         ARMV4_5_MODE_SVC = 19,
  36         ARMV4_5_MODE_ABT = 23,
  37         ARMV4_5_MODE_UND = 27,
  38         ARMV4_5_MODE_SYS = 31,
  39         ARMV4_5_MODE_ANY = -1
  40 } armv4_5_mode_t;
  41
  42 extern char** armv4_5_mode_strings;
  43
  44 typedef enum armv4_5_state
  45 {
  46         ARMV4_5_STATE_ARM,
  47         ARMV4_5_STATE_THUMB,
  48         ARMV4_5_STATE_JAZELLE,
  49 } armv4_5_state_t;
  50
  51 extern char* armv4_5_state_strings[];
  52
  53 extern int armv4_5_core_reg_map[7][17];
  54
  55 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  56                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  57 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
  58                 cache->reg_list[armv4_5_core_reg_map[mode][num]]
  59
  60 /* offsets into armv4_5 core register cache */
  61 enum
  62 {
  63         ARMV4_5_CPSR = 31,
  64         ARMV4_5_SPSR_FIQ = 32,
  65         ARMV4_5_SPSR_IRQ = 33,
  66         ARMV4_5_SPSR_SVC = 34,
  67         ARMV4_5_SPSR_ABT = 35,
  68         ARMV4_5_SPSR_UND = 36
  69 };
  70
  71 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  72
  73 typedef struct armv4_5_common_s
  74 {
  75         int common_magic;
  76         reg_cache_t *core_cache;
  77         int /* armv4_5_mode */ core_mode;
  78         enum armv4_5_state core_state;
  79         bool is_armv4;
  80         int (*full_context)(struct target_s *target);
  81         int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
  82         int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
  83         void *arch_info;
  84 } armv4_5_common_t;
  85
  86 typedef struct armv4_5_algorithm_s
  87 {
  88         int common_magic;
  89
  90         enum armv4_5_mode core_mode;
  91         enum armv4_5_state core_state;
  92 } armv4_5_algorithm_t;
  93
  94 typedef struct armv4_5_core_reg_s
  95 {
  96         int num;
  97         enum armv4_5_mode mode;
  98         target_t *target;
  99         armv4_5_common_t *armv4_5_common;
 100 } armv4_5_core_reg_t;
 101
 102 extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
 103
 104 /* map psr mode bits to linear number */
 105 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 106 {
 107         switch (mode)
 108         {
 109                 case ARMV4_5_MODE_USR: return 0; break;
 110                 case ARMV4_5_MODE_FIQ: return 1; break;
 111                 case ARMV4_5_MODE_IRQ: return 2; break;
 112                 case ARMV4_5_MODE_SVC: return 3; break;
 113                 case ARMV4_5_MODE_ABT: return 4; break;
 114                 case ARMV4_5_MODE_UND: return 5; break;
 115                 case ARMV4_5_MODE_SYS: return 6; break;
 116                 case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
 117                 default:
 118                         LOG_ERROR("invalid mode value encountered %d", mode);
 119                         return -1;
 120         }
 121 }
 122
 123 /* map linear number to mode bits */
 124 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 125 {
 126         switch (number)
 127         {
 128                 case 0: return ARMV4_5_MODE_USR; break;
 129                 case 1: return ARMV4_5_MODE_FIQ; break;
 130                 case 2: return ARMV4_5_MODE_IRQ; break;
 131                 case 3: return ARMV4_5_MODE_SVC; break;
 132                 case 4: return ARMV4_5_MODE_ABT; break;
 133                 case 5: return ARMV4_5_MODE_UND; break;
 134                 case 6: return ARMV4_5_MODE_SYS; break;
 135                 default:
 136                         LOG_ERROR("mode index out of bounds %d", number);
 137                         return ARMV4_5_MODE_ANY;
 138         }
 139 };
 140
 141 extern int armv4_5_arch_state(struct target_s *target);
 142 extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 143
 144 extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
 145 extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
 146
 147 extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
 148
 149 extern int armv4_5_invalidate_core_regs(target_t *target);
 150
 151 /* ARM mode instructions
 152  */
 153
 154 /* Store multiple increment after
 155  * Rn: base register
 156  * List: for each bit in list: store register
 157  * S: in priviledged mode: store user-mode registers
 158  * W = 1: update the base register. W = 0: leave the base register untouched
 159  */
 160 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 161
 162 /* Load multiple increment after
 163  * Rn: base register
 164  * List: for each bit in list: store register
 165  * S: in priviledged mode: store user-mode registers
 166  * W = 1: update the base register. W = 0: leave the base register untouched
 167  */
 168 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 169
 170 /* MOV r8, r8 */
 171 #define ARMV4_5_NOP                                     (0xe1a08008)
 172
 173 /* Move PSR to general purpose register
 174  * R = 1: SPSR R = 0: CPSR
 175  * Rn: target register
 176  */
 177 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 178
 179 /* Store register
 180  * Rd: register to store
 181  * Rn: base register
 182  */
 183 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 184
 185 /* Load register
 186  * Rd: register to load
 187  * Rn: base register
 188  */
 189 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 190
 191 /* Move general purpose register to PSR
 192  * R = 1: SPSR R = 0: CPSR
 193  * Field: Field mask
 194  * 1: control field 2: extension field 4: status field 8: flags field
 195  * Rm: source register
 196  */
 197 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 198 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 199
 200 /* Load Register Halfword Immediate Post-Index
 201  * Rd: register to load
 202  * Rn: base register
 203  */
 204 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 205
 206 /* Load Register Byte Immediate Post-Index
 207  * Rd: register to load
 208  * Rn: base register
 209  */
 210 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 211
 212 /* Store register Halfword Immediate Post-Index
 213  * Rd: register to store
 214  * Rn: base register
 215  */
 216 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 217
 218 /* Store register Byte Immediate Post-Index
 219  * Rd: register to store
 220  * Rn: base register
 221  */
 222 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 223
 224 /* Branch (and Link)
 225  * Im: Branch target (left-shifted by 2 bits, added to PC)
 226  * L: 1: branch and link 0: branch only
 227  */
 228 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 229
 230 /* Branch and exchange (ARM state)
 231  * Rm: register holding branch target address
 232  */
 233 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 234
 235 /* Move to ARM register from coprocessor
 236  * CP: Coprocessor number
 237  * op1: Coprocessor opcode
 238  * Rd: destination register
 239  * CRn: first coprocessor operand
 240  * CRm: second coprocessor operand
 241  * op2: Second coprocessor opcode
 242  */
 243 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 244
 245 /* Move to coprocessor from ARM register
 246  * CP: Coprocessor number
 247  * op1: Coprocessor opcode
 248  * Rd: destination register
 249  * CRn: first coprocessor operand
 250  * CRm: second coprocessor operand
 251  * op2: Second coprocessor opcode
 252  */
 253 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 254
 255 /* Breakpoint instruction (ARMv5)
 256  * Im: 16-bit immediate
 257  */
 258 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 259
 260
 261 /* Thumb mode instructions
 262  */
 263
 264 /* Store register (Thumb mode)
 265  * Rd: source register
 266  * Rn: base register
 267  */
 268 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 269
 270 /* Load register (Thumb state)
 271  * Rd: destination register
 272  * Rn: base register
 273  */
 274 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 275
 276 /* Load multiple (Thumb state)
 277  * Rn: base register
 278  * List: for each bit in list: store register
 279  */
 280 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 281
 282 /* Load register with PC relative addressing
 283  * Rd: register to load
 284  */
 285 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 286
 287 /* Move hi register (Thumb mode)
 288  * Rd: destination register
 289  * Rm: source register
 290  */
 291 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 292
 293 /* No operation (Thumb mode)
 294  */
 295 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 296
 297 /* Move immediate to register (Thumb state)
 298  * Rd: destination register
 299  * Im: 8-bit immediate value
 300  */
 301 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 302
 303 /* Branch and Exchange
 304  * Rm: register containing branch target
 305  */
 306 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 307
 308 /* Branch (Thumb state)
 309  * Imm: Branch target
 310  */
 311 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 312
 313 /* Breakpoint instruction (ARMv5) (Thumb state)
 314  * Im: 8-bit immediate
 315  */
 316 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 317
 318 #endif /* ARMV4_5_H */