src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include "target.h"
  30
  31 typedef enum armv4_5_mode
  32 {
  33         ARMV4_5_MODE_USR = 16,
  34         ARMV4_5_MODE_FIQ = 17,
  35         ARMV4_5_MODE_IRQ = 18,
  36         ARMV4_5_MODE_SVC = 19,
  37         ARMV4_5_MODE_ABT = 23,
  38         ARM_MODE_MON = 26,
  39         ARMV4_5_MODE_UND = 27,
  40         ARMV4_5_MODE_SYS = 31,
  41         ARMV4_5_MODE_ANY = -1
  42 } armv4_5_mode_t;
  43
  44 const char *arm_mode_name(unsigned psr_mode);
  45 bool is_arm_mode(unsigned psr_mode);
  46
  47 int armv4_5_mode_to_number(enum armv4_5_mode mode);
  48 enum armv4_5_mode armv4_5_number_to_mode(int number);
  49
  50 typedef enum armv4_5_state
  51 {
  52         ARMV4_5_STATE_ARM,
  53         ARMV4_5_STATE_THUMB,
  54         ARMV4_5_STATE_JAZELLE,
  55 } armv4_5_state_t;
  56
  57 extern char* armv4_5_state_strings[];
  58
  59 extern const int armv4_5_core_reg_map[7][17];
  60
  61 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  62                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  63
  64 /* offsets into armv4_5 core register cache */
  65 enum
  66 {
  67         ARMV4_5_CPSR = 31,
  68         ARMV4_5_SPSR_FIQ = 32,
  69         ARMV4_5_SPSR_IRQ = 33,
  70         ARMV4_5_SPSR_SVC = 34,
  71         ARMV4_5_SPSR_ABT = 35,
  72         ARMV4_5_SPSR_UND = 36
  73 };
  74
  75 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  76
  77 /* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
  78 #define armv4_5_common_s arm
  79
  80 /**
  81  * Represents a generic ARM core, with standard application registers.
  82  *
  83  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  84  * Cortex-M series cores do not support as many core states or shadowed
  85  * registers as traditional ARM cores, and only support Thumb2 instructions.
  86  */
  87 struct arm
  88 {
  89         int common_magic;
  90         struct reg_cache *core_cache;
  91
  92         /**
  93          * Indicates what registers are in the ARM state core register set.
  94          * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
  95          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
  96          * more registers are shadowed, for "Secure Monitor" mode.
  97          */
  98         enum armv4_5_mode core_type;
  99
 100         enum armv4_5_mode core_mode;
 101         enum armv4_5_state core_state;
 102
 103         /** Flag reporting unavailability of the BKPT instruction. */
 104         bool is_armv4;
 105
 106         /** Handle for the Embedded Trace Module, if one is present. */
 107         struct etm_context *etm;
 108
 109         int (*full_context)(struct target *target);
 110         int (*read_core_reg)(struct target *target,
 111                         int num, enum armv4_5_mode mode);
 112         int (*write_core_reg)(struct target *target,
 113                         int num, enum armv4_5_mode mode, uint32_t value);
 114         void *arch_info;
 115 };
 116
 117 #define target_to_armv4_5 target_to_arm
 118
 119 /** Convert target handle to generic ARM target state handle. */
 120 static inline struct arm *target_to_arm(struct target *target)
 121 {
 122         return target->arch_info;
 123 }
 124
 125 static inline bool is_arm(struct arm *arm)
 126 {
 127         return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
 128 }
 129
 130 struct armv4_5_algorithm
 131 {
 132         int common_magic;
 133
 134         enum armv4_5_mode core_mode;
 135         enum armv4_5_state core_state;
 136 };
 137
 138 struct armv4_5_core_reg
 139 {
 140         int num;
 141         enum armv4_5_mode mode;
 142         struct target *target;
 143         struct arm *armv4_5_common;
 144 };
 145
 146 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
 147                 struct arm *armv4_5_common);
 148
 149 int armv4_5_arch_state(struct target *target);
 150 int armv4_5_get_gdb_reg_list(struct target *target,
 151                 struct reg **reg_list[], int *reg_list_size);
 152
 153 int armv4_5_register_commands(struct command_context *cmd_ctx);
 154 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 155
 156 int armv4_5_run_algorithm(struct target *target,
 157                 int num_mem_params, struct mem_param *mem_params,
 158                 int num_reg_params, struct reg_param *reg_params,
 159                 uint32_t entry_point, uint32_t exit_point,
 160                 int timeout_ms, void *arch_info);
 161
 162 int armv4_5_invalidate_core_regs(struct target *target);
 163
 164 int arm_checksum_memory(struct target *target,
 165                 uint32_t address, uint32_t count, uint32_t *checksum);
 166 int arm_blank_check_memory(struct target *target,
 167                 uint32_t address, uint32_t count, uint32_t *blank);
 168
 169 extern struct reg arm_gdb_dummy_fp_reg;
 170 extern struct reg arm_gdb_dummy_fps_reg;
 171
 172 /* ARM mode instructions
 173  */
 174
 175 /* Store multiple increment after
 176  * Rn: base register
 177  * List: for each bit in list: store register
 178  * S: in priviledged mode: store user-mode registers
 179  * W = 1: update the base register. W = 0: leave the base register untouched
 180  */
 181 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 182
 183 /* Load multiple increment after
 184  * Rn: base register
 185  * List: for each bit in list: store register
 186  * S: in priviledged mode: store user-mode registers
 187  * W = 1: update the base register. W = 0: leave the base register untouched
 188  */
 189 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 190
 191 /* MOV r8, r8 */
 192 #define ARMV4_5_NOP                                     (0xe1a08008)
 193
 194 /* Move PSR to general purpose register
 195  * R = 1: SPSR R = 0: CPSR
 196  * Rn: target register
 197  */
 198 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 199
 200 /* Store register
 201  * Rd: register to store
 202  * Rn: base register
 203  */
 204 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 205
 206 /* Load register
 207  * Rd: register to load
 208  * Rn: base register
 209  */
 210 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 211
 212 /* Move general purpose register to PSR
 213  * R = 1: SPSR R = 0: CPSR
 214  * Field: Field mask
 215  * 1: control field 2: extension field 4: status field 8: flags field
 216  * Rm: source register
 217  */
 218 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 219 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 220
 221 /* Load Register Halfword Immediate Post-Index
 222  * Rd: register to load
 223  * Rn: base register
 224  */
 225 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 226
 227 /* Load Register Byte Immediate Post-Index
 228  * Rd: register to load
 229  * Rn: base register
 230  */
 231 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 232
 233 /* Store register Halfword Immediate Post-Index
 234  * Rd: register to store
 235  * Rn: base register
 236  */
 237 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 238
 239 /* Store register Byte Immediate Post-Index
 240  * Rd: register to store
 241  * Rn: base register
 242  */
 243 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 244
 245 /* Branch (and Link)
 246  * Im: Branch target (left-shifted by 2 bits, added to PC)
 247  * L: 1: branch and link 0: branch only
 248  */
 249 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 250
 251 /* Branch and exchange (ARM state)
 252  * Rm: register holding branch target address
 253  */
 254 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 255
 256 /* Move to ARM register from coprocessor
 257  * CP: Coprocessor number
 258  * op1: Coprocessor opcode
 259  * Rd: destination register
 260  * CRn: first coprocessor operand
 261  * CRm: second coprocessor operand
 262  * op2: Second coprocessor opcode
 263  */
 264 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 265
 266 /* Move to coprocessor from ARM register
 267  * CP: Coprocessor number
 268  * op1: Coprocessor opcode
 269  * Rd: destination register
 270  * CRn: first coprocessor operand
 271  * CRm: second coprocessor operand
 272  * op2: Second coprocessor opcode
 273  */
 274 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 275
 276 /* Breakpoint instruction (ARMv5)
 277  * Im: 16-bit immediate
 278  */
 279 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 280
 281
 282 /* Thumb mode instructions
 283  */
 284
 285 /* Store register (Thumb mode)
 286  * Rd: source register
 287  * Rn: base register
 288  */
 289 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 290
 291 /* Load register (Thumb state)
 292  * Rd: destination register
 293  * Rn: base register
 294  */
 295 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 296
 297 /* Load multiple (Thumb state)
 298  * Rn: base register
 299  * List: for each bit in list: store register
 300  */
 301 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 302
 303 /* Load register with PC relative addressing
 304  * Rd: register to load
 305  */
 306 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 307
 308 /* Move hi register (Thumb mode)
 309  * Rd: destination register
 310  * Rm: source register
 311  */
 312 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 313
 314 /* No operation (Thumb mode)
 315  */
 316 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 317
 318 /* Move immediate to register (Thumb state)
 319  * Rd: destination register
 320  * Im: 8-bit immediate value
 321  */
 322 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 323
 324 /* Branch and Exchange
 325  * Rm: register containing branch target
 326  */
 327 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 328
 329 /* Branch (Thumb state)
 330  * Imm: Branch target
 331  */
 332 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 333
 334 /* Breakpoint instruction (ARMv5) (Thumb state)
 335  * Im: 8-bit immediate
 336  */
 337 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 338
 339 /* build basic mrc/mcr opcode */
 340
 341 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 342 {
 343         uint32_t t = 0;
 344         t|=op1<<21;
 345         t|=op2<<5;
 346         t|=CRn<<16;
 347         t|=CRm<<0;
 348         return t;
 349 }
 350
 351 #endif /* ARMV4_5_H */