src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifndef ARMV4_5_H
  21 #define ARMV4_5_H
  22
  23 #include "register.h"
  24 #include "target.h"
  25 #include "log.h"
  26
  27 typedef enum armv4_5_mode
  28 {
  29         ARMV4_5_MODE_USR = 16,
  30         ARMV4_5_MODE_FIQ = 17,
  31         ARMV4_5_MODE_IRQ = 18,
  32         ARMV4_5_MODE_SVC = 19,
  33         ARMV4_5_MODE_ABT = 23,
  34         ARMV4_5_MODE_UND = 27,
  35         ARMV4_5_MODE_SYS = 31,
  36         ARMV4_5_MODE_ANY = -1
  37 } armv4_5_mode_t;
  38
  39 extern char* armv4_5_mode_strings[];
  40
  41 typedef enum armv4_5_state
  42 {
  43         ARMV4_5_STATE_ARM,
  44         ARMV4_5_STATE_THUMB,
  45         ARMV4_5_STATE_JAZELLE,
  46 } armv4_5_state_t;
  47
  48 extern char* armv4_5_state_strings[];
  49
  50 extern int armv4_5_core_reg_map[7][17];
  51
  52 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  53                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  54 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
  55                 cache->reg_list[armv4_5_core_reg_map[mode][num]]
  56
  57 /* offsets into armv4_5 core register cache */
  58 enum
  59 {
  60         ARMV4_5_CPSR = 31,
  61         ARMV4_5_SPSR_FIQ = 32,
  62         ARMV4_5_SPSR_IRQ = 33,
  63         ARMV4_5_SPSR_SVC = 34,
  64         ARMV4_5_SPSR_ABT = 35,
  65         ARMV4_5_SPSR_UND = 36
  66 };
  67
  68 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  69
  70 typedef struct armv4_5_common_s
  71 {
  72         int common_magic;
  73         reg_cache_t *core_cache;
  74         enum armv4_5_mode core_mode;
  75         enum armv4_5_state core_state;
  76         int (*full_context)(struct target_s *target);
  77         int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
  78         int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
  79         void *arch_info;
  80 } armv4_5_common_t;
  81
  82 typedef struct armv4_5_algorithm_s
  83 {
  84         int common_magic;
  85
  86         enum armv4_5_mode core_mode;
  87         enum armv4_5_state core_state;
  88 } armv4_5_algorithm_t;
  89
  90 typedef struct armv4_5_core_reg_s
  91 {
  92         int num;
  93         enum armv4_5_mode mode;
  94         target_t *target;
  95         armv4_5_common_t *armv4_5_common;
  96 } armv4_5_core_reg_t;
  97
  98 extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
  99
 100 /* map psr mode bits to linear number */
 101 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 102 {
 103         switch (mode)
 104         {
 105                 case ARMV4_5_MODE_USR: return 0; break;
 106                 case ARMV4_5_MODE_FIQ: return 1; break;
 107                 case ARMV4_5_MODE_IRQ: return 2; break;
 108                 case ARMV4_5_MODE_SVC: return 3; break;
 109                 case ARMV4_5_MODE_ABT: return 4; break;
 110                 case ARMV4_5_MODE_UND: return 5; break;
 111                 case ARMV4_5_MODE_SYS: return 6; break;
 112                 case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
 113                 default:
 114                         LOG_ERROR("invalid mode value encountered");
 115                         return -1;
 116         }
 117 }
 118
 119 /* map linear number to mode bits */
 120 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 121 {
 122         switch(number)
 123         {
 124                 case 0: return ARMV4_5_MODE_USR; break;
 125                 case 1: return ARMV4_5_MODE_FIQ; break;
 126                 case 2: return ARMV4_5_MODE_IRQ; break;
 127                 case 3: return ARMV4_5_MODE_SVC; break;
 128                 case 4: return ARMV4_5_MODE_ABT; break;
 129                 case 5: return ARMV4_5_MODE_UND; break;
 130                 case 6: return ARMV4_5_MODE_SYS; break;
 131                 default:
 132                         LOG_ERROR("mode index out of bounds");
 133                         return -1;
 134         }
 135 };
 136
 137
 138 extern int armv4_5_arch_state(struct target_s *target);
 139 extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 140 extern int armv4_5_invalidate_core_regs(target_t *target);
 141
 142 extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
 143 extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
 144
 145 extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 146
 147 extern int armv4_5_invalidate_core_regs(target_t *target);
 148
 149 /* ARM mode instructions
 150  */
 151
 152 /* Store multiple increment after
 153  * Rn: base register
 154  * List: for each bit in list: store register
 155  * S: in priviledged mode: store user-mode registers
 156  * W=1: update the base register. W=0: leave the base register untouched
 157  */
 158 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 159
 160 /* Load multiple increment after
 161  * Rn: base register
 162  * List: for each bit in list: store register
 163  * S: in priviledged mode: store user-mode registers
 164  * W=1: update the base register. W=0: leave the base register untouched
 165  */
 166 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 167
 168 /* MOV r8, r8 */
 169 #define ARMV4_5_NOP                                     (0xe1a08008)
 170
 171 /* Move PSR to general purpose register
 172  * R=1: SPSR R=0: CPSR
 173  * Rn: target register
 174  */
 175 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 176
 177 /* Store register
 178  * Rd: register to store
 179  * Rn: base register
 180  */
 181 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 182
 183 /* Load register
 184  * Rd: register to load
 185  * Rn: base register
 186  */
 187 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 188
 189 /* Move general purpose register to PSR
 190  * R=1: SPSR R=0: CPSR
 191  * Field: Field mask
 192  * 1: control field 2: extension field 4: status field 8: flags field
 193  * Rm: source register
 194  */
 195 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 196 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 197
 198 /* Load Register Halfword Immediate Post-Index
 199  * Rd: register to load
 200  * Rn: base register
 201  */
 202 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 203
 204 /* Load Register Byte Immediate Post-Index
 205  * Rd: register to load
 206  * Rn: base register
 207  */
 208 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 209
 210 /* Store register Halfword Immediate Post-Index
 211  * Rd: register to store
 212  * Rn: base register
 213  */
 214 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 215
 216 /* Store register Byte Immediate Post-Index
 217  * Rd: register to store
 218  * Rn: base register
 219  */
 220 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 221
 222 /* Branch (and Link)
 223  * Im: Branch target (left-shifted by 2 bits, added to PC)
 224  * L: 1: branch and link 0: branch only
 225  */
 226 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 227
 228 /* Branch and exchange (ARM state)
 229  * Rm: register holding branch target address
 230  */
 231 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 232
 233 /* Move to ARM register from coprocessor
 234  * CP: Coprocessor number
 235  * op1: Coprocessor opcode
 236  * Rd: destination register
 237  * CRn: first coprocessor operand
 238  * CRm: second coprocessor operand
 239  * op2: Second coprocessor opcode
 240  */
 241 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 242
 243 /* Move to coprocessor from ARM register
 244  * CP: Coprocessor number
 245  * op1: Coprocessor opcode
 246  * Rd: destination register
 247  * CRn: first coprocessor operand
 248  * CRm: second coprocessor operand
 249  * op2: Second coprocessor opcode
 250  */
 251 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 252
 253 /* Breakpoint instruction (ARMv5)
 254  * Im: 16-bit immediate
 255  */
 256 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 257
 258
 259 /* Thumb mode instructions
 260  */
 261
 262 /* Store register (Thumb mode)
 263  * Rd: source register
 264  * Rn: base register
 265  */
 266 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 267
 268 /* Load register (Thumb state)
 269  * Rd: destination register
 270  * Rn: base register
 271  */
 272 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 273
 274 /* Load multiple (Thumb state)
 275  * Rn: base register
 276  * List: for each bit in list: store register
 277  */
 278 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 279
 280 /* Load register with PC relative addressing
 281  * Rd: register to load
 282  */
 283 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 284
 285 /* Move hi register (Thumb mode)
 286  * Rd: destination register
 287  * Rm: source register
 288  */
 289 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 290
 291 /* No operation (Thumb mode)
 292  */
 293 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 294
 295 /* Move immediate to register (Thumb state)
 296  * Rd: destination register
 297  * Im: 8-bit immediate value
 298  */
 299 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 300
 301 /* Branch and Exchange
 302  * Rm: register containing branch target
 303  */
 304 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 305
 306 /* Branch (Thumb state)
 307  * Imm: Branch target
 308  */
 309 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 310
 311 /* Breakpoint instruction (ARMv5) (Thumb state)
 312  * Im: 8-bit immediate
 313  */
 314 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 315
 316 #endif /* ARMV4_5_H */