1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 ***************************************************************************/
8 #ifndef OPENOCD_TARGET_ARMV4_5_MMU_H
9 #define OPENOCD_TARGET_ARMV4_5_MMU_H
11 #include "armv4_5_cache.h"
15 struct armv4_5_mmu_common
{
16 int (*get_ttb
)(struct target
*target
, uint32_t *result
);
17 int (*read_memory
)(struct target
*target
, target_addr_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
18 int (*write_memory
)(struct target
*target
, target_addr_t address
,
19 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
20 int (*disable_mmu_caches
)(struct target
*target
, int mmu
, int d_u_cache
, int i_cache
);
21 int (*enable_mmu_caches
)(struct target
*target
, int mmu
, int d_u_cache
, int i_cache
);
22 struct armv4_5_cache_common armv4_5_cache
;
27 int armv4_5_mmu_translate_va(struct target
*target
,
28 struct armv4_5_mmu_common
*armv4_5_mmu
, uint32_t va
,
29 uint32_t *cb
, uint32_t *val
);
31 int armv4_5_mmu_read_physical(struct target
*target
,
32 struct armv4_5_mmu_common
*armv4_5_mmu
,
33 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
35 int armv4_5_mmu_write_physical(struct target
*target
,
36 struct armv4_5_mmu_common
*armv4_5_mmu
,
37 uint32_t address
, uint32_t size
, uint32_t count
, const uint8_t *buffer
);
40 ARMV4_5_MMU_ENABLED
= 0x1,
41 ARMV4_5_ALIGNMENT_CHECK
= 0x2,
42 ARMV4_5_MMU_S_BIT
= 0x100,
43 ARMV4_5_MMU_R_BIT
= 0x200
46 #endif /* OPENOCD_TARGET_ARMV4_5_MMU_H */
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