#include "target.h" less wildly
[openocd.git] / src / target / armv7a.h
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
21
22 #include "arm_adi_v5.h"
23 #include "armv4_5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26
27 typedef enum armv7a_mode
28 {
29 ARMV7A_MODE_USR = 16,
30 ARMV7A_MODE_FIQ = 17,
31 ARMV7A_MODE_IRQ = 18,
32 ARMV7A_MODE_SVC = 19,
33 ARMV7A_MODE_ABT = 23,
34 ARMV7A_MODE_UND = 27,
35 ARMV7A_MODE_SYS = 31,
36 ARMV7A_MODE_MON = 22,
37 ARMV7A_MODE_ANY = -1
38 } armv7a_t;
39
40 extern char **armv7a_mode_strings;
41
42 typedef enum armv7a_state
43 {
44 ARMV7A_STATE_ARM,
45 ARMV7A_STATE_THUMB,
46 ARMV7A_STATE_JAZELLE,
47 ARMV7A_STATE_THUMBEE,
48 } armv7a_state_t;
49
50 extern char *armv7a_state_strings[];
51
52 extern int armv7a_core_reg_map[8][17];
53
54 #define ARMV7A_CORE_REG_MODE(cache, mode, num) \
55 cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
56 #define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
57 cache->reg_list[armv7a_core_reg_map[mode][num]]
58
59 enum
60 {
61 ARM_PC = 15,
62 ARM_CPSR = 16
63 }
64 ;
65 /* offsets into armv4_5 core register cache */
66 enum
67 {
68 ARMV7A_CPSR = 31,
69 ARMV7A_SPSR_FIQ = 32,
70 ARMV7A_SPSR_IRQ = 33,
71 ARMV7A_SPSR_SVC = 34,
72 ARMV7A_SPSR_ABT = 35,
73 ARMV7A_SPSR_UND = 36
74 };
75
76 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
77 #define ARMV7_COMMON_MAGIC 0x0A450999
78
79 /* VA to PA translation operations opc2 values*/
80 #define V2PCWPR 0
81 #define V2PCWPW 1
82 #define V2PCWUR 2
83 #define V2PCWUW 3
84 #define V2POWPR 4
85 #define V2POWPW 5
86 #define V2POWUR 6
87 #define V2POWUW 7
88
89 struct armv7a_common
90 {
91 int common_magic;
92 struct reg_cache *core_cache;
93 enum armv7a_mode core_mode;
94 enum armv7a_state core_state;
95
96 /* arm adp debug port */
97 struct swjdp_common swjdp_info;
98
99 /* Core Debug Unit */
100 uint32_t debug_base;
101 uint8_t debug_ap;
102 uint8_t memory_ap;
103
104 /* Cache and Memory Management Unit */
105 struct armv4_5_mmu_common armv4_5_mmu;
106 struct arm armv4_5_common;
107
108 // int (*full_context)(struct target *target);
109 // int (*read_core_reg)(struct target *target, int num, enum armv7a_mode mode);
110 // int (*write_core_reg)(struct target *target, int num, enum armv7a_mode mode, u32 value);
111 int (*read_cp15)(struct target *target,
112 uint32_t op1, uint32_t op2,
113 uint32_t CRn, uint32_t CRm, uint32_t *value);
114 int (*write_cp15)(struct target *target,
115 uint32_t op1, uint32_t op2,
116 uint32_t CRn, uint32_t CRm, uint32_t value);
117
118 int (*examine_debug_reason)(struct target *target);
119 void (*post_debug_entry)(struct target *target);
120
121 void (*pre_restore_context)(struct target *target);
122 void (*post_restore_context)(struct target *target);
123
124 };
125
126 static inline struct armv7a_common *
127 target_to_armv7a(struct target *target)
128 {
129 return container_of(target->arch_info, struct armv7a_common,
130 armv4_5_common);
131 }
132
133 struct armv7a_algorithm
134 {
135 int common_magic;
136
137 enum armv7a_mode core_mode;
138 enum armv7a_state core_state;
139 };
140
141 struct armv7a_core_reg
142 {
143 int num;
144 enum armv7a_mode mode;
145 struct target *target;
146 struct armv7a_common *armv7a_common;
147 };
148
149 int armv7a_arch_state(struct target *target);
150 struct reg_cache *armv7a_build_reg_cache(struct target *target,
151 struct armv7a_common *armv7a_common);
152 int armv7a_register_commands(struct command_context *cmd_ctx);
153 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
154
155 /* map psr mode bits to linear number */
156 static inline int armv7a_mode_to_number(enum armv7a_mode mode)
157 {
158 switch (mode)
159 {
160 case ARMV7A_MODE_USR: return 0; break;
161 case ARMV7A_MODE_FIQ: return 1; break;
162 case ARMV7A_MODE_IRQ: return 2; break;
163 case ARMV7A_MODE_SVC: return 3; break;
164 case ARMV7A_MODE_ABT: return 4; break;
165 case ARMV7A_MODE_UND: return 5; break;
166 case ARMV7A_MODE_SYS: return 6; break;
167 case ARMV7A_MODE_MON: return 7; break;
168 case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
169 default:
170 LOG_ERROR("invalid mode value encountered, val %d", mode);
171 return -1;
172 }
173 }
174
175 /* map linear number to mode bits */
176 static inline enum armv7a_mode armv7a_number_to_mode(int number)
177 {
178 switch(number)
179 {
180 case 0: return ARMV7A_MODE_USR; break;
181 case 1: return ARMV7A_MODE_FIQ; break;
182 case 2: return ARMV7A_MODE_IRQ; break;
183 case 3: return ARMV7A_MODE_SVC; break;
184 case 4: return ARMV7A_MODE_ABT; break;
185 case 5: return ARMV7A_MODE_UND; break;
186 case 6: return ARMV7A_MODE_SYS; break;
187 case 7: return ARMV7A_MODE_MON; break;
188 default:
189 LOG_ERROR("mode index out of bounds");
190 return ARMV7A_MODE_ANY;
191 }
192 };
193
194
195 #endif /* ARMV4_5_H */

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