src/target/armv7a.h

   1 /***************************************************************************
   2  *    Copyright (C) 2009 by David Brownell                                 *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef ARMV7A_H
  21 #define ARMV7A_H
  22
  23 #include "arm_adi_v5.h"
  24 #include "armv7a_cache.h"
  25 #include "arm.h"
  26 #include "armv4_5_mmu.h"
  27 #include "armv4_5_cache.h"
  28 #include "arm_dpm.h"
  29
  30 enum {
  31         ARM_PC  = 15,
  32         ARM_CPSR = 16
  33 };
  34
  35 #define ARMV7_COMMON_MAGIC 0x0A450999
  36
  37 /* VA to PA translation operations opc2 values*/
  38 #define V2PCWPR  0
  39 #define V2PCWPW  1
  40 #define V2PCWUR  2
  41 #define V2PCWUW  3
  42 #define V2POWPR  4
  43 #define V2POWPW  5
  44 #define V2POWUR  6
  45 #define V2POWUW  7
  46 /*   L210/L220 cache controller support */
  47 struct armv7a_l2x_cache {
  48         uint32_t base;
  49         uint32_t way;
  50 };
  51
  52 struct armv7a_cachesize {
  53         uint32_t level_num;
  54         /*  cache dimensionning */
  55         uint32_t linelen;
  56         uint32_t associativity;
  57         uint32_t nsets;
  58         uint32_t cachesize;
  59         /* info for set way operation on cache */
  60         uint32_t index;
  61         uint32_t index_shift;
  62         uint32_t way;
  63         uint32_t way_shift;
  64 };
  65
  66 /* information about one architecture cache at any level */
  67 struct armv7a_arch_cache {
  68         int ctype;                              /* cache type, CLIDR encoding */
  69         struct armv7a_cachesize d_u_size;       /* data cache */
  70         struct armv7a_cachesize i_size;         /* instruction cache */
  71 };
  72
  73 /* common cache information */
  74 struct armv7a_cache_common {
  75         int info;                               /* -1 invalid, else valid */
  76         int loc;                                /* level of coherency */
  77         uint32_t dminline;                      /* minimum d-cache linelen */
  78         uint32_t iminline;                      /* minimum i-cache linelen */
  79         struct armv7a_arch_cache arch[6];       /* cache info, L1 - L7 */
  80         int i_cache_enabled;
  81         int d_u_cache_enabled;
  82         int auto_cache_enabled;                 /* openocd automatic
  83                                                  * cache handling */
  84         /* outer unified cache if some */
  85         void *outer_cache;
  86         int (*flush_all_data_cache)(struct target *target);
  87 };
  88
  89 struct armv7a_mmu_common {
  90         /* following field mmu working way */
  91         int32_t cached;     /* 0: not initialized, 1: initialized */
  92         uint32_t ttbcr;     /* cache for ttbcr register */
  93         uint32_t ttbr_mask[2];
  94         uint32_t ttbr_range[2];
  95
  96         int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
  97                         uint32_t count, uint8_t *buffer);
  98         struct armv7a_cache_common armv7a_cache;
  99         uint32_t mmu_enabled;
 100 };
 101
 102 struct armv7a_common {
 103         struct arm arm;
 104         int common_magic;
 105         struct reg_cache *core_cache;
 106
 107         /* Core Debug Unit */
 108         struct arm_dpm dpm;
 109         uint32_t debug_base;
 110         uint8_t debug_ap;
 111         uint8_t memory_ap;
 112         bool memory_ap_available;
 113         /* mdir */
 114         uint8_t multi_processor_system;
 115         uint8_t cluster_id;
 116         uint8_t cpu_id;
 117         bool is_armv7r;
 118         uint32_t rev;
 119         uint32_t partnum;
 120         uint32_t arch;
 121         uint32_t variant;
 122         uint32_t implementor;
 123
 124         /* cache specific to V7 Memory Management Unit compatible with v4_5*/
 125         struct armv7a_mmu_common armv7a_mmu;
 126
 127         int (*examine_debug_reason)(struct target *target);
 128         int (*post_debug_entry)(struct target *target);
 129
 130         void (*pre_restore_context)(struct target *target);
 131 };
 132
 133 static inline struct armv7a_common *
 134 target_to_armv7a(struct target *target)
 135 {
 136         return container_of(target->arch_info, struct armv7a_common, arm);
 137 }
 138
 139 /* register offsets from armv7a.debug_base */
 140
 141 /* See ARMv7a arch spec section C10.2 */
 142 #define CPUDBG_DIDR             0x000
 143
 144 /* See ARMv7a arch spec section C10.3 */
 145 #define CPUDBG_WFAR             0x018
 146 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
 147 #define CPUDBG_DSCR             0x088
 148 #define CPUDBG_DRCR             0x090
 149 #define CPUDBG_PRCR             0x310
 150 #define CPUDBG_PRSR             0x314
 151
 152 /* See ARMv7a arch spec section C10.4 */
 153 #define CPUDBG_DTRRX            0x080
 154 #define CPUDBG_ITR              0x084
 155 #define CPUDBG_DTRTX            0x08c
 156
 157 /* See ARMv7a arch spec section C10.5 */
 158 #define CPUDBG_BVR_BASE         0x100
 159 #define CPUDBG_BCR_BASE         0x140
 160 #define CPUDBG_WVR_BASE         0x180
 161 #define CPUDBG_WCR_BASE         0x1C0
 162 #define CPUDBG_VCR              0x01C
 163
 164 /* See ARMv7a arch spec section C10.6 */
 165 #define CPUDBG_OSLAR            0x300
 166 #define CPUDBG_OSLSR            0x304
 167 #define CPUDBG_OSSRR            0x308
 168 #define CPUDBG_ECR              0x024
 169
 170 /* See ARMv7a arch spec section C10.7 */
 171 #define CPUDBG_DSCCR            0x028
 172 #define CPUDBG_DSMCR            0x02C
 173
 174 /* See ARMv7a arch spec section C10.8 */
 175 #define CPUDBG_AUTHSTATUS       0xFB8
 176
 177 int armv7a_arch_state(struct target *target);
 178 int armv7a_identify_cache(struct target *target);
 179 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 180 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
 181                 uint32_t *val, int meminfo);
 182 int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val);
 183
 184 int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 185                 struct armv7a_cache_common *armv7a_cache);
 186
 187 extern const struct command_registration armv7a_command_handlers[];
 188
 189 #endif /* ARMV4_5_H */