ARM: add arm_mode_name()
[openocd.git] / src / target / armv7a.h
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
21
22 #include "arm_adi_v5.h"
23 #include "armv4_5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26
27 typedef enum armv7a_mode
28 {
29 ARMV7A_MODE_USR = 16,
30 ARMV7A_MODE_FIQ = 17,
31 ARMV7A_MODE_IRQ = 18,
32 ARMV7A_MODE_SVC = 19,
33 ARMV7A_MODE_ABT = 23,
34 ARMV7A_MODE_UND = 27,
35 ARMV7A_MODE_SYS = 31,
36 ARMV7A_MODE_MON = 22,
37 ARMV7A_MODE_ANY = -1
38 } armv7a_t;
39
40 typedef enum armv7a_state
41 {
42 ARMV7A_STATE_ARM,
43 ARMV7A_STATE_THUMB,
44 ARMV7A_STATE_JAZELLE,
45 ARMV7A_STATE_THUMBEE,
46 } armv7a_state_t;
47
48 extern char *armv7a_state_strings[];
49
50 extern int armv7a_core_reg_map[8][17];
51
52 #define ARMV7A_CORE_REG_MODE(cache, mode, num) \
53 cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
54 #define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
55 cache->reg_list[armv7a_core_reg_map[mode][num]]
56
57 enum
58 {
59 ARM_PC = 15,
60 ARM_CPSR = 16
61 }
62 ;
63 /* offsets into armv4_5 core register cache */
64 enum
65 {
66 ARMV7A_CPSR = 31,
67 ARMV7A_SPSR_FIQ = 32,
68 ARMV7A_SPSR_IRQ = 33,
69 ARMV7A_SPSR_SVC = 34,
70 ARMV7A_SPSR_ABT = 35,
71 ARMV7A_SPSR_UND = 36
72 };
73
74 #define ARMV7_COMMON_MAGIC 0x0A450999
75
76 /* VA to PA translation operations opc2 values*/
77 #define V2PCWPR 0
78 #define V2PCWPW 1
79 #define V2PCWUR 2
80 #define V2PCWUW 3
81 #define V2POWPR 4
82 #define V2POWPW 5
83 #define V2POWUR 6
84 #define V2POWUW 7
85
86 struct armv7a_common
87 {
88 int common_magic;
89 struct reg_cache *core_cache;
90 enum armv7a_mode core_mode;
91 enum armv7a_state core_state;
92
93 /* arm adp debug port */
94 struct swjdp_common swjdp_info;
95
96 /* Core Debug Unit */
97 uint32_t debug_base;
98 uint8_t debug_ap;
99 uint8_t memory_ap;
100
101 /* Cache and Memory Management Unit */
102 struct armv4_5_mmu_common armv4_5_mmu;
103 struct arm armv4_5_common;
104
105 // int (*full_context)(struct target *target);
106 // int (*read_core_reg)(struct target *target, int num, enum armv7a_mode mode);
107 // int (*write_core_reg)(struct target *target, int num, enum armv7a_mode mode, u32 value);
108 int (*read_cp15)(struct target *target,
109 uint32_t op1, uint32_t op2,
110 uint32_t CRn, uint32_t CRm, uint32_t *value);
111 int (*write_cp15)(struct target *target,
112 uint32_t op1, uint32_t op2,
113 uint32_t CRn, uint32_t CRm, uint32_t value);
114
115 int (*examine_debug_reason)(struct target *target);
116 void (*post_debug_entry)(struct target *target);
117
118 void (*pre_restore_context)(struct target *target);
119 void (*post_restore_context)(struct target *target);
120
121 };
122
123 static inline struct armv7a_common *
124 target_to_armv7a(struct target *target)
125 {
126 return container_of(target->arch_info, struct armv7a_common,
127 armv4_5_common);
128 }
129
130 struct armv7a_algorithm
131 {
132 int common_magic;
133
134 enum armv7a_mode core_mode;
135 enum armv7a_state core_state;
136 };
137
138 struct armv7a_core_reg
139 {
140 int num;
141 enum armv7a_mode mode;
142 struct target *target;
143 struct armv7a_common *armv7a_common;
144 };
145
146 int armv7a_arch_state(struct target *target);
147 struct reg_cache *armv7a_build_reg_cache(struct target *target,
148 struct armv7a_common *armv7a_common);
149 int armv7a_register_commands(struct command_context *cmd_ctx);
150 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
151
152 /* map psr mode bits to linear number */
153 static inline int armv7a_mode_to_number(enum armv7a_mode mode)
154 {
155 switch (mode)
156 {
157 case ARMV7A_MODE_USR: return 0; break;
158 case ARMV7A_MODE_FIQ: return 1; break;
159 case ARMV7A_MODE_IRQ: return 2; break;
160 case ARMV7A_MODE_SVC: return 3; break;
161 case ARMV7A_MODE_ABT: return 4; break;
162 case ARMV7A_MODE_UND: return 5; break;
163 case ARMV7A_MODE_SYS: return 6; break;
164 case ARMV7A_MODE_MON: return 7; break;
165 case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
166 default:
167 LOG_ERROR("invalid mode value encountered, val %d", mode);
168 return -1;
169 }
170 }
171
172 /* map linear number to mode bits */
173 static inline enum armv7a_mode armv7a_number_to_mode(int number)
174 {
175 switch(number)
176 {
177 case 0: return ARMV7A_MODE_USR; break;
178 case 1: return ARMV7A_MODE_FIQ; break;
179 case 2: return ARMV7A_MODE_IRQ; break;
180 case 3: return ARMV7A_MODE_SVC; break;
181 case 4: return ARMV7A_MODE_ABT; break;
182 case 5: return ARMV7A_MODE_UND; break;
183 case 6: return ARMV7A_MODE_SYS; break;
184 case 7: return ARMV7A_MODE_MON; break;
185 default:
186 LOG_ERROR("mode index out of bounds");
187 return ARMV7A_MODE_ANY;
188 }
189 };
190
191
192 #endif /* ARMV4_5_H */

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