ARMv7-A: use standard ARM core states
[openocd.git] / src / target / armv7a.h
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
21
22 #include "arm_adi_v5.h"
23 #include "armv4_5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26
27 enum
28 {
29 ARM_PC = 15,
30 ARM_CPSR = 16
31 }
32 ;
33 /* offsets into armv4_5 core register cache */
34 enum
35 {
36 ARMV7A_CPSR = 31,
37 ARMV7A_SPSR_FIQ = 32,
38 ARMV7A_SPSR_IRQ = 33,
39 ARMV7A_SPSR_SVC = 34,
40 ARMV7A_SPSR_ABT = 35,
41 ARMV7A_SPSR_UND = 36
42 };
43
44 #define ARMV7_COMMON_MAGIC 0x0A450999
45
46 /* VA to PA translation operations opc2 values*/
47 #define V2PCWPR 0
48 #define V2PCWPW 1
49 #define V2PCWUR 2
50 #define V2PCWUW 3
51 #define V2POWPR 4
52 #define V2POWPW 5
53 #define V2POWUR 6
54 #define V2POWUW 7
55
56 struct armv7a_common
57 {
58 struct arm armv4_5_common;
59 int common_magic;
60 struct reg_cache *core_cache;
61
62 /* arm adp debug port */
63 struct swjdp_common swjdp_info;
64
65 /* Core Debug Unit */
66 uint32_t debug_base;
67 uint8_t debug_ap;
68 uint8_t memory_ap;
69
70 /* Cache and Memory Management Unit */
71 struct armv4_5_mmu_common armv4_5_mmu;
72
73 int (*read_cp15)(struct target *target,
74 uint32_t op1, uint32_t op2,
75 uint32_t CRn, uint32_t CRm, uint32_t *value);
76 int (*write_cp15)(struct target *target,
77 uint32_t op1, uint32_t op2,
78 uint32_t CRn, uint32_t CRm, uint32_t value);
79
80 int (*examine_debug_reason)(struct target *target);
81 void (*post_debug_entry)(struct target *target);
82
83 void (*pre_restore_context)(struct target *target);
84 void (*post_restore_context)(struct target *target);
85
86 };
87
88 static inline struct armv7a_common *
89 target_to_armv7a(struct target *target)
90 {
91 return container_of(target->arch_info, struct armv7a_common,
92 armv4_5_common);
93 }
94
95 struct armv7a_algorithm
96 {
97 int common_magic;
98
99 enum armv4_5_mode core_mode;
100 enum armv4_5_state core_state;
101 };
102
103 struct armv7a_core_reg
104 {
105 int num;
106 enum armv4_5_mode mode;
107 struct target *target;
108 struct armv7a_common *armv7a_common;
109 };
110
111 int armv7a_arch_state(struct target *target);
112 struct reg_cache *armv7a_build_reg_cache(struct target *target,
113 struct armv7a_common *armv7a_common);
114 int armv7a_register_commands(struct command_context *cmd_ctx);
115 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
116
117 #endif /* ARMV4_5_H */

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