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- added str912 test example, and test result
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "armv7m.h"
30 #include "register.h"
31 #include "target.h"
32 #include "log.h"
33 #include "jtag.h"
34 #include "arm_jtag.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 char* armv7m_mode_strings[] =
44 {
45 "Handler", "Thread"
46 };
47
48 char* armv7m_state_strings[] =
49 {
50 "Thumb", "Debug"
51 };
52
53 char* armv7m_exception_strings[] =
54 {
55 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
56 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
57 };
58
59 char* armv7m_core_reg_list[] =
60 {
61 /* Registers accessed through core debug */
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
63 "sp", "lr", "pc",
64 "xPSR", "msp", "psp",
65 /* Registers accessed through MSR instructions */
66 // "apsr", "iapsr", "ipsr", "epsr",
67 "primask", "basepri", "faultmask", "control"
68 };
69
70 char* armv7m_core_dbgreg_list[] =
71 {
72 /* Registers accessed through core debug */
73 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
74 "sp", "lr", "pc",
75 "xPSR", "msp", "psp",
76 /* Registers accessed through MSR instructions */
77 // "dbg_apsr", "iapsr", "ipsr", "epsr",
78 "primask", "basepri", "faultmask", "dbg_control"
79 };
80
81 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
82
83 reg_t armv7m_gdb_dummy_fp_reg =
84 {
85 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
86 };
87
88 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
89 {
90 /* CORE_GP are accesible using the core debug registers */
91 {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
92 {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
93 {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
94 {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
95 {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
96 {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
97 {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
98 {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
99 {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
100 {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
101 {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
102 {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
103 {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
104 {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
105 {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
106 {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
107
108 {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
109 {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
110 {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
111
112 /* CORE_SP are accesible using MSR and MRS instructions */
113 // {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
114 // {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
115 // {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
116 // {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
117
118 {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
119 {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
120 {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
121 {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
122 };
123
124 int armv7m_core_reg_arch_type = -1;
125
126 /* Keep different contexts for the process being debugged and debug algorithms */
127 enum armv7m_runcontext armv7m_get_context(target_t *target)
128 {
129 /* get pointers to arch-specific information */
130 armv7m_common_t *armv7m = target->arch_info;
131
132 if (armv7m->process_context == armv7m->core_cache)
133 return ARMV7M_PROCESS_CONTEXT;
134 if (armv7m->debug_context == armv7m->core_cache)
135 return ARMV7M_DEBUG_CONTEXT;
136
137 ERROR("Invalid runcontext");
138 exit(-1);
139 }
140
141 int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
142 {
143 int i;
144 /* get pointers to arch-specific information */
145 armv7m_common_t *armv7m = target->arch_info;
146
147 if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
148 {
149 WARNING("target not halted, switch context ");
150 return ERROR_TARGET_NOT_HALTED;
151 }
152
153 if (new_ctx == armv7m_get_context(target))
154 return ERROR_OK;
155
156 switch (new_ctx)
157 {
158 case ARMV7M_PROCESS_CONTEXT:
159 armv7m->core_cache = armv7m->process_context;
160 break;
161 case ARMV7M_DEBUG_CONTEXT:
162 armv7m->core_cache = armv7m->debug_context;
163 break;
164 default:
165 ERROR("Invalid runcontext");
166 exit(-1);
167 }
168 /* Mark registers in new context as dirty to force reload when run */
169
170 for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
171 {
172 armv7m->core_cache->reg_list[i].dirty = 1;
173 }
174
175 return ERROR_OK;
176 }
177
178 int armv7m_restore_context(target_t *target)
179 {
180 int i;
181
182 /* get pointers to arch-specific information */
183 armv7m_common_t *armv7m = target->arch_info;
184
185 DEBUG(" ");
186
187 if (armv7m->pre_restore_context)
188 armv7m->pre_restore_context(target);
189
190 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
191 {
192 if (armv7m->core_cache->reg_list[i].dirty)
193 {
194 armv7m->write_core_reg(target, i);
195 }
196 }
197
198 if (armv7m->post_restore_context)
199 armv7m->post_restore_context(target);
200
201 return ERROR_OK;
202 }
203
204
205 /* Core state functions */
206 char enamebuf[32];
207 char *armv7m_exception_string(int number)
208 {
209 if ((number < 0) | (number > 511))
210 return "Invalid exception";
211 if (number < 16)
212 return armv7m_exception_strings[number];
213 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
214 return enamebuf;
215 }
216
217 int armv7m_get_core_reg(reg_t *reg)
218 {
219 int retval;
220 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
221 target_t *target = armv7m_reg->target;
222 armv7m_common_t *armv7m_target = target->arch_info;
223
224 if (target->state != TARGET_HALTED)
225 {
226 return ERROR_TARGET_NOT_HALTED;
227 }
228
229 retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
230
231 return retval;
232 }
233
234 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
235 {
236 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
237 target_t *target = armv7m_reg->target;
238 u32 value = buf_get_u32(buf, 0, 32);
239
240 if (target->state != TARGET_HALTED)
241 {
242 return ERROR_TARGET_NOT_HALTED;
243 }
244
245 buf_set_u32(reg->value, 0, 32, value);
246 reg->dirty = 1;
247 reg->valid = 1;
248
249 return ERROR_OK;
250 }
251
252 int armv7m_read_core_reg(struct target_s *target, int num)
253 {
254 u32 reg_value;
255 int retval;
256 armv7m_core_reg_t * armv7m_core_reg;
257
258 /* get pointers to arch-specific information */
259 armv7m_common_t *armv7m = target->arch_info;
260
261 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
262 return ERROR_INVALID_ARGUMENTS;
263
264 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
265 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
266 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
267 armv7m->core_cache->reg_list[num].valid = 1;
268 armv7m->core_cache->reg_list[num].dirty = 0;
269
270 return ERROR_OK;
271 }
272
273 int armv7m_write_core_reg(struct target_s *target, int num)
274 {
275 int retval;
276 u32 reg_value;
277 armv7m_core_reg_t *armv7m_core_reg;
278
279 /* get pointers to arch-specific information */
280 armv7m_common_t *armv7m = target->arch_info;
281
282 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
283 return ERROR_INVALID_ARGUMENTS;
284
285 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
286 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
287 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
288 if (retval != ERROR_OK)
289 {
290 ERROR("JTAG failure");
291 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
292 return ERROR_JTAG_DEVICE_ERROR;
293 }
294 DEBUG("write core reg %i value 0x%x", num , reg_value);
295 armv7m->core_cache->reg_list[num].valid = 1;
296 armv7m->core_cache->reg_list[num].dirty = 0;
297
298 return ERROR_OK;
299 }
300
301 int armv7m_invalidate_core_regs(target_t *target)
302 {
303 /* get pointers to arch-specific information */
304 armv7m_common_t *armv7m = target->arch_info;
305 int i;
306
307 for (i = 0; i < armv7m->core_cache->num_regs; i++)
308 {
309 armv7m->core_cache->reg_list[i].valid = 0;
310 armv7m->core_cache->reg_list[i].dirty = 0;
311 }
312
313 return ERROR_OK;
314 }
315
316 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
317 {
318 /* get pointers to arch-specific information */
319 armv7m_common_t *armv7m = target->arch_info;
320 int i;
321
322 if (target->state != TARGET_HALTED)
323 {
324 return ERROR_TARGET_NOT_HALTED;
325 }
326
327 *reg_list_size = 26;
328 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
329
330 /* TODOLATER correct list of registers, names ? */
331 for (i = 0; i < *reg_list_size; i++)
332 {
333 if (i < ARMV7NUMCOREREGS)
334 (*reg_list)[i] = &armv7m->process_context->reg_list[i];
335 //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
336 else
337 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
338 }
339 /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
340 armv7m->process_context->reg_list[15].value[0] |= 1;
341 (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
342 return ERROR_OK;
343 }
344
345 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
346 {
347 // get pointers to arch-specific information
348 armv7m_common_t *armv7m = target->arch_info;
349 armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
350 enum armv7m_state core_state = armv7m->core_state;
351 enum armv7m_mode core_mode = armv7m->core_mode;
352 int retval = ERROR_OK;
353 u32 pc;
354 int exit_breakpoint_size = 0;
355 int i;
356
357 armv7m->core_state = core_state;
358 armv7m->core_mode = core_mode;
359
360 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
361 {
362 ERROR("current target isn't an ARMV7M target");
363 return ERROR_TARGET_INVALID;
364 }
365
366 if (target->state != TARGET_HALTED)
367 {
368 WARNING("target not halted");
369 return ERROR_TARGET_NOT_HALTED;
370 }
371
372 /* refresh core register cache */
373 /* Not needed if core register cache is always consistent with target process state */
374 armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
375
376 for (i = 0; i < num_mem_params; i++)
377 {
378 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
379 }
380
381 for (i = 0; i < num_reg_params; i++)
382 {
383 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
384 u32 regvalue;
385
386 if (!reg)
387 {
388 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
389 exit(-1);
390 }
391
392 if (reg->size != reg_params[i].size)
393 {
394 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
395 exit(-1);
396 }
397
398 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
399 armv7m_set_core_reg(reg, reg_params[i].value);
400 }
401
402 /* ARMV7M always runs in Thumb state */
403 exit_breakpoint_size = 2;
404 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
405 {
406 ERROR("can't add breakpoint to finish algorithm execution");
407 return ERROR_TARGET_FAILURE;
408 }
409
410 /* This code relies on the target specific resume() and poll()->debug_entry()
411 sequence to write register values to the processor and the read them back */
412 target->type->resume(target, 0, entry_point, 1, 1);
413 target->type->poll(target);
414
415 while (target->state != TARGET_HALTED)
416 {
417 usleep(5000);
418 target->type->poll(target);
419 if ((timeout_ms -= 5) <= 0)
420 {
421 ERROR("timeout waiting for algorithm to complete, trying to halt target");
422 target->type->halt(target);
423 timeout_ms = 1000;
424 while (target->state != TARGET_HALTED)
425 {
426 usleep(10000);
427 target->type->poll(target);
428 if ((timeout_ms -= 10) <= 0)
429 {
430 ERROR("target didn't reenter debug state, exiting");
431 exit(-1);
432 }
433 }
434 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
435 DEBUG("failed algoritm halted at 0x%x ", pc);
436 retval = ERROR_TARGET_TIMEOUT;
437 }
438 }
439
440 breakpoint_remove(target, exit_point);
441
442 /* Read memory values to mem_params[] */
443 for (i = 0; i < num_mem_params; i++)
444 {
445 if (mem_params[i].direction != PARAM_OUT)
446 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
447 }
448
449 /* Copy core register values to reg_params[] */
450 for (i = 0; i < num_reg_params; i++)
451 {
452 if (reg_params[i].direction != PARAM_OUT)
453 {
454 reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
455
456 if (!reg)
457 {
458 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
459 exit(-1);
460 }
461
462 if (reg->size != reg_params[i].size)
463 {
464 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
465 exit(-1);
466 }
467
468 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
469 }
470 }
471
472 return retval;
473 }
474
475 int armv7m_arch_state(struct target_s *target)
476 {
477 /* get pointers to arch-specific information */
478 armv7m_common_t *armv7m = target->arch_info;
479
480 USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
481 armv7m_state_strings[armv7m->core_state],
482 target_debug_reason_strings[target->debug_reason],
483 armv7m_mode_strings[armv7m->core_mode],
484 armv7m_exception_string(armv7m->exception_number),
485 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
486 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
487
488 return ERROR_OK;
489 }
490
491 reg_cache_t *armv7m_build_reg_cache(target_t *target)
492 {
493 /* get pointers to arch-specific information */
494 armv7m_common_t *armv7m = target->arch_info;
495
496 int num_regs = ARMV7NUMCOREREGS;
497 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
498 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
499 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
500 armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
501 int i;
502
503 if (armv7m_core_reg_arch_type == -1)
504 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
505
506 /* Build the process context cache */
507 cache->name = "arm v7m registers";
508 cache->next = NULL;
509 cache->reg_list = reg_list;
510 cache->num_regs = num_regs;
511 (*cache_p) = cache;
512 armv7m->core_cache = cache;
513 armv7m->process_context = cache;
514
515 for (i = 0; i < num_regs; i++)
516 {
517 arch_info[i] = armv7m_core_reg_list_arch_info[i];
518 arch_info[i].target = target;
519 arch_info[i].armv7m_common = armv7m;
520 reg_list[i].name = armv7m_core_reg_list[i];
521 reg_list[i].size = 32;
522 reg_list[i].value = calloc(1, 4);
523 reg_list[i].dirty = 0;
524 reg_list[i].valid = 0;
525 reg_list[i].bitfield_desc = NULL;
526 reg_list[i].num_bitfields = 0;
527 reg_list[i].arch_type = armv7m_core_reg_arch_type;
528 reg_list[i].arch_info = &arch_info[i];
529 }
530
531 /* Build the debug context cache*/
532 cache = malloc(sizeof(reg_cache_t));
533 reg_list = malloc(sizeof(reg_t) * num_regs);
534
535 cache->name = "arm v7m debug registers";
536 cache->next = NULL;
537 cache->reg_list = reg_list;
538 cache->num_regs = num_regs;
539 armv7m->debug_context = cache;
540 armv7m->process_context->next = cache;
541
542 for (i = 0; i < num_regs; i++)
543 {
544 reg_list[i].name = armv7m_core_dbgreg_list[i];
545 reg_list[i].size = 32;
546 reg_list[i].value = calloc(1, 4);
547 reg_list[i].dirty = 0;
548 reg_list[i].valid = 0;
549 reg_list[i].bitfield_desc = NULL;
550 reg_list[i].num_bitfields = 0;
551 reg_list[i].arch_type = armv7m_core_reg_arch_type;
552 reg_list[i].arch_info = &arch_info[i];
553 }
554
555 return cache;
556 }
557
558 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
559 {
560 armv7m_build_reg_cache(target);
561
562 return ERROR_OK;
563 }
564
565 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
566 {
567 /* register arch-specific functions */
568
569 target->arch_info = armv7m;
570 armv7m->core_state = ARMV7M_STATE_THUMB;
571 armv7m->read_core_reg = armv7m_read_core_reg;
572 armv7m->write_core_reg = armv7m_write_core_reg;
573
574 return ERROR_OK;
575 }
576
577 int armv7m_register_commands(struct command_context_s *cmd_ctx)
578 {
579 return ERROR_OK;
580 }
581
582 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
583 {
584 working_area_t *crc_algorithm;
585 armv7m_algorithm_t armv7m_info;
586 reg_param_t reg_params[2];
587 int retval;
588
589 u16 cortex_m3_crc_code[] = {
590 0x4602, /* mov r2, r0 */
591 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
592 0x460B, /* mov r3, r1 */
593 0xF04F, 0x0400, /* mov r4, #0 */
594 0xE013, /* b ncomp */
595 /* nbyte: */
596 0x5D11, /* ldrb r1, [r2, r4] */
597 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
598 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
599
600 0xF04F, 0x0500, /* mov r5, #0 */
601 /* loop: */
602 0x2800, /* cmp r0, #0 */
603 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
604 0xF105, 0x0501, /* add r5, r5, #1 */
605 0x4630, /* mov r0, r6 */
606 0xBFB8, /* it lt */
607 0xEA86, 0x0007, /* eor r0, r6, r7 */
608 0x2D08, /* cmp r5, #8 */
609 0xD1F4, /* bne loop */
610
611 0xF104, 0x0401, /* add r4, r4, #1 */
612 /* ncomp: */
613 0x429C, /* cmp r4, r3 */
614 0xD1E9, /* bne nbyte */
615 /* end: */
616 0xE7FE, /* b end */
617 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
618 };
619
620 int i;
621
622 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
623 {
624 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
625 }
626
627 /* convert flash writing code into a buffer in target endianness */
628 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
629 target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
630
631 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
632 armv7m_info.core_mode = ARMV7M_MODE_ANY;
633 armv7m_info.core_state = ARMV7M_STATE_THUMB;
634
635 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
636 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
637
638 buf_set_u32(reg_params[0].value, 0, 32, address);
639 buf_set_u32(reg_params[1].value, 0, 32, count);
640
641 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
642 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
643 {
644 ERROR("error executing cortex_m3 crc algorithm");
645 destroy_reg_param(&reg_params[0]);
646 destroy_reg_param(&reg_params[1]);
647 target_free_working_area(target, crc_algorithm);
648 return retval;
649 }
650
651 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
652
653 destroy_reg_param(&reg_params[0]);
654 destroy_reg_param(&reg_params[1]);
655
656 target_free_working_area(target, crc_algorithm);
657
658 return ERROR_OK;
659 }
660
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