89157113ff7d10b97b9ae9bfcc8ed883f5e0929b
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 √ėyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
31 * *
32 ***************************************************************************/
33
34 #ifdef HAVE_CONFIG_H
35 #include "config.h"
36 #endif
37
38 #include "breakpoints.h"
39 #include "armv7m.h"
40 #include "algorithm.h"
41 #include "register.h"
42
43 #if 0
44 #define _DEBUG_INSTRUCTION_EXECUTION_
45 #endif
46
47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
48 char *armv7m_mode_strings[] = {
49 "Thread", "Thread (User)", "Handler",
50 };
51
52 static char *armv7m_exception_strings[] = {
53 "", "Reset", "NMI", "HardFault",
54 "MemManage", "BusFault", "UsageFault", "RESERVED",
55 "RESERVED", "RESERVED", "RESERVED", "SVCall",
56 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
57 };
58
59 /* PSP is used in some thread modes */
60 const int armv7m_psp_reg_map[17] = {
61 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
62 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
63 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
64 ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
65 ARMV7M_xPSR,
66 };
67
68 /* MSP is used in handler and some thread modes */
69 const int armv7m_msp_reg_map[17] = {
70 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
71 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
72 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
73 ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
74 ARMV7M_xPSR,
75 };
76
77 #ifdef ARMV7_GDB_HACKS
78 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
79
80 struct reg armv7m_gdb_dummy_cpsr_reg = {
81 .name = "GDB dummy cpsr register",
82 .value = armv7m_gdb_dummy_cpsr_value,
83 .dirty = 0,
84 .valid = 1,
85 .size = 32,
86 .arch_info = NULL,
87 };
88 #endif
89
90 /*
91 * These registers are not memory-mapped. The ARMv7-M profile includes
92 * memory mapped registers too, such as for the NVIC (interrupt controller)
93 * and SysTick (timer) modules; those can mostly be treated as peripherals.
94 *
95 * The ARMv6-M profile is almost identical in this respect, except that it
96 * doesn't include basepri or faultmask registers.
97 */
98 static const struct {
99 unsigned id;
100 const char *name;
101 unsigned bits;
102 } armv7m_regs[] = {
103 { ARMV7M_R0, "r0", 32 },
104 { ARMV7M_R1, "r1", 32 },
105 { ARMV7M_R2, "r2", 32 },
106 { ARMV7M_R3, "r3", 32 },
107
108 { ARMV7M_R4, "r4", 32 },
109 { ARMV7M_R5, "r5", 32 },
110 { ARMV7M_R6, "r6", 32 },
111 { ARMV7M_R7, "r7", 32 },
112
113 { ARMV7M_R8, "r8", 32 },
114 { ARMV7M_R9, "r9", 32 },
115 { ARMV7M_R10, "r10", 32 },
116 { ARMV7M_R11, "r11", 32 },
117
118 { ARMV7M_R12, "r12", 32 },
119 { ARMV7M_R13, "sp", 32 },
120 { ARMV7M_R14, "lr", 32 },
121 { ARMV7M_PC, "pc", 32 },
122
123 { ARMV7M_xPSR, "xPSR", 32 },
124 { ARMV7M_MSP, "msp", 32 },
125 { ARMV7M_PSP, "psp", 32 },
126
127 { ARMV7M_PRIMASK, "primask", 1 },
128 { ARMV7M_BASEPRI, "basepri", 8 },
129 { ARMV7M_FAULTMASK, "faultmask", 1 },
130 { ARMV7M_CONTROL, "control", 2 },
131 };
132
133 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
134
135 /**
136 * Restores target context using the cache of core registers set up
137 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
138 */
139 int armv7m_restore_context(struct target *target)
140 {
141 int i;
142 struct armv7m_common *armv7m = target_to_armv7m(target);
143
144 LOG_DEBUG(" ");
145
146 if (armv7m->pre_restore_context)
147 armv7m->pre_restore_context(target);
148
149 for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
150 if (armv7m->core_cache->reg_list[i].dirty)
151 armv7m->write_core_reg(target, i);
152 }
153
154 return ERROR_OK;
155 }
156
157 /* Core state functions */
158
159 /**
160 * Maps ISR number (from xPSR) to name.
161 * Note that while names and meanings for the first sixteen are standardized
162 * (with zero not a true exception), external interrupts are only numbered.
163 * They are assigned by vendors, which generally assign different numbers to
164 * peripherals (such as UART0 or a USB peripheral controller).
165 */
166 char *armv7m_exception_string(int number)
167 {
168 static char enamebuf[32];
169
170 if ((number < 0) | (number > 511))
171 return "Invalid exception";
172 if (number < 16)
173 return armv7m_exception_strings[number];
174 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
175 return enamebuf;
176 }
177
178 static int armv7m_get_core_reg(struct reg *reg)
179 {
180 int retval;
181 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
182 struct target *target = armv7m_reg->target;
183 struct armv7m_common *armv7m = target_to_armv7m(target);
184
185 if (target->state != TARGET_HALTED)
186 return ERROR_TARGET_NOT_HALTED;
187
188 retval = armv7m->read_core_reg(target, armv7m_reg->num);
189
190 return retval;
191 }
192
193 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
194 {
195 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
196 struct target *target = armv7m_reg->target;
197 uint32_t value = buf_get_u32(buf, 0, 32);
198
199 if (target->state != TARGET_HALTED)
200 return ERROR_TARGET_NOT_HALTED;
201
202 buf_set_u32(reg->value, 0, 32, value);
203 reg->dirty = 1;
204 reg->valid = 1;
205
206 return ERROR_OK;
207 }
208
209 static int armv7m_read_core_reg(struct target *target, unsigned num)
210 {
211 uint32_t reg_value;
212 int retval;
213 struct armv7m_core_reg *armv7m_core_reg;
214 struct armv7m_common *armv7m = target_to_armv7m(target);
215
216 if (num >= ARMV7M_NUM_REGS)
217 return ERROR_COMMAND_SYNTAX_ERROR;
218
219 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
220 retval = armv7m->load_core_reg_u32(target,
221 armv7m_core_reg->type,
222 armv7m_core_reg->num,
223 &reg_value);
224 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
225 armv7m->core_cache->reg_list[num].valid = 1;
226 armv7m->core_cache->reg_list[num].dirty = 0;
227
228 return retval;
229 }
230
231 static int armv7m_write_core_reg(struct target *target, unsigned num)
232 {
233 int retval;
234 uint32_t reg_value;
235 struct armv7m_core_reg *armv7m_core_reg;
236 struct armv7m_common *armv7m = target_to_armv7m(target);
237
238 if (num >= ARMV7M_NUM_REGS)
239 return ERROR_COMMAND_SYNTAX_ERROR;
240
241 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
242 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
243 retval = armv7m->store_core_reg_u32(target,
244 armv7m_core_reg->type,
245 armv7m_core_reg->num,
246 reg_value);
247 if (retval != ERROR_OK) {
248 LOG_ERROR("JTAG failure");
249 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
250 return ERROR_JTAG_DEVICE_ERROR;
251 }
252 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
253 armv7m->core_cache->reg_list[num].valid = 1;
254 armv7m->core_cache->reg_list[num].dirty = 0;
255
256 return ERROR_OK;
257 }
258
259 /**
260 * Returns generic ARM userspace registers to GDB.
261 * GDB doesn't quite understand that most ARMs don't have floating point
262 * hardware, so this also fakes a set of long-obsolete FPA registers that
263 * are not used in EABI based software stacks.
264 */
265 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
266 {
267 struct armv7m_common *armv7m = target_to_armv7m(target);
268 int i;
269
270 *reg_list_size = 26;
271 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
272
273 /*
274 * GDB register packet format for ARM:
275 * - the first 16 registers are r0..r15
276 * - (obsolete) 8 FPA registers
277 * - (obsolete) FPA status
278 * - CPSR
279 */
280 for (i = 0; i < 16; i++)
281 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
282
283 for (i = 16; i < 24; i++)
284 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
285 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
286
287 #ifdef ARMV7_GDB_HACKS
288 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
289 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
290
291 /* ARMV7M is always in thumb mode, try to make GDB understand this
292 * if it does not support this arch */
293 *((char *)armv7m->arm.pc->value) |= 1;
294 #else
295 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
296 #endif
297
298 return ERROR_OK;
299 }
300
301 /** Runs a Thumb algorithm in the target. */
302 int armv7m_run_algorithm(struct target *target,
303 int num_mem_params, struct mem_param *mem_params,
304 int num_reg_params, struct reg_param *reg_params,
305 uint32_t entry_point, uint32_t exit_point,
306 int timeout_ms, void *arch_info)
307 {
308 int retval;
309
310 retval = armv7m_start_algorithm(target,
311 num_mem_params, mem_params,
312 num_reg_params, reg_params,
313 entry_point, exit_point,
314 arch_info);
315
316 if (retval == ERROR_OK)
317 retval = armv7m_wait_algorithm(target,
318 num_mem_params, mem_params,
319 num_reg_params, reg_params,
320 exit_point, timeout_ms,
321 arch_info);
322
323 return retval;
324 }
325
326 /** Starts a Thumb algorithm in the target. */
327 int armv7m_start_algorithm(struct target *target,
328 int num_mem_params, struct mem_param *mem_params,
329 int num_reg_params, struct reg_param *reg_params,
330 uint32_t entry_point, uint32_t exit_point,
331 void *arch_info)
332 {
333 struct armv7m_common *armv7m = target_to_armv7m(target);
334 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
335 enum armv7m_mode core_mode = armv7m->core_mode;
336 int retval = ERROR_OK;
337
338 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
339 * at the exit point */
340
341 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
342 LOG_ERROR("current target isn't an ARMV7M target");
343 return ERROR_TARGET_INVALID;
344 }
345
346 if (target->state != TARGET_HALTED) {
347 LOG_WARNING("target not halted");
348 return ERROR_TARGET_NOT_HALTED;
349 }
350
351 /* refresh core register cache
352 * Not needed if core register cache is always consistent with target process state */
353 for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
354 if (!armv7m->core_cache->reg_list[i].valid)
355 armv7m->read_core_reg(target, i);
356 armv7m_algorithm_info->context[i] = buf_get_u32(
357 armv7m->core_cache->reg_list[i].value,
358 0,
359 32);
360 }
361
362 for (int i = 0; i < num_mem_params; i++) {
363 /* TODO: Write only out params */
364 retval = target_write_buffer(target, mem_params[i].address,
365 mem_params[i].size,
366 mem_params[i].value);
367 if (retval != ERROR_OK)
368 return retval;
369 }
370
371 for (int i = 0; i < num_reg_params; i++) {
372 struct reg *reg =
373 register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
374 /* uint32_t regvalue; */
375
376 if (!reg) {
377 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
378 return ERROR_COMMAND_SYNTAX_ERROR;
379 }
380
381 if (reg->size != reg_params[i].size) {
382 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
383 reg_params[i].reg_name);
384 return ERROR_COMMAND_SYNTAX_ERROR;
385 }
386
387 /* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */
388 armv7m_set_core_reg(reg, reg_params[i].value);
389 }
390
391 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) {
392 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
393 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
394 0, 1, armv7m_algorithm_info->core_mode);
395 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
396 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
397 }
398 armv7m_algorithm_info->core_mode = core_mode;
399
400 retval = target_resume(target, 0, entry_point, 1, 1);
401
402 return retval;
403 }
404
405 /** Waits for an algorithm in the target. */
406 int armv7m_wait_algorithm(struct target *target,
407 int num_mem_params, struct mem_param *mem_params,
408 int num_reg_params, struct reg_param *reg_params,
409 uint32_t exit_point, int timeout_ms,
410 void *arch_info)
411 {
412 struct armv7m_common *armv7m = target_to_armv7m(target);
413 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
414 int retval = ERROR_OK;
415 uint32_t pc;
416
417 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
418 * at the exit point */
419
420 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
421 LOG_ERROR("current target isn't an ARMV7M target");
422 return ERROR_TARGET_INVALID;
423 }
424
425 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
426 /* If the target fails to halt due to the breakpoint, force a halt */
427 if (retval != ERROR_OK || target->state != TARGET_HALTED) {
428 retval = target_halt(target);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = target_wait_state(target, TARGET_HALTED, 500);
432 if (retval != ERROR_OK)
433 return retval;
434 return ERROR_TARGET_TIMEOUT;
435 }
436
437 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
438 if (exit_point && (pc != exit_point)) {
439 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32,
440 pc,
441 exit_point);
442 return ERROR_TARGET_TIMEOUT;
443 }
444
445 /* Read memory values to mem_params[] */
446 for (int i = 0; i < num_mem_params; i++) {
447 if (mem_params[i].direction != PARAM_OUT) {
448 retval = target_read_buffer(target, mem_params[i].address,
449 mem_params[i].size,
450 mem_params[i].value);
451 if (retval != ERROR_OK)
452 return retval;
453 }
454 }
455
456 /* Copy core register values to reg_params[] */
457 for (int i = 0; i < num_reg_params; i++) {
458 if (reg_params[i].direction != PARAM_OUT) {
459 struct reg *reg = register_get_by_name(armv7m->core_cache,
460 reg_params[i].reg_name,
461 0);
462
463 if (!reg) {
464 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
465 return ERROR_COMMAND_SYNTAX_ERROR;
466 }
467
468 if (reg->size != reg_params[i].size) {
469 LOG_ERROR(
470 "BUG: register '%s' size doesn't match reg_params[i].size",
471 reg_params[i].reg_name);
472 return ERROR_COMMAND_SYNTAX_ERROR;
473 }
474
475 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
476 }
477 }
478
479 for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
480 uint32_t regvalue;
481 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
482 if (regvalue != armv7m_algorithm_info->context[i]) {
483 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
484 armv7m->core_cache->reg_list[i].name,
485 armv7m_algorithm_info->context[i]);
486 buf_set_u32(armv7m->core_cache->reg_list[i].value,
487 0, 32, armv7m_algorithm_info->context[i]);
488 armv7m->core_cache->reg_list[i].valid = 1;
489 armv7m->core_cache->reg_list[i].dirty = 1;
490 }
491 }
492
493 armv7m->core_mode = armv7m_algorithm_info->core_mode;
494
495 return retval;
496 }
497
498 /** Logs summary of ARMv7-M state for a halted target. */
499 int armv7m_arch_state(struct target *target)
500 {
501 struct armv7m_common *armv7m = target_to_armv7m(target);
502 struct arm *arm = &armv7m->arm;
503 uint32_t ctrl, sp;
504
505 ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
506 sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
507
508 LOG_USER("target halted due to %s, current mode: %s %s\n"
509 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
510 debug_reason_name(target),
511 armv7m_mode_strings[armv7m->core_mode],
512 armv7m_exception_string(armv7m->exception_number),
513 buf_get_u32(arm->cpsr->value, 0, 32),
514 buf_get_u32(arm->pc->value, 0, 32),
515 (ctrl & 0x02) ? 'p' : 'm',
516 sp,
517 arm->is_semihosting ? ", semihosting" : "");
518
519 return ERROR_OK;
520 }
521 static const struct reg_arch_type armv7m_reg_type = {
522 .get = armv7m_get_core_reg,
523 .set = armv7m_set_core_reg,
524 };
525
526 /** Builds cache of architecturally defined registers. */
527 struct reg_cache *armv7m_build_reg_cache(struct target *target)
528 {
529 struct armv7m_common *armv7m = target_to_armv7m(target);
530 struct arm *arm = &armv7m->arm;
531 int num_regs = ARMV7M_NUM_REGS;
532 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
533 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
534 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
535 struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
536 int i;
537
538 #ifdef ARMV7_GDB_HACKS
539 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
540 #endif
541
542 /* Build the process context cache */
543 cache->name = "arm v7m registers";
544 cache->next = NULL;
545 cache->reg_list = reg_list;
546 cache->num_regs = num_regs;
547 (*cache_p) = cache;
548 armv7m->core_cache = cache;
549
550 for (i = 0; i < num_regs; i++) {
551 arch_info[i].num = armv7m_regs[i].id;
552 arch_info[i].target = target;
553 arch_info[i].armv7m_common = armv7m;
554 reg_list[i].name = armv7m_regs[i].name;
555 reg_list[i].size = armv7m_regs[i].bits;
556 reg_list[i].value = calloc(1, 4);
557 reg_list[i].dirty = 0;
558 reg_list[i].valid = 0;
559 reg_list[i].type = &armv7m_reg_type;
560 reg_list[i].arch_info = &arch_info[i];
561 }
562
563 arm->cpsr = reg_list + ARMV7M_xPSR;
564 arm->pc = reg_list + ARMV7M_PC;
565 arm->core_cache = cache;
566 return cache;
567 }
568
569 static int armv7m_setup_semihosting(struct target *target, int enable)
570 {
571 /* nothing todo for armv7m */
572 return ERROR_OK;
573 }
574
575 /** Sets up target as a generic ARMv7-M core */
576 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
577 {
578 struct arm *arm = &armv7m->arm;
579
580 armv7m->common_magic = ARMV7M_COMMON_MAGIC;
581 armv7m->fp_feature = FP_NONE;
582
583 arm->core_type = ARM_MODE_THREAD;
584 arm->arch_info = armv7m;
585 arm->setup_semihosting = armv7m_setup_semihosting;
586
587 /* FIXME remove v7m-specific r/w core_reg functions;
588 * use the generic ARM core support..
589 */
590 armv7m->read_core_reg = armv7m_read_core_reg;
591 armv7m->write_core_reg = armv7m_write_core_reg;
592
593 return arm_init_arch_info(target, arm);
594 }
595
596 /** Generates a CRC32 checksum of a memory region. */
597 int armv7m_checksum_memory(struct target *target,
598 uint32_t address, uint32_t count, uint32_t *checksum)
599 {
600 struct working_area *crc_algorithm;
601 struct armv7m_algorithm armv7m_info;
602 struct reg_param reg_params[2];
603 int retval;
604
605 /* see contrib/loaders/checksum/armv7m_crc.s for src */
606
607 static const uint8_t cortex_m3_crc_code[] = {
608 /* main: */
609 0x02, 0x46, /* mov r2, r0 */
610 0x00, 0x20, /* movs r0, #0 */
611 0xC0, 0x43, /* mvns r0, r0 */
612 0x0A, 0x4E, /* ldr r6, CRC32XOR */
613 0x0B, 0x46, /* mov r3, r1 */
614 0x00, 0x24, /* movs r4, #0 */
615 0x0D, 0xE0, /* b ncomp */
616 /* nbyte: */
617 0x11, 0x5D, /* ldrb r1, [r2, r4] */
618 0x09, 0x06, /* lsls r1, r1, #24 */
619 0x48, 0x40, /* eors r0, r0, r1 */
620 0x00, 0x25, /* movs r5, #0 */
621 /* loop: */
622 0x00, 0x28, /* cmp r0, #0 */
623 0x02, 0xDA, /* bge notset */
624 0x40, 0x00, /* lsls r0, r0, #1 */
625 0x70, 0x40, /* eors r0, r0, r6 */
626 0x00, 0xE0, /* b cont */
627 /* notset: */
628 0x40, 0x00, /* lsls r0, r0, #1 */
629 /* cont: */
630 0x01, 0x35, /* adds r5, r5, #1 */
631 0x08, 0x2D, /* cmp r5, #8 */
632 0xF6, 0xD1, /* bne loop */
633 0x01, 0x34, /* adds r4, r4, #1 */
634 /* ncomp: */
635 0x9C, 0x42, /* cmp r4, r3 */
636 0xEF, 0xD1, /* bne nbyte */
637 0x00, 0xBE, /* bkpt #0 */
638 0xB7, 0x1D, 0xC1, 0x04 /* CRC32XOR: .word 0x04c11db7 */
639 };
640
641 retval = target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm);
642 if (retval != ERROR_OK)
643 return retval;
644
645 retval = target_write_buffer(target, crc_algorithm->address,
646 sizeof(cortex_m3_crc_code), (uint8_t *)cortex_m3_crc_code);
647 if (retval != ERROR_OK)
648 goto cleanup;
649
650 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
651 armv7m_info.core_mode = ARMV7M_MODE_ANY;
652
653 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
654 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
655
656 buf_set_u32(reg_params[0].value, 0, 32, address);
657 buf_set_u32(reg_params[1].value, 0, 32, count);
658
659 int timeout = 20000 * (1 + (count / (1024 * 1024)));
660
661 retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
662 crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6),
663 timeout, &armv7m_info);
664
665 if (retval == ERROR_OK)
666 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
667 else
668 LOG_ERROR("error executing cortex_m3 crc algorithm");
669
670 destroy_reg_param(&reg_params[0]);
671 destroy_reg_param(&reg_params[1]);
672
673 cleanup:
674 target_free_working_area(target, crc_algorithm);
675
676 return retval;
677 }
678
679 /** Checks whether a memory region is zeroed. */
680 int armv7m_blank_check_memory(struct target *target,
681 uint32_t address, uint32_t count, uint32_t *blank)
682 {
683 struct working_area *erase_check_algorithm;
684 struct reg_param reg_params[3];
685 struct armv7m_algorithm armv7m_info;
686 int retval;
687
688 /* see contrib/loaders/erase_check/armv7m_erase_check.s for src */
689
690 static const uint8_t erase_check_code[] = {
691 /* loop: */
692 0x03, 0x78, /* ldrb r3, [r0] */
693 0x01, 0x30, /* adds r0, #1 */
694 0x1A, 0x40, /* ands r2, r2, r3 */
695 0x01, 0x39, /* subs r1, r1, #1 */
696 0xFA, 0xD1, /* bne loop */
697 0x00, 0xBE /* bkpt #0 */
698 };
699
700 /* make sure we have a working area */
701 if (target_alloc_working_area(target, sizeof(erase_check_code),
702 &erase_check_algorithm) != ERROR_OK)
703 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
704
705 retval = target_write_buffer(target, erase_check_algorithm->address,
706 sizeof(erase_check_code), (uint8_t *)erase_check_code);
707 if (retval != ERROR_OK)
708 return retval;
709
710 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
711 armv7m_info.core_mode = ARMV7M_MODE_ANY;
712
713 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
714 buf_set_u32(reg_params[0].value, 0, 32, address);
715
716 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
717 buf_set_u32(reg_params[1].value, 0, 32, count);
718
719 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
720 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
721
722 retval = target_run_algorithm(target,
723 0,
724 NULL,
725 3,
726 reg_params,
727 erase_check_algorithm->address,
728 erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
729 10000,
730 &armv7m_info);
731
732 if (retval == ERROR_OK)
733 *blank = buf_get_u32(reg_params[2].value, 0, 32);
734
735 destroy_reg_param(&reg_params[0]);
736 destroy_reg_param(&reg_params[1]);
737 destroy_reg_param(&reg_params[2]);
738
739 target_free_working_area(target, erase_check_algorithm);
740
741 return retval;
742 }
743
744 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
745 {
746 struct armv7m_common *armv7m = target_to_armv7m(target);
747 struct reg *r = armv7m->arm.pc;
748 bool result = false;
749
750
751 /* if we halted last time due to a bkpt instruction
752 * then we have to manually step over it, otherwise
753 * the core will break again */
754
755 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
756 uint16_t op;
757 uint32_t pc = buf_get_u32(r->value, 0, 32);
758
759 pc &= ~1;
760 if (target_read_u16(target, pc, &op) == ERROR_OK) {
761 if ((op & 0xFF00) == 0xBE00) {
762 pc = buf_get_u32(r->value, 0, 32) + 2;
763 buf_set_u32(r->value, 0, 32, pc);
764 r->dirty = true;
765 r->valid = true;
766 result = true;
767 LOG_DEBUG("Skipping over BKPT instruction");
768 }
769 }
770 }
771
772 if (inst_found)
773 *inst_found = result;
774
775 return ERROR_OK;
776 }
777
778 const struct command_registration armv7m_command_handlers[] = {
779 {
780 .chain = arm_command_handlers,
781 },
782 {
783 .chain = dap_command_handlers,
784 },
785 COMMAND_REGISTRATION_DONE
786 };

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