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- 16 and 32 bit unaligned accesses supported
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "armv7m.h"
30 #include "register.h"
31 #include "target.h"
32 #include "log.h"
33 #include "jtag.h"
34 #include "arm_jtag.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 char* armv7m_mode_strings[] =
44 {
45 "Handler", "Thread"
46 };
47
48 char* armv7m_state_strings[] =
49 {
50 "Thumb", "Debug"
51 };
52
53 char* armv7m_exception_strings[] =
54 {
55 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
56 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
57 };
58
59 char* armv7m_core_reg_list[] =
60 {
61 /* Registers accessed through core debug */
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
63 "sp", "lr", "pc",
64 "xPSR", "msp", "psp",
65 /* Registers accessed through MSR instructions */
66 /* "apsr", "iapsr", "ipsr", "epsr", */
67 "primask", "basepri", "faultmask", "control"
68 };
69
70 char* armv7m_core_dbgreg_list[] =
71 {
72 /* Registers accessed through core debug */
73 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
74 "sp", "lr", "pc",
75 "xPSR", "msp", "psp",
76 /* Registers accessed through MSR instructions */
77 /* "dbg_apsr", "iapsr", "ipsr", "epsr", */
78 "primask", "basepri", "faultmask", "dbg_control"
79 };
80
81 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
82
83 reg_t armv7m_gdb_dummy_fp_reg =
84 {
85 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
86 };
87
88 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
89 {
90 /* CORE_GP are accesible using the core debug registers */
91 {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
92 {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
93 {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
94 {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
95 {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
96 {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
97 {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
98 {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
99 {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
100 {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
101 {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
102 {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
103 {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
104 {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
105 {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
106 {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
107
108 {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
109 {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
110 {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
111
112 /* CORE_SP are accesible using MSR and MRS instructions */
113 #if 0
114 {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
115 {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
116 {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
117 {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
118 #endif
119
120 {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
121 {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
122 {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
123 {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
124 };
125
126 int armv7m_core_reg_arch_type = -1;
127
128 /* Keep different contexts for the process being debugged and debug algorithms */
129 enum armv7m_runcontext armv7m_get_context(target_t *target)
130 {
131 /* get pointers to arch-specific information */
132 armv7m_common_t *armv7m = target->arch_info;
133
134 if (armv7m->process_context == armv7m->core_cache)
135 return ARMV7M_PROCESS_CONTEXT;
136 if (armv7m->debug_context == armv7m->core_cache)
137 return ARMV7M_DEBUG_CONTEXT;
138
139 ERROR("Invalid runcontext");
140 exit(-1);
141 }
142
143 int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
144 {
145 int i;
146 /* get pointers to arch-specific information */
147 armv7m_common_t *armv7m = target->arch_info;
148
149 if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
150 {
151 WARNING("target not halted, switch context ");
152 return ERROR_TARGET_NOT_HALTED;
153 }
154
155 if (new_ctx == armv7m_get_context(target))
156 return ERROR_OK;
157
158 switch (new_ctx)
159 {
160 case ARMV7M_PROCESS_CONTEXT:
161 armv7m->core_cache = armv7m->process_context;
162 break;
163 case ARMV7M_DEBUG_CONTEXT:
164 armv7m->core_cache = armv7m->debug_context;
165 break;
166 default:
167 ERROR("Invalid runcontext");
168 exit(-1);
169 }
170 /* Mark registers in new context as dirty to force reload when run */
171
172 for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
173 {
174 armv7m->core_cache->reg_list[i].dirty = 1;
175 }
176
177 return ERROR_OK;
178 }
179
180 int armv7m_restore_context(target_t *target)
181 {
182 int i;
183
184 /* get pointers to arch-specific information */
185 armv7m_common_t *armv7m = target->arch_info;
186
187 DEBUG(" ");
188
189 if (armv7m->pre_restore_context)
190 armv7m->pre_restore_context(target);
191
192 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
193 {
194 if (armv7m->core_cache->reg_list[i].dirty)
195 {
196 armv7m->write_core_reg(target, i);
197 }
198 }
199
200 if (armv7m->post_restore_context)
201 armv7m->post_restore_context(target);
202
203 return ERROR_OK;
204 }
205
206
207 /* Core state functions */
208 char enamebuf[32];
209 char *armv7m_exception_string(int number)
210 {
211 if ((number < 0) | (number > 511))
212 return "Invalid exception";
213 if (number < 16)
214 return armv7m_exception_strings[number];
215 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
216 return enamebuf;
217 }
218
219 int armv7m_get_core_reg(reg_t *reg)
220 {
221 int retval;
222 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
223 target_t *target = armv7m_reg->target;
224 armv7m_common_t *armv7m_target = target->arch_info;
225
226 if (target->state != TARGET_HALTED)
227 {
228 return ERROR_TARGET_NOT_HALTED;
229 }
230
231 retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
232
233 return retval;
234 }
235
236 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
237 {
238 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
239 target_t *target = armv7m_reg->target;
240 u32 value = buf_get_u32(buf, 0, 32);
241
242 if (target->state != TARGET_HALTED)
243 {
244 return ERROR_TARGET_NOT_HALTED;
245 }
246
247 buf_set_u32(reg->value, 0, 32, value);
248 reg->dirty = 1;
249 reg->valid = 1;
250
251 return ERROR_OK;
252 }
253
254 int armv7m_read_core_reg(struct target_s *target, int num)
255 {
256 u32 reg_value;
257 int retval;
258 armv7m_core_reg_t * armv7m_core_reg;
259
260 /* get pointers to arch-specific information */
261 armv7m_common_t *armv7m = target->arch_info;
262
263 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
264 return ERROR_INVALID_ARGUMENTS;
265
266 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
267 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
268 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
269 armv7m->core_cache->reg_list[num].valid = 1;
270 armv7m->core_cache->reg_list[num].dirty = 0;
271
272 return ERROR_OK;
273 }
274
275 int armv7m_write_core_reg(struct target_s *target, int num)
276 {
277 int retval;
278 u32 reg_value;
279 armv7m_core_reg_t *armv7m_core_reg;
280
281 /* get pointers to arch-specific information */
282 armv7m_common_t *armv7m = target->arch_info;
283
284 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
285 return ERROR_INVALID_ARGUMENTS;
286
287 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
288 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
289 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
290 if (retval != ERROR_OK)
291 {
292 ERROR("JTAG failure");
293 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
294 return ERROR_JTAG_DEVICE_ERROR;
295 }
296 DEBUG("write core reg %i value 0x%x", num , reg_value);
297 armv7m->core_cache->reg_list[num].valid = 1;
298 armv7m->core_cache->reg_list[num].dirty = 0;
299
300 return ERROR_OK;
301 }
302
303 int armv7m_invalidate_core_regs(target_t *target)
304 {
305 /* get pointers to arch-specific information */
306 armv7m_common_t *armv7m = target->arch_info;
307 int i;
308
309 for (i = 0; i < armv7m->core_cache->num_regs; i++)
310 {
311 armv7m->core_cache->reg_list[i].valid = 0;
312 armv7m->core_cache->reg_list[i].dirty = 0;
313 }
314
315 return ERROR_OK;
316 }
317
318 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
319 {
320 /* get pointers to arch-specific information */
321 armv7m_common_t *armv7m = target->arch_info;
322 int i;
323
324 *reg_list_size = 26;
325 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
326
327 /* TODOLATER correct list of registers, names ? */
328 for (i = 0; i < *reg_list_size; i++)
329 {
330 if (i < ARMV7NUMCOREREGS)
331 (*reg_list)[i] = &armv7m->process_context->reg_list[i];
332 /* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
333 else
334 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
335 }
336 /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
337 armv7m->process_context->reg_list[15].value[0] |= 1;
338 (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
339 return ERROR_OK;
340 }
341
342 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
343 {
344 /* get pointers to arch-specific information */
345 armv7m_common_t *armv7m = target->arch_info;
346 armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
347 enum armv7m_state core_state = armv7m->core_state;
348 enum armv7m_mode core_mode = armv7m->core_mode;
349 int retval = ERROR_OK;
350 u32 pc;
351 int exit_breakpoint_size = 0;
352 int i;
353
354 armv7m->core_state = core_state;
355 armv7m->core_mode = core_mode;
356
357 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
358 {
359 ERROR("current target isn't an ARMV7M target");
360 return ERROR_TARGET_INVALID;
361 }
362
363 if (target->state != TARGET_HALTED)
364 {
365 WARNING("target not halted");
366 return ERROR_TARGET_NOT_HALTED;
367 }
368
369 /* refresh core register cache */
370 /* Not needed if core register cache is always consistent with target process state */
371 armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
372
373 for (i = 0; i < num_mem_params; i++)
374 {
375 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
376 }
377
378 for (i = 0; i < num_reg_params; i++)
379 {
380 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
381 u32 regvalue;
382
383 if (!reg)
384 {
385 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
386 exit(-1);
387 }
388
389 if (reg->size != reg_params[i].size)
390 {
391 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
392 exit(-1);
393 }
394
395 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
396 armv7m_set_core_reg(reg, reg_params[i].value);
397 }
398
399 /* ARMV7M always runs in Thumb state */
400 exit_breakpoint_size = 2;
401 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
402 {
403 ERROR("can't add breakpoint to finish algorithm execution");
404 return ERROR_TARGET_FAILURE;
405 }
406
407 /* This code relies on the target specific resume() and poll()->debug_entry()
408 sequence to write register values to the processor and the read them back */
409 target->type->resume(target, 0, entry_point, 1, 1);
410 target->type->poll(target);
411
412 while (target->state != TARGET_HALTED)
413 {
414 usleep(5000);
415 target->type->poll(target);
416 if ((timeout_ms -= 5) <= 0)
417 {
418 ERROR("timeout waiting for algorithm to complete, trying to halt target");
419 target->type->halt(target);
420 timeout_ms = 1000;
421 while (target->state != TARGET_HALTED)
422 {
423 usleep(10000);
424 target->type->poll(target);
425 if ((timeout_ms -= 10) <= 0)
426 {
427 ERROR("target didn't reenter debug state, exiting");
428 exit(-1);
429 }
430 }
431 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
432 DEBUG("failed algoritm halted at 0x%x ", pc);
433 retval = ERROR_TARGET_TIMEOUT;
434 }
435 }
436
437 breakpoint_remove(target, exit_point);
438
439 /* Read memory values to mem_params[] */
440 for (i = 0; i < num_mem_params; i++)
441 {
442 if (mem_params[i].direction != PARAM_OUT)
443 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
444 }
445
446 /* Copy core register values to reg_params[] */
447 for (i = 0; i < num_reg_params; i++)
448 {
449 if (reg_params[i].direction != PARAM_OUT)
450 {
451 reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
452
453 if (!reg)
454 {
455 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
456 exit(-1);
457 }
458
459 if (reg->size != reg_params[i].size)
460 {
461 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
462 exit(-1);
463 }
464
465 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
466 }
467 }
468
469 return retval;
470 }
471
472 int armv7m_arch_state(struct target_s *target)
473 {
474 /* get pointers to arch-specific information */
475 armv7m_common_t *armv7m = target->arch_info;
476
477 USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
478 armv7m_state_strings[armv7m->core_state],
479 target_debug_reason_strings[target->debug_reason],
480 armv7m_mode_strings[armv7m->core_mode],
481 armv7m_exception_string(armv7m->exception_number),
482 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
483 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
484
485 return ERROR_OK;
486 }
487
488 reg_cache_t *armv7m_build_reg_cache(target_t *target)
489 {
490 /* get pointers to arch-specific information */
491 armv7m_common_t *armv7m = target->arch_info;
492
493 int num_regs = ARMV7NUMCOREREGS;
494 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
495 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
496 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
497 armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
498 int i;
499
500 if (armv7m_core_reg_arch_type == -1)
501 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
502
503 /* Build the process context cache */
504 cache->name = "arm v7m registers";
505 cache->next = NULL;
506 cache->reg_list = reg_list;
507 cache->num_regs = num_regs;
508 (*cache_p) = cache;
509 armv7m->core_cache = cache;
510 armv7m->process_context = cache;
511
512 for (i = 0; i < num_regs; i++)
513 {
514 arch_info[i] = armv7m_core_reg_list_arch_info[i];
515 arch_info[i].target = target;
516 arch_info[i].armv7m_common = armv7m;
517 reg_list[i].name = armv7m_core_reg_list[i];
518 reg_list[i].size = 32;
519 reg_list[i].value = calloc(1, 4);
520 reg_list[i].dirty = 0;
521 reg_list[i].valid = 0;
522 reg_list[i].bitfield_desc = NULL;
523 reg_list[i].num_bitfields = 0;
524 reg_list[i].arch_type = armv7m_core_reg_arch_type;
525 reg_list[i].arch_info = &arch_info[i];
526 }
527
528 /* Build the debug context cache*/
529 cache = malloc(sizeof(reg_cache_t));
530 reg_list = malloc(sizeof(reg_t) * num_regs);
531
532 cache->name = "arm v7m debug registers";
533 cache->next = NULL;
534 cache->reg_list = reg_list;
535 cache->num_regs = num_regs;
536 armv7m->debug_context = cache;
537 armv7m->process_context->next = cache;
538
539 for (i = 0; i < num_regs; i++)
540 {
541 reg_list[i].name = armv7m_core_dbgreg_list[i];
542 reg_list[i].size = 32;
543 reg_list[i].value = calloc(1, 4);
544 reg_list[i].dirty = 0;
545 reg_list[i].valid = 0;
546 reg_list[i].bitfield_desc = NULL;
547 reg_list[i].num_bitfields = 0;
548 reg_list[i].arch_type = armv7m_core_reg_arch_type;
549 reg_list[i].arch_info = &arch_info[i];
550 }
551
552 return cache;
553 }
554
555 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
556 {
557 armv7m_build_reg_cache(target);
558
559 return ERROR_OK;
560 }
561
562 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
563 {
564 /* register arch-specific functions */
565
566 target->arch_info = armv7m;
567 armv7m->core_state = ARMV7M_STATE_THUMB;
568 armv7m->read_core_reg = armv7m_read_core_reg;
569 armv7m->write_core_reg = armv7m_write_core_reg;
570
571 return ERROR_OK;
572 }
573
574 int armv7m_register_commands(struct command_context_s *cmd_ctx)
575 {
576 return ERROR_OK;
577 }
578
579 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
580 {
581 working_area_t *crc_algorithm;
582 armv7m_algorithm_t armv7m_info;
583 reg_param_t reg_params[2];
584 int retval;
585
586 u16 cortex_m3_crc_code[] = {
587 0x4602, /* mov r2, r0 */
588 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
589 0x460B, /* mov r3, r1 */
590 0xF04F, 0x0400, /* mov r4, #0 */
591 0xE013, /* b ncomp */
592 /* nbyte: */
593 0x5D11, /* ldrb r1, [r2, r4] */
594 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
595 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
596
597 0xF04F, 0x0500, /* mov r5, #0 */
598 /* loop: */
599 0x2800, /* cmp r0, #0 */
600 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
601 0xF105, 0x0501, /* add r5, r5, #1 */
602 0x4630, /* mov r0, r6 */
603 0xBFB8, /* it lt */
604 0xEA86, 0x0007, /* eor r0, r6, r7 */
605 0x2D08, /* cmp r5, #8 */
606 0xD1F4, /* bne loop */
607
608 0xF104, 0x0401, /* add r4, r4, #1 */
609 /* ncomp: */
610 0x429C, /* cmp r4, r3 */
611 0xD1E9, /* bne nbyte */
612 /* end: */
613 0xE7FE, /* b end */
614 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
615 };
616
617 int i;
618
619 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
620 {
621 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
622 }
623
624 /* convert flash writing code into a buffer in target endianness */
625 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
626 target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
627
628 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
629 armv7m_info.core_mode = ARMV7M_MODE_ANY;
630 armv7m_info.core_state = ARMV7M_STATE_THUMB;
631
632 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
633 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
634
635 buf_set_u32(reg_params[0].value, 0, 32, address);
636 buf_set_u32(reg_params[1].value, 0, 32, count);
637
638 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
639 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
640 {
641 ERROR("error executing cortex_m3 crc algorithm");
642 destroy_reg_param(&reg_params[0]);
643 destroy_reg_param(&reg_params[1]);
644 target_free_working_area(target, crc_algorithm);
645 return retval;
646 }
647
648 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
649
650 destroy_reg_param(&reg_params[0]);
651 destroy_reg_param(&reg_params[1]);
652
653 target_free_working_area(target, crc_algorithm);
654
655 return ERROR_OK;
656 }
657
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