Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
- remove build warnings
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifdef HAVE_CONFIG_H
30 #include "config.h"
31 #endif
32
33 #include "replacements.h"
34
35 #include "armv7m.h"
36 #include "register.h"
37 #include "target.h"
38 #include "log.h"
39 #include "jtag.h"
40 #include "arm_jtag.h"
41
42 #include <stdlib.h>
43 #include <string.h>
44
45 #if 0
46 #define _DEBUG_INSTRUCTION_EXECUTION_
47 #endif
48
49 char* armv7m_mode_strings[] =
50 {
51 "Thread", "Thread (User)", "Handler",
52 };
53
54 char* armv7m_exception_strings[] =
55 {
56 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
57 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
58 };
59
60 char* armv7m_core_reg_list[] =
61 {
62 /* Registers accessed through core debug */
63 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
64 "sp", "lr", "pc",
65 "xPSR", "msp", "psp",
66 /* Registers accessed through special reg 20 */
67 "primask", "basepri", "faultmask", "control"
68 };
69
70 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
71
72 reg_t armv7m_gdb_dummy_fp_reg =
73 {
74 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
75 };
76
77 u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
78
79 reg_t armv7m_gdb_dummy_fps_reg =
80 {
81 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
82 };
83
84 #ifdef ARMV7_GDB_HACKS
85 u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
86
87 reg_t armv7m_gdb_dummy_cpsr_reg =
88 {
89 "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
90 };
91 #endif
92
93 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
94 {
95 /* CORE_GP are accesible using the core debug registers */
96 {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
97 {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
98 {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
99 {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
100 {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
101 {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
102 {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
103 {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
104 {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
105 {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
106 {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
107 {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
108 {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
109 {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
110 {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
111 {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
112
113 {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
114 {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
115 {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
116
117 /* CORE_SP are accesible using coreregister 20 */
118 {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
119 {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
120 {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
121 {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
122 };
123
124 int armv7m_core_reg_arch_type = -1;
125 int armv7m_dummy_core_reg_arch_type = -1;
126
127 int armv7m_restore_context(target_t *target)
128 {
129 int i;
130
131 /* get pointers to arch-specific information */
132 armv7m_common_t *armv7m = target->arch_info;
133
134 LOG_DEBUG(" ");
135
136 if (armv7m->pre_restore_context)
137 armv7m->pre_restore_context(target);
138
139 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
140 {
141 if (armv7m->core_cache->reg_list[i].dirty)
142 {
143 armv7m->write_core_reg(target, i);
144 }
145 }
146
147 if (armv7m->post_restore_context)
148 armv7m->post_restore_context(target);
149
150 return ERROR_OK;
151 }
152
153 /* Core state functions */
154 char *armv7m_exception_string(int number)
155 {
156 static char enamebuf[32];
157
158 if ((number < 0) | (number > 511))
159 return "Invalid exception";
160 if (number < 16)
161 return armv7m_exception_strings[number];
162 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
163 return enamebuf;
164 }
165
166 int armv7m_get_core_reg(reg_t *reg)
167 {
168 int retval;
169 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
170 target_t *target = armv7m_reg->target;
171 armv7m_common_t *armv7m_target = target->arch_info;
172
173 if (target->state != TARGET_HALTED)
174 {
175 return ERROR_TARGET_NOT_HALTED;
176 }
177
178 retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
179
180 return retval;
181 }
182
183 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
184 {
185 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
186 target_t *target = armv7m_reg->target;
187 u32 value = buf_get_u32(buf, 0, 32);
188
189 if (target->state != TARGET_HALTED)
190 {
191 return ERROR_TARGET_NOT_HALTED;
192 }
193
194 buf_set_u32(reg->value, 0, 32, value);
195 reg->dirty = 1;
196 reg->valid = 1;
197
198 return ERROR_OK;
199 }
200
201 int armv7m_read_core_reg(struct target_s *target, int num)
202 {
203 u32 reg_value;
204 int retval;
205 armv7m_core_reg_t * armv7m_core_reg;
206
207 /* get pointers to arch-specific information */
208 armv7m_common_t *armv7m = target->arch_info;
209
210 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
211 return ERROR_INVALID_ARGUMENTS;
212
213 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
214 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
215 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
216 armv7m->core_cache->reg_list[num].valid = 1;
217 armv7m->core_cache->reg_list[num].dirty = 0;
218
219 return retval;
220 }
221
222 int armv7m_write_core_reg(struct target_s *target, int num)
223 {
224 int retval;
225 u32 reg_value;
226 armv7m_core_reg_t *armv7m_core_reg;
227
228 /* get pointers to arch-specific information */
229 armv7m_common_t *armv7m = target->arch_info;
230
231 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
232 return ERROR_INVALID_ARGUMENTS;
233
234 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
235 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
236 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
237 if (retval != ERROR_OK)
238 {
239 LOG_ERROR("JTAG failure");
240 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
241 return ERROR_JTAG_DEVICE_ERROR;
242 }
243 LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
244 armv7m->core_cache->reg_list[num].valid = 1;
245 armv7m->core_cache->reg_list[num].dirty = 0;
246
247 return ERROR_OK;
248 }
249
250 int armv7m_invalidate_core_regs(target_t *target)
251 {
252 /* get pointers to arch-specific information */
253 armv7m_common_t *armv7m = target->arch_info;
254 int i;
255
256 for (i = 0; i < armv7m->core_cache->num_regs; i++)
257 {
258 armv7m->core_cache->reg_list[i].valid = 0;
259 armv7m->core_cache->reg_list[i].dirty = 0;
260 }
261
262 return ERROR_OK;
263 }
264
265 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
266 {
267 /* get pointers to arch-specific information */
268 armv7m_common_t *armv7m = target->arch_info;
269 int i;
270
271 *reg_list_size = 26;
272 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
273
274 for (i = 0; i < 16; i++)
275 {
276 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
277 }
278
279 for (i = 16; i < 24; i++)
280 {
281 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
282 }
283
284 (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
285
286 #ifdef ARMV7_GDB_HACKS
287 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
288 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
289
290 /* ARMV7M is always in thumb mode, try to make GDB understand this
291 * if it does not support this arch */
292 armv7m->core_cache->reg_list[15].value[0] |= 1;
293 #else
294 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
295 #endif
296
297 return ERROR_OK;
298 }
299
300 /* run to exit point. return error if exit point was not reached. */
301 static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int timeout_ms, u32 exit_point, armv7m_common_t *armv7m)
302 {
303 u32 pc;
304 int retval;
305 /* This code relies on the target specific resume() and poll()->debug_entry()
306 sequence to write register values to the processor and the read them back */
307 if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
308 {
309 return retval;
310 }
311
312 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
313 // If the target fails to halt due to the breakpoint, force a halt
314 if (retval != ERROR_OK || target->state != TARGET_HALTED)
315 {
316 if ((retval=target_halt(target))!=ERROR_OK)
317 return retval;
318 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
319 {
320 return retval;
321 }
322 return ERROR_TARGET_TIMEOUT;
323 }
324
325
326 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
327 if (pc != exit_point)
328 {
329 LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
330 return ERROR_TARGET_TIMEOUT;
331 }
332
333 return ERROR_OK;
334 }
335
336 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
337 {
338 /* get pointers to arch-specific information */
339 armv7m_common_t *armv7m = target->arch_info;
340 armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
341 enum armv7m_mode core_mode = armv7m->core_mode;
342 int retval = ERROR_OK;
343 int i;
344 u32 context[ARMV7NUMCOREREGS];
345
346 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
347 {
348 LOG_ERROR("current target isn't an ARMV7M target");
349 return ERROR_TARGET_INVALID;
350 }
351
352 if (target->state != TARGET_HALTED)
353 {
354 LOG_WARNING("target not halted");
355 return ERROR_TARGET_NOT_HALTED;
356 }
357
358 /* refresh core register cache */
359 /* Not needed if core register cache is always consistent with target process state */
360 for (i = 0; i < ARMV7NUMCOREREGS; i++)
361 {
362 if (!armv7m->core_cache->reg_list[i].valid)
363 armv7m->read_core_reg(target, i);
364 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
365 }
366
367 for (i = 0; i < num_mem_params; i++)
368 {
369 if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK)
370 return retval;
371 }
372
373 for (i = 0; i < num_reg_params; i++)
374 {
375 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
376 u32 regvalue;
377
378 if (!reg)
379 {
380 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
381 exit(-1);
382 }
383
384 if (reg->size != reg_params[i].size)
385 {
386 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
387 exit(-1);
388 }
389
390 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
391 armv7m_set_core_reg(reg, reg_params[i].value);
392 }
393
394 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
395 {
396 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
397 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
398 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
399 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
400 }
401
402 /* ARMV7M always runs in Thumb state */
403 if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
404 {
405 LOG_ERROR("can't add breakpoint to finish algorithm execution");
406 return ERROR_TARGET_FAILURE;
407 }
408
409 retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
410
411 breakpoint_remove(target, exit_point);
412
413 if (retval != ERROR_OK)
414 {
415 return retval;
416 }
417
418 /* Read memory values to mem_params[] */
419 for (i = 0; i < num_mem_params; i++)
420 {
421 if (mem_params[i].direction != PARAM_OUT)
422 if((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
423 {
424 return retval;
425 }
426 }
427
428 /* Copy core register values to reg_params[] */
429 for (i = 0; i < num_reg_params; i++)
430 {
431 if (reg_params[i].direction != PARAM_OUT)
432 {
433 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
434
435 if (!reg)
436 {
437 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
438 exit(-1);
439 }
440
441 if (reg->size != reg_params[i].size)
442 {
443 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
444 exit(-1);
445 }
446
447 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
448 }
449 }
450
451 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
452 {
453 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
454 buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
455 armv7m->core_cache->reg_list[i].valid = 1;
456 armv7m->core_cache->reg_list[i].dirty = 1;
457 }
458
459 armv7m->core_mode = core_mode;
460
461 return retval;
462 }
463
464 int armv7m_arch_state(struct target_s *target)
465 {
466 /* get pointers to arch-specific information */
467 armv7m_common_t *armv7m = target->arch_info;
468
469 LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
470 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
471 armv7m_mode_strings[armv7m->core_mode],
472 armv7m_exception_string(armv7m->exception_number),
473 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
474 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
475
476 return ERROR_OK;
477 }
478
479 reg_cache_t *armv7m_build_reg_cache(target_t *target)
480 {
481 /* get pointers to arch-specific information */
482 armv7m_common_t *armv7m = target->arch_info;
483
484 int num_regs = ARMV7NUMCOREREGS;
485 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
486 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
487 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
488 armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
489 int i;
490
491 if (armv7m_core_reg_arch_type == -1)
492 {
493 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
494 }
495
496 register_init_dummy(&armv7m_gdb_dummy_fps_reg);
497 #ifdef ARMV7_GDB_HACKS
498 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
499 #endif
500 register_init_dummy(&armv7m_gdb_dummy_fp_reg);
501
502 /* Build the process context cache */
503 cache->name = "arm v7m registers";
504 cache->next = NULL;
505 cache->reg_list = reg_list;
506 cache->num_regs = num_regs;
507 (*cache_p) = cache;
508 armv7m->core_cache = cache;
509
510 for (i = 0; i < num_regs; i++)
511 {
512 arch_info[i] = armv7m_core_reg_list_arch_info[i];
513 arch_info[i].target = target;
514 arch_info[i].armv7m_common = armv7m;
515 reg_list[i].name = armv7m_core_reg_list[i];
516 reg_list[i].size = 32;
517 reg_list[i].value = calloc(1, 4);
518 reg_list[i].dirty = 0;
519 reg_list[i].valid = 0;
520 reg_list[i].bitfield_desc = NULL;
521 reg_list[i].num_bitfields = 0;
522 reg_list[i].arch_type = armv7m_core_reg_arch_type;
523 reg_list[i].arch_info = &arch_info[i];
524 }
525
526 return cache;
527 }
528
529 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
530 {
531 armv7m_build_reg_cache(target);
532
533 return ERROR_OK;
534 }
535
536 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
537 {
538 /* register arch-specific functions */
539
540 target->arch_info = armv7m;
541 armv7m->read_core_reg = armv7m_read_core_reg;
542 armv7m->write_core_reg = armv7m_write_core_reg;
543
544 return ERROR_OK;
545 }
546
547 int armv7m_register_commands(struct command_context_s *cmd_ctx)
548 {
549 return ERROR_OK;
550 }
551
552 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
553 {
554 working_area_t *crc_algorithm;
555 armv7m_algorithm_t armv7m_info;
556 reg_param_t reg_params[2];
557 int retval;
558
559 u16 cortex_m3_crc_code[] = {
560 0x4602, /* mov r2, r0 */
561 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
562 0x460B, /* mov r3, r1 */
563 0xF04F, 0x0400, /* mov r4, #0 */
564 0xE013, /* b ncomp */
565 /* nbyte: */
566 0x5D11, /* ldrb r1, [r2, r4] */
567 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
568 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
569
570 0xF04F, 0x0500, /* mov r5, #0 */
571 /* loop: */
572 0x2800, /* cmp r0, #0 */
573 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
574 0xF105, 0x0501, /* add r5, r5, #1 */
575 0x4630, /* mov r0, r6 */
576 0xBFB8, /* it lt */
577 0xEA86, 0x0007, /* eor r0, r6, r7 */
578 0x2D08, /* cmp r5, #8 */
579 0xD1F4, /* bne loop */
580
581 0xF104, 0x0401, /* add r4, r4, #1 */
582 /* ncomp: */
583 0x429C, /* cmp r4, r3 */
584 0xD1E9, /* bne nbyte */
585 /* end: */
586 0xE7FE, /* b end */
587 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
588 };
589
590 int i;
591
592 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
593 {
594 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
595 }
596
597 /* convert flash writing code into a buffer in target endianness */
598 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
599 if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i])) != ERROR_OK)
600 {
601 return retval;
602 }
603
604 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
605 armv7m_info.core_mode = ARMV7M_MODE_ANY;
606
607 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
608 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
609
610 buf_set_u32(reg_params[0].value, 0, 32, address);
611 buf_set_u32(reg_params[1].value, 0, 32, count);
612
613 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
614 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
615 {
616 LOG_ERROR("error executing cortex_m3 crc algorithm");
617 destroy_reg_param(&reg_params[0]);
618 destroy_reg_param(&reg_params[1]);
619 target_free_working_area(target, crc_algorithm);
620 return retval;
621 }
622
623 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
624
625 destroy_reg_param(&reg_params[0]);
626 destroy_reg_param(&reg_params[1]);
627
628 target_free_working_area(target, crc_algorithm);
629
630 return ERROR_OK;
631 }
632
633 int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
634 {
635 working_area_t *erase_check_algorithm;
636 reg_param_t reg_params[3];
637 armv7m_algorithm_t armv7m_info;
638 int retval;
639 int i;
640
641 u16 erase_check_code[] =
642 {
643 /* loop: */
644 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
645 0xEA02, 0x0203, /* and r2, r2, r3 */
646 0x3901, /* subs r1, r1, #1 */
647 0xD1F9, /* bne loop */
648 /* end: */
649 0xE7FE, /* b end */
650 };
651
652 /* make sure we have a working area */
653 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
654 {
655 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
656 }
657
658 /* convert flash writing code into a buffer in target endianness */
659 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
660 target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
661
662 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
663 armv7m_info.core_mode = ARMV7M_MODE_ANY;
664
665 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
666 buf_set_u32(reg_params[0].value, 0, 32, address);
667
668 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
669 buf_set_u32(reg_params[1].value, 0, 32, count);
670
671 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
672 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
673
674 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
675 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
676 {
677 destroy_reg_param(&reg_params[0]);
678 destroy_reg_param(&reg_params[1]);
679 destroy_reg_param(&reg_params[2]);
680 target_free_working_area(target, erase_check_algorithm);
681 return 0;
682 }
683
684 *blank = buf_get_u32(reg_params[2].value, 0, 32);
685
686 destroy_reg_param(&reg_params[0]);
687 destroy_reg_param(&reg_params[1]);
688 destroy_reg_param(&reg_params[2]);
689
690 target_free_working_area(target, erase_check_algorithm);
691
692 return ERROR_OK;
693 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)