1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2006 by Magnus Lundin *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include "replacements.h"
39 #define _DEBUG_INSTRUCTION_EXECUTION_
42 char* armv7m_mode_strings
[] =
47 char* armv7m_state_strings
[] =
52 char* armv7m_exception_strings
[] =
54 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
55 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
58 char* armv7m_core_reg_list
[] =
60 /* Registers accessed through core debug */
61 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
64 /* Registers accessed through MSR instructions */
65 // "apsr", "iapsr", "ipsr", "epsr",
66 "primask", "basepri", "faultmask", "control"
69 char* armv7m_core_dbgreg_list
[] =
71 /* Registers accessed through core debug */
72 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
75 /* Registers accessed through MSR instructions */
76 // "dbg_apsr", "iapsr", "ipsr", "epsr",
77 "primask", "basepri", "faultmask", "dbg_control"
80 u8 armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
82 reg_t armv7m_gdb_dummy_fp_reg
=
84 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
87 armv7m_core_reg_t armv7m_core_reg_list_arch_info
[] =
89 /* CORE_GP are accesible using the core debug registers */
90 {0, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
91 {1, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
92 {2, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
93 {3, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
94 {4, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
95 {5, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
96 {6, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
97 {7, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
98 {8, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
99 {9, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
100 {10, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
101 {11, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
102 {12, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
103 {13, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
104 {14, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
105 {15, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
107 {16, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* xPSR */
108 {17, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* MSP */
109 {18, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PSP */
111 /* CORE_SP are accesible using MSR and MRS instructions */
112 // {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
113 // {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
114 // {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
115 // {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
117 {0x10, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PRIMASK */
118 {0x11, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* BASEPRI */
119 {0x13, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* FAULTMASK */
120 {0x14, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
} /* CONTROL */
123 int armv7m_core_reg_arch_type
= -1;
125 /* Keep different contexts for the process being debugged and debug algorithms */
126 enum armv7m_runcontext
armv7m_get_context(target_t
*target
)
128 /* get pointers to arch-specific information */
129 armv7m_common_t
*armv7m
= target
->arch_info
;
131 if (armv7m
->process_context
== armv7m
->core_cache
)
132 return ARMV7M_PROCESS_CONTEXT
;
133 if (armv7m
->debug_context
== armv7m
->core_cache
)
134 return ARMV7M_DEBUG_CONTEXT
;
136 ERROR("Invalid runcontext");
140 int armv7m_use_context(target_t
*target
, enum armv7m_runcontext new_ctx
)
143 /* get pointers to arch-specific information */
144 armv7m_common_t
*armv7m
= target
->arch_info
;
146 if ((target
->state
!= TARGET_HALTED
) && (target
->state
!= TARGET_RESET
))
148 WARNING("target not halted, switch context ");
149 return ERROR_TARGET_NOT_HALTED
;
152 if (new_ctx
== armv7m_get_context(target
))
157 case ARMV7M_PROCESS_CONTEXT
:
158 armv7m
->core_cache
= armv7m
->process_context
;
160 case ARMV7M_DEBUG_CONTEXT
:
161 armv7m
->core_cache
= armv7m
->debug_context
;
164 ERROR("Invalid runcontext");
167 /* Mark registers in new context as dirty to force reload when run */
169 for (i
= 0; i
< armv7m
->core_cache
->num_regs
-1; i
++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
171 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
177 /* Core state functions */
179 char *armv7m_exception_string(int number
)
181 if ((number
< 0) | (number
> 511))
182 return "Invalid exception";
184 return armv7m_exception_strings
[number
];
185 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
189 int armv7m_get_core_reg(reg_t
*reg
)
192 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
193 target_t
*target
= armv7m_reg
->target
;
194 armv7m_common_t
*armv7m_target
= target
->arch_info
;
196 if (target
->state
!= TARGET_HALTED
)
198 return ERROR_TARGET_NOT_HALTED
;
201 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
206 int armv7m_set_core_reg(reg_t
*reg
, u8
*buf
)
208 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
209 target_t
*target
= armv7m_reg
->target
;
210 armv7m_common_t
*armv7m_target
= target
->arch_info
;
211 u32 value
= buf_get_u32(buf
, 0, 32);
213 if (target
->state
!= TARGET_HALTED
)
215 return ERROR_TARGET_NOT_HALTED
;
218 buf_set_u32(reg
->value
, 0, 32, value
);
225 int armv7m_read_core_reg(struct target_s
*target
, int num
)
229 armv7m_core_reg_t
* armv7m_core_reg
;
231 /* get pointers to arch-specific information */
232 armv7m_common_t
*armv7m
= target
->arch_info
;
234 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
235 return ERROR_INVALID_ARGUMENTS
;
237 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
238 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
239 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
240 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
241 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
246 int armv7m_write_core_reg(struct target_s
*target
, int num
)
250 armv7m_core_reg_t
*armv7m_core_reg
;
252 /* get pointers to arch-specific information */
253 armv7m_common_t
*armv7m
= target
->arch_info
;
255 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
256 return ERROR_INVALID_ARGUMENTS
;
258 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
259 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
260 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
261 if (retval
!= ERROR_OK
)
263 ERROR("JTAG failure");
264 armv7m
->core_cache
->reg_list
[num
].dirty
= 1;
265 return ERROR_JTAG_DEVICE_ERROR
;
267 DEBUG("write core reg %i value 0x%x", num
, reg_value
);
268 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
269 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
274 int armv7m_invalidate_core_regs(target_t
*target
)
276 /* get pointers to arch-specific information */
277 armv7m_common_t
*armv7m
= target
->arch_info
;
280 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
282 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
283 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
289 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
291 /* get pointers to arch-specific information */
292 armv7m_common_t
*armv7m
= target
->arch_info
;
295 if (target
->state
!= TARGET_HALTED
)
297 return ERROR_TARGET_NOT_HALTED
;
301 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
303 /* TODOLATER correct list of registers, names ? */
304 for (i
= 0; i
< *reg_list_size
; i
++)
306 if (i
< ARMV7NUMCOREREGS
)
307 (*reg_list
)[i
] = &armv7m
->process_context
->reg_list
[i
];
308 //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
310 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
312 /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
313 //armv7m->core_cache->reg_list[15].value[0] |= 1;
314 armv7m
->process_context
->reg_list
[15].value
[0] |= 1;
315 //armv7m->core_cache->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
316 //armv7m->process_context->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
317 (*reg_list
)[25] = &armv7m
->process_context
->reg_list
[ARMV7M_xPSR
];
318 //(*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
322 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
324 // get pointers to arch-specific information
325 armv7m_common_t
*armv7m
= target
->arch_info
;
326 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
327 enum armv7m_state core_state
= armv7m
->core_state
;
328 enum armv7m_mode core_mode
= armv7m
->core_mode
;
329 int retval
= ERROR_OK
;
331 int exit_breakpoint_size
= 0;
334 armv7m
->core_state
= core_state
;
335 armv7m
->core_mode
= core_mode
;
337 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
339 ERROR("current target isn't an ARMV7M target");
340 return ERROR_TARGET_INVALID
;
343 if (target
->state
!= TARGET_HALTED
)
345 WARNING("target not halted");
346 return ERROR_TARGET_NOT_HALTED
;
349 /* refresh core register cache */
350 /* Not needed if core register cache is always consistent with target process state */
351 armv7m_use_context(target
, ARMV7M_DEBUG_CONTEXT
);
353 for (i
= 0; i
< num_mem_params
; i
++)
355 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
358 for (i
= 0; i
< num_reg_params
; i
++)
360 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
361 //reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
362 //armv7m_core_reg_t * armv7m_core_reg = reg->arch_info;
367 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
371 if (reg
->size
!= reg_params
[i
].size
)
373 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
377 regvalue
= buf_get_u32(reg_params
[i
].value
, 0, 32);
378 //armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, regvalue);
379 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
382 /* ARMV7M always runs in Thumb state */
383 exit_breakpoint_size
= 2;
384 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_SOFT
)) != ERROR_OK
)
386 ERROR("can't add breakpoint to finish algorithm execution");
387 return ERROR_TARGET_FAILURE
;
390 /* This code relies on the target specific resume() and poll()->debug_entry()
391 sequence to write register values to the processor and the read them back */
392 target
->type
->resume(target
, 0, entry_point
, 1, 1);
393 target
->type
->poll(target
);
395 while (target
->state
!= TARGET_HALTED
)
398 target
->type
->poll(target
);
399 if ((timeout_ms
-= 5) <= 0)
401 ERROR("timeout waiting for algorithm to complete, trying to halt target");
402 target
->type
->halt(target
);
404 while (target
->state
!= TARGET_HALTED
)
407 target
->type
->poll(target
);
408 if ((timeout_ms
-= 10) <= 0)
410 ERROR("target didn't reenter debug state, exiting");
414 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
415 DEBUG("failed algoritm halted at 0x%x ", pc
);
416 retval
= ERROR_TARGET_TIMEOUT
;
420 breakpoint_remove(target
, exit_point
);
422 /* Read memory values to mem_params[] */
423 for (i
= 0; i
< num_mem_params
; i
++)
425 if (mem_params
[i
].direction
!= PARAM_OUT
)
426 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
429 /* Copy core register values to reg_params[] */
430 for (i
= 0; i
< num_reg_params
; i
++)
432 if (reg_params
[i
].direction
!= PARAM_OUT
)
434 //reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
435 reg_t
*reg
= register_get_by_name(armv7m
->debug_context
, reg_params
[i
].reg_name
, 0);
440 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
444 if (reg
->size
!= reg_params
[i
].size
)
446 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
450 armv7m_core_reg_t
*armv7m_core_reg
= reg
->arch_info
;
451 //armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®value);
452 //buf_set_u32(reg_params[i].value, 0, 32, regvalue);
453 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
457 /* Mark all core registers !! except control !! as valid but dirty */
458 /* This will be done by armv7m_use_context in resume function */
459 //for (i = 0; i < armv7m->core_cache->num_regs-1; i++)
461 // armv7m->core_cache->reg_list[i].dirty = 1;
464 // ????armv7m->core_state = core_state;
465 // ????armv7m->core_mode = core_mode;
470 int armv7m_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
472 /* get pointers to arch-specific information */
473 armv7m_common_t
*armv7m
= target
->arch_info
;
475 snprintf(buf
, buf_size
,
476 "target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
477 armv7m_state_strings
[armv7m
->core_state
],
478 target_debug_reason_strings
[target
->debug_reason
],
479 armv7m_mode_strings
[armv7m
->core_mode
],
480 armv7m_exception_string(armv7m
->exception_number
),
481 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
482 buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32));
487 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
489 /* get pointers to arch-specific information */
490 armv7m_common_t
*armv7m
= target
->arch_info
;
491 arm_jtag_t
*jtag_info
= &armv7m
->jtag_info
;
493 int num_regs
= ARMV7NUMCOREREGS
;
494 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
495 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
496 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
497 armv7m_core_reg_t
*arch_info
= malloc(sizeof(armv7m_core_reg_t
) * num_regs
);
500 if (armv7m_core_reg_arch_type
== -1)
501 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
503 /* Build the process context cache */
504 cache
->name
= "arm v7m registers";
506 cache
->reg_list
= reg_list
;
507 cache
->num_regs
= num_regs
;
509 armv7m
->core_cache
= cache
;
510 armv7m
->process_context
= cache
;
512 for (i
= 0; i
< num_regs
; i
++)
514 arch_info
[i
] = armv7m_core_reg_list_arch_info
[i
];
515 arch_info
[i
].target
= target
;
516 arch_info
[i
].armv7m_common
= armv7m
;
517 reg_list
[i
].name
= armv7m_core_reg_list
[i
];
518 reg_list
[i
].size
= 32;
519 reg_list
[i
].value
= calloc(1, 4);
520 reg_list
[i
].dirty
= 0;
521 reg_list
[i
].valid
= 0;
522 reg_list
[i
].bitfield_desc
= NULL
;
523 reg_list
[i
].num_bitfields
= 0;
524 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
525 reg_list
[i
].arch_info
= &arch_info
[i
];
528 /* Build the debug context cache*/
529 cache
= malloc(sizeof(reg_cache_t
));
530 reg_list
= malloc(sizeof(reg_t
) * num_regs
);
532 cache
->name
= "arm v7m debug registers";
534 cache
->reg_list
= reg_list
;
535 cache
->num_regs
= num_regs
;
536 armv7m
->debug_context
= cache
;
537 armv7m
->process_context
->next
= cache
;
539 for (i
= 0; i
< num_regs
; i
++)
541 reg_list
[i
].name
= armv7m_core_dbgreg_list
[i
];
542 reg_list
[i
].size
= 32;
543 reg_list
[i
].value
= calloc(1, 4);
544 reg_list
[i
].dirty
= 0;
545 reg_list
[i
].valid
= 0;
546 reg_list
[i
].bitfield_desc
= NULL
;
547 reg_list
[i
].num_bitfields
= 0;
548 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
549 reg_list
[i
].arch_info
= &arch_info
[i
];
555 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
557 armv7m_build_reg_cache(target
);
562 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
564 /* register arch-specific functions */
566 target
->arch_info
= armv7m
;
567 armv7m
->core_state
= ARMV7M_STATE_THUMB
;
568 armv7m
->read_core_reg
= armv7m_read_core_reg
;
569 armv7m
->write_core_reg
= armv7m_write_core_reg
;
574 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)