src/target/armv7m.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2006 by Magnus Lundin                                   *
   5  *   lundin@mlu.mine.nu                                                    *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "replacements.h"
  27
  28 #include "armv7m.h"
  29 #include "register.h"
  30 #include "target.h"
  31 #include "log.h"
  32 #include "jtag.h"
  33 #include "arm_jtag.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 char* armv7m_mode_strings[] =
  43 {
  44         "Handler", "Thread"
  45 };
  46
  47 char* armv7m_state_strings[] =
  48 {
  49         "Thumb", "Debug"
  50 };
  51
  52 char* armv7m_exception_strings[] =
  53 {
  54         "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
  55         "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  56 };
  57
  58 char* armv7m_core_reg_list[] =
  59 {
  60         /* Registers accessed through core debug */
  61         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  62         "sp", "lr", "pc",
  63         "xPSR", "msp", "psp",
  64         /* Registers accessed through MSR instructions */
  65 //      "apsr", "iapsr", "ipsr", "epsr",
  66         "primask", "basepri", "faultmask", "control"
  67 };
  68
  69 char* armv7m_core_dbgreg_list[] =
  70 {
  71         /* Registers accessed through core debug */
  72         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  73         "sp", "lr", "pc",
  74         "xPSR", "msp", "psp",
  75         /* Registers accessed through MSR instructions */
  76 //      "dbg_apsr", "iapsr", "ipsr", "epsr",
  77         "primask", "basepri", "faultmask", "dbg_control"
  78 };
  79
  80 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  81
  82 reg_t armv7m_gdb_dummy_fp_reg =
  83 {
  84         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  85 };
  86
  87 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  88 {
  89         /*  CORE_GP are accesible using the core debug registers */
  90         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  91         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  92         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  93         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  98         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  99         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 100         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 101         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 102         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 103         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 104         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 105         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 106
 107         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
 108         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 109         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 110
 111         /*  CORE_SP are accesible using MSR and MRS instructions */
 112 //      {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
 113 //      {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
 114 //      {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
 115 //      {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
 116
 117         {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 118         {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 119         {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 120         {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 121 };
 122
 123 int armv7m_core_reg_arch_type = -1;
 124
 125 /* Keep different contexts for the process being debugged and debug algorithms */
 126 enum armv7m_runcontext armv7m_get_context(target_t *target)
 127 {
 128         /* get pointers to arch-specific information */
 129         armv7m_common_t *armv7m = target->arch_info;
 130
 131         if (armv7m->process_context == armv7m->core_cache)
 132                 return ARMV7M_PROCESS_CONTEXT;
 133         if (armv7m->debug_context == armv7m->core_cache)
 134                 return ARMV7M_DEBUG_CONTEXT;
 135
 136         ERROR("Invalid runcontext");
 137         exit(-1);
 138 }
 139
 140 int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
 141 {
 142         int i;
 143         /* get pointers to arch-specific information */
 144         armv7m_common_t *armv7m = target->arch_info;
 145
 146         if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
 147         {
 148                 WARNING("target not halted, switch context ");
 149                 return ERROR_TARGET_NOT_HALTED;
 150         }
 151
 152         if (new_ctx == armv7m_get_context(target))
 153                 return ERROR_OK;
 154
 155         switch (new_ctx)
 156         {
 157                 case ARMV7M_PROCESS_CONTEXT:
 158                          armv7m->core_cache = armv7m->process_context;
 159                          break;
 160                 case ARMV7M_DEBUG_CONTEXT:
 161                          armv7m->core_cache = armv7m->debug_context;
 162                          break;
 163                 default:
 164                         ERROR("Invalid runcontext");
 165                         exit(-1);
 166         }
 167         /* Mark registers in new context as dirty to force reload when run */
 168
 169         for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
 170         {
 171                 armv7m->core_cache->reg_list[i].dirty = 1;
 172         }
 173
 174         return ERROR_OK;
 175 }
 176
 177 int armv7m_restore_context(target_t *target)
 178 {
 179         int i;
 180
 181         /* get pointers to arch-specific information */
 182         armv7m_common_t *armv7m = target->arch_info;
 183
 184         DEBUG(" ");
 185
 186         if (armv7m->pre_restore_context)
 187                 armv7m->pre_restore_context(target);
 188
 189         for (i = ARMV7NUMCOREREGS; i >= 0; i--)
 190         {
 191                 if (armv7m->core_cache->reg_list[i].dirty)
 192                 {
 193                         armv7m->write_core_reg(target, i);
 194                 }
 195         }
 196
 197         if (armv7m->post_restore_context)
 198                 armv7m->post_restore_context(target);
 199
 200         return ERROR_OK;
 201 }
 202
 203
 204 /* Core state functions */
 205 char enamebuf[32];
 206 char *armv7m_exception_string(int number)
 207 {
 208         if ((number < 0) | (number > 511))
 209                 return "Invalid exception";
 210         if (number < 16)
 211                 return armv7m_exception_strings[number];
 212         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 213         return enamebuf;
 214 }
 215
 216 int armv7m_get_core_reg(reg_t *reg)
 217 {
 218         int retval;
 219         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 220         target_t *target = armv7m_reg->target;
 221         armv7m_common_t *armv7m_target = target->arch_info;
 222
 223         if (target->state != TARGET_HALTED)
 224         {
 225                 return ERROR_TARGET_NOT_HALTED;
 226         }
 227
 228         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 229
 230         return retval;
 231 }
 232
 233 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
 234 {
 235         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 236         target_t *target = armv7m_reg->target;
 237         u32 value = buf_get_u32(buf, 0, 32);
 238
 239         if (target->state != TARGET_HALTED)
 240         {
 241                 return ERROR_TARGET_NOT_HALTED;
 242         }
 243
 244         buf_set_u32(reg->value, 0, 32, value);
 245         reg->dirty = 1;
 246         reg->valid = 1;
 247
 248         return ERROR_OK;
 249 }
 250
 251 int armv7m_read_core_reg(struct target_s *target, int num)
 252 {
 253         u32 reg_value;
 254         int retval;
 255         armv7m_core_reg_t * armv7m_core_reg;
 256
 257         /* get pointers to arch-specific information */
 258         armv7m_common_t *armv7m = target->arch_info;
 259
 260         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 261                 return ERROR_INVALID_ARGUMENTS;
 262
 263         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 264         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 265         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 266         armv7m->core_cache->reg_list[num].valid = 1;
 267         armv7m->core_cache->reg_list[num].dirty = 0;
 268
 269         return ERROR_OK;
 270 }
 271
 272 int armv7m_write_core_reg(struct target_s *target, int num)
 273 {
 274         int retval;
 275         u32 reg_value;
 276         armv7m_core_reg_t *armv7m_core_reg;
 277
 278         /* get pointers to arch-specific information */
 279         armv7m_common_t *armv7m = target->arch_info;
 280
 281         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 282                 return ERROR_INVALID_ARGUMENTS;
 283
 284         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 285         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 286         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 287         if (retval != ERROR_OK)
 288         {
 289                 ERROR("JTAG failure");
 290                 armv7m->core_cache->reg_list[num].dirty = 1;
 291                 return ERROR_JTAG_DEVICE_ERROR;
 292         }
 293         DEBUG("write core reg %i value 0x%x", num , reg_value);
 294         armv7m->core_cache->reg_list[num].valid = 1;
 295         armv7m->core_cache->reg_list[num].dirty = 0;
 296
 297         return ERROR_OK;
 298 }
 299
 300 int armv7m_invalidate_core_regs(target_t *target)
 301 {
 302         /* get pointers to arch-specific information */
 303         armv7m_common_t *armv7m = target->arch_info;
 304         int i;
 305
 306         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 307         {
 308                 armv7m->core_cache->reg_list[i].valid = 0;
 309                 armv7m->core_cache->reg_list[i].dirty = 0;
 310         }
 311
 312         return ERROR_OK;
 313 }
 314
 315 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 316 {
 317         /* get pointers to arch-specific information */
 318         armv7m_common_t *armv7m = target->arch_info;
 319         int i;
 320
 321         if (target->state != TARGET_HALTED)
 322         {
 323                 return ERROR_TARGET_NOT_HALTED;
 324         }
 325
 326         *reg_list_size = 26;
 327         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 328
 329         /* TODOLATER correct list of registers, names ? */
 330         for (i = 0; i < *reg_list_size; i++)
 331         {
 332                 if (i < ARMV7NUMCOREREGS)
 333                         (*reg_list)[i] = &armv7m->process_context->reg_list[i];
 334                         //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 335                 else
 336                         (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 337         }
 338         /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
 339         armv7m->process_context->reg_list[15].value[0] |= 1;
 340         (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
 341         return ERROR_OK;
 342 }
 343
 344 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 345 {
 346         // get pointers to arch-specific information
 347         armv7m_common_t *armv7m = target->arch_info;
 348         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 349         enum armv7m_state core_state = armv7m->core_state;
 350         enum armv7m_mode core_mode = armv7m->core_mode;
 351         int retval = ERROR_OK;
 352         u32 pc;
 353         int exit_breakpoint_size = 0;
 354         int i;
 355
 356         armv7m->core_state = core_state;
 357         armv7m->core_mode = core_mode;
 358
 359         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 360         {
 361                 ERROR("current target isn't an ARMV7M target");
 362                 return ERROR_TARGET_INVALID;
 363         }
 364
 365         if (target->state != TARGET_HALTED)
 366         {
 367                 WARNING("target not halted");
 368                 return ERROR_TARGET_NOT_HALTED;
 369         }
 370
 371         /* refresh core register cache */
 372         /* Not needed if core register cache is always consistent with target process state */
 373         armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
 374
 375         for (i = 0; i < num_mem_params; i++)
 376         {
 377                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 378         }
 379
 380         for (i = 0; i < num_reg_params; i++)
 381         {
 382                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 383                 u32 regvalue;
 384
 385                 if (!reg)
 386                 {
 387                         ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 388                         exit(-1);
 389                 }
 390
 391                 if (reg->size != reg_params[i].size)
 392                 {
 393                         ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 394                         exit(-1);
 395                 }
 396
 397                 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 398                 armv7m_set_core_reg(reg, reg_params[i].value);
 399         }
 400
 401         /* ARMV7M always runs in Thumb state */
 402         exit_breakpoint_size = 2;
 403         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
 404         {
 405                 ERROR("can't add breakpoint to finish algorithm execution");
 406                 return ERROR_TARGET_FAILURE;
 407         }
 408
 409         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 410         sequence to write register values to the processor and the read them back */
 411         target->type->resume(target, 0, entry_point, 1, 1);
 412         target->type->poll(target);
 413
 414         while (target->state != TARGET_HALTED)
 415         {
 416                 usleep(5000);
 417                 target->type->poll(target);
 418                 if ((timeout_ms -= 5) <= 0)
 419                 {
 420                         ERROR("timeout waiting for algorithm to complete, trying to halt target");
 421                         target->type->halt(target);
 422                         timeout_ms = 1000;
 423                         while (target->state != TARGET_HALTED)
 424                         {
 425                                 usleep(10000);
 426                                 target->type->poll(target);
 427                                 if ((timeout_ms -= 10) <= 0)
 428                                 {
 429                                         ERROR("target didn't reenter debug state, exiting");
 430                                         exit(-1);
 431                                 }
 432                         }
 433                         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 434                         DEBUG("failed algoritm halted at 0x%x ", pc);
 435                         retval = ERROR_TARGET_TIMEOUT;
 436                 }
 437         }
 438
 439         breakpoint_remove(target, exit_point);
 440
 441         /* Read memory values to mem_params[] */
 442         for (i = 0; i < num_mem_params; i++)
 443         {
 444                 if (mem_params[i].direction != PARAM_OUT)
 445                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 446         }
 447
 448         /* Copy core register values to reg_params[] */
 449         for (i = 0; i < num_reg_params; i++)
 450         {
 451                 if (reg_params[i].direction != PARAM_OUT)
 452                 {
 453                         reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
 454
 455                         if (!reg)
 456                         {
 457                                 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 458                                 exit(-1);
 459                         }
 460
 461                         if (reg->size != reg_params[i].size)
 462                         {
 463                                 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 464                                 exit(-1);
 465                         }
 466
 467                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 468                 }
 469         }
 470
 471         return retval;
 472 }
 473
 474 int armv7m_arch_state(struct target_s *target, char *buf, int buf_size)
 475 {
 476         /* get pointers to arch-specific information */
 477         armv7m_common_t *armv7m = target->arch_info;
 478
 479         snprintf(buf, buf_size,
 480                  "target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
 481                  armv7m_state_strings[armv7m->core_state],
 482                  target_debug_reason_strings[target->debug_reason],
 483                  armv7m_mode_strings[armv7m->core_mode],
 484                  armv7m_exception_string(armv7m->exception_number),
 485                  buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 486                  buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 487
 488         return ERROR_OK;
 489 }
 490
 491 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 492 {
 493         /* get pointers to arch-specific information */
 494         armv7m_common_t *armv7m = target->arch_info;
 495
 496         int num_regs = ARMV7NUMCOREREGS;
 497         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 498         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 499         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 500         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 501         int i;
 502
 503         if (armv7m_core_reg_arch_type == -1)
 504                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 505
 506         /* Build the process context cache */
 507         cache->name = "arm v7m registers";
 508         cache->next = NULL;
 509         cache->reg_list = reg_list;
 510         cache->num_regs = num_regs;
 511         (*cache_p) = cache;
 512         armv7m->core_cache = cache;
 513         armv7m->process_context = cache;
 514
 515         for (i = 0; i < num_regs; i++)
 516         {
 517                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 518                 arch_info[i].target = target;
 519                 arch_info[i].armv7m_common = armv7m;
 520                 reg_list[i].name = armv7m_core_reg_list[i];
 521                 reg_list[i].size = 32;
 522                 reg_list[i].value = calloc(1, 4);
 523                 reg_list[i].dirty = 0;
 524                 reg_list[i].valid = 0;
 525                 reg_list[i].bitfield_desc = NULL;
 526                 reg_list[i].num_bitfields = 0;
 527                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 528                 reg_list[i].arch_info = &arch_info[i];
 529         }
 530
 531         /* Build the debug context cache*/
 532         cache = malloc(sizeof(reg_cache_t));
 533         reg_list = malloc(sizeof(reg_t) * num_regs);
 534
 535         cache->name = "arm v7m debug registers";
 536         cache->next = NULL;
 537         cache->reg_list = reg_list;
 538         cache->num_regs = num_regs;
 539         armv7m->debug_context = cache;
 540         armv7m->process_context->next = cache;
 541
 542         for (i = 0; i < num_regs; i++)
 543         {
 544                 reg_list[i].name = armv7m_core_dbgreg_list[i];
 545                 reg_list[i].size = 32;
 546                 reg_list[i].value = calloc(1, 4);
 547                 reg_list[i].dirty = 0;
 548                 reg_list[i].valid = 0;
 549                 reg_list[i].bitfield_desc = NULL;
 550                 reg_list[i].num_bitfields = 0;
 551                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 552                 reg_list[i].arch_info = &arch_info[i];
 553         }
 554
 555         return cache;
 556 }
 557
 558 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 559 {
 560         armv7m_build_reg_cache(target);
 561
 562         return ERROR_OK;
 563 }
 564
 565 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 566 {
 567         /* register arch-specific functions */
 568
 569         target->arch_info = armv7m;
 570         armv7m->core_state = ARMV7M_STATE_THUMB;
 571         armv7m->read_core_reg = armv7m_read_core_reg;
 572         armv7m->write_core_reg = armv7m_write_core_reg;
 573
 574         return ERROR_OK;
 575 }
 576
 577 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 578 {
 579         return ERROR_OK;
 580 }