1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_ARMV7M_H
26 #define OPENOCD_TARGET_ARMV7M_H
29 #include "armv7m_trace.h"
33 extern const int armv7m_psp_reg_map
[];
34 extern const int armv7m_msp_reg_map
[];
36 const char *armv7m_exception_string(int number
);
38 /* Cortex-M DCRSR.REGSEL selectors */
58 ARMV7M_REGSEL_PC
= 15,
60 ARMV7M_REGSEL_xPSR
= 16,
64 ARMV8M_REGSEL_MSP_NS
= 0x18,
68 ARMV8M_REGSEL_MSPLIM_S
,
69 ARMV8M_REGSEL_PSPLIM_S
,
70 ARMV8M_REGSEL_MSPLIM_NS
,
71 ARMV8M_REGSEL_PSPLIM_NS
,
73 ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL
= 0x14,
74 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S
= 0x22,
75 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS
= 0x23,
76 ARMV7M_REGSEL_FPSCR
= 0x21,
78 /* 32bit Floating-point registers */
79 ARMV7M_REGSEL_S0
= 0x40,
113 /* offsets into armv7m core register cache */
115 /* for convenience, the first set of indices match
116 * the Cortex-M DCRSR.REGSEL selectors
118 ARMV7M_R0
= ARMV7M_REGSEL_R0
,
119 ARMV7M_R1
= ARMV7M_REGSEL_R1
,
120 ARMV7M_R2
= ARMV7M_REGSEL_R2
,
121 ARMV7M_R3
= ARMV7M_REGSEL_R3
,
123 ARMV7M_R4
= ARMV7M_REGSEL_R4
,
124 ARMV7M_R5
= ARMV7M_REGSEL_R5
,
125 ARMV7M_R6
= ARMV7M_REGSEL_R6
,
126 ARMV7M_R7
= ARMV7M_REGSEL_R7
,
128 ARMV7M_R8
= ARMV7M_REGSEL_R8
,
129 ARMV7M_R9
= ARMV7M_REGSEL_R9
,
130 ARMV7M_R10
= ARMV7M_REGSEL_R10
,
131 ARMV7M_R11
= ARMV7M_REGSEL_R11
,
133 ARMV7M_R12
= ARMV7M_REGSEL_R12
,
134 ARMV7M_R13
= ARMV7M_REGSEL_R13
,
135 ARMV7M_R14
= ARMV7M_REGSEL_R14
,
136 ARMV7M_PC
= ARMV7M_REGSEL_PC
,
138 ARMV7M_xPSR
= ARMV7M_REGSEL_xPSR
,
139 ARMV7M_MSP
= ARMV7M_REGSEL_MSP
,
140 ARMV7M_PSP
= ARMV7M_REGSEL_PSP
,
142 /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
144 /* A block of container and contained registers follows:
145 * THE ORDER IS IMPORTANT to the end of the block ! */
146 /* working register for packing/unpacking special regs, hidden from gdb */
147 ARMV7M_PMSK_BPRI_FLTMSK_CTRL
,
149 /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
150 * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
151 * cache only and are not flushed to CPU HW register.
152 * To trigger write to CPU HW register, add
153 * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
159 /* The end of block of container and contained registers */
161 /* ARMv8-M specific registers */
171 /* A block of container and contained registers follows:
172 * THE ORDER IS IMPORTANT to the end of the block ! */
173 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S
,
178 /* The end of block of container and contained registers */
180 /* A block of container and contained registers follows:
181 * THE ORDER IS IMPORTANT to the end of the block ! */
182 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS
,
187 /* The end of block of container and contained registers */
189 /* 64bit Floating-point registers */
207 /* Floating-point status register */
210 /* for convenience add registers' block delimiters */
212 ARMV7M_CORE_FIRST_REG
= ARMV7M_R0
,
213 ARMV7M_CORE_LAST_REG
= ARMV7M_xPSR
,
214 ARMV7M_FPU_FIRST_REG
= ARMV7M_D0
,
215 ARMV7M_FPU_LAST_REG
= ARMV7M_FPSCR
,
216 ARMV8M_FIRST_REG
= ARMV8M_MSP_NS
,
217 ARMV8M_LAST_REG
= ARMV8M_CONTROL_NS
,
227 #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
229 #define ARMV7M_COMMON_MAGIC 0x2A452A45
231 struct armv7m_common
{
235 int exception_number
;
237 /* AP this processor is connected to in the DAP */
238 struct adiv5_ap
*debug_ap
;
243 /* hla_target uses a high level adapter that does not support all functions */
246 struct armv7m_trace_config trace_config
;
248 /* Direct processor core register read and writes */
249 int (*load_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t *value
);
250 int (*store_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t value
);
252 int (*examine_debug_reason
)(struct target
*target
);
253 int (*post_debug_entry
)(struct target
*target
);
255 void (*pre_restore_context
)(struct target
*target
);
258 static inline struct armv7m_common
*
259 target_to_armv7m(struct target
*target
)
261 return container_of(target
->arch_info
, struct armv7m_common
, arm
);
264 static inline bool is_armv7m(const struct armv7m_common
*armv7m
)
266 return armv7m
->common_magic
== ARMV7M_COMMON_MAGIC
;
269 struct armv7m_algorithm
{
272 enum arm_mode core_mode
;
274 uint32_t context
[ARMV7M_LAST_REG
]; /* ARMV7M_NUM_REGS */
277 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
);
278 void armv7m_free_reg_cache(struct target
*target
);
280 enum armv7m_mode
armv7m_number_to_mode(int number
);
281 int armv7m_mode_to_number(enum armv7m_mode mode
);
283 int armv7m_arch_state(struct target
*target
);
284 int armv7m_get_gdb_reg_list(struct target
*target
,
285 struct reg
**reg_list
[], int *reg_list_size
,
286 enum target_register_class reg_class
);
288 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
);
290 int armv7m_run_algorithm(struct target
*target
,
291 int num_mem_params
, struct mem_param
*mem_params
,
292 int num_reg_params
, struct reg_param
*reg_params
,
293 target_addr_t entry_point
, target_addr_t exit_point
,
294 int timeout_ms
, void *arch_info
);
296 int armv7m_start_algorithm(struct target
*target
,
297 int num_mem_params
, struct mem_param
*mem_params
,
298 int num_reg_params
, struct reg_param
*reg_params
,
299 target_addr_t entry_point
, target_addr_t exit_point
,
302 int armv7m_wait_algorithm(struct target
*target
,
303 int num_mem_params
, struct mem_param
*mem_params
,
304 int num_reg_params
, struct reg_param
*reg_params
,
305 target_addr_t exit_point
, int timeout_ms
,
308 int armv7m_invalidate_core_regs(struct target
*target
);
310 int armv7m_restore_context(struct target
*target
);
312 int armv7m_checksum_memory(struct target
*target
,
313 target_addr_t address
, uint32_t count
, uint32_t *checksum
);
314 int armv7m_blank_check_memory(struct target
*target
,
315 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
);
317 int armv7m_maybe_skip_bkpt_inst(struct target
*target
, bool *inst_found
);
319 extern const struct command_registration armv7m_command_handlers
[];
321 #endif /* OPENOCD_TARGET_ARMV7M_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)