src/target/armv7m.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV7M_COMMON_H
  27 #define ARMV7M_COMMON_H
  28
  29 #include "arm_adi_v5.h"
  30
  31 /* define for enabling armv7 gdb workarounds */
  32 #if 1
  33 #define ARMV7_GDB_HACKS
  34 #endif
  35
  36 enum armv7m_mode
  37 {
  38         ARMV7M_MODE_THREAD = 0,
  39         ARMV7M_MODE_USER_THREAD = 1,
  40         ARMV7M_MODE_HANDLER = 2,
  41         ARMV7M_MODE_ANY = -1
  42 };
  43
  44 extern char *armv7m_mode_strings[];
  45
  46 enum armv7m_regtype
  47 {
  48         ARMV7M_REGISTER_CORE_GP,
  49         ARMV7M_REGISTER_CORE_SP,
  50         ARMV7M_REGISTER_MEMMAP
  51 };
  52
  53 char *armv7m_exception_string(int number);
  54
  55 /* offsets into armv7m core register cache */
  56 enum
  57 {
  58         /* for convenience, the first set of indices match
  59          * the Cortex-M3 DCRSR selectors
  60          */
  61         ARMV7M_R0,
  62         ARMV7M_R1,
  63         ARMV7M_R2,
  64         ARMV7M_R3,
  65
  66         ARMV7M_R4,
  67         ARMV7M_R5,
  68         ARMV7M_R6,
  69         ARMV7M_R7,
  70
  71         ARMV7M_R8,
  72         ARMV7M_R9,
  73         ARMV7M_R10,
  74         ARMV7M_R11,
  75
  76         ARMV7M_R12,
  77         ARMV7M_R13,
  78         ARMV7M_R14,
  79         ARMV7M_PC = 15,
  80
  81         ARMV7M_xPSR = 16,
  82         ARMV7M_MSP,
  83         ARMV7M_PSP,
  84
  85         /* this next set of indices is arbitrary */
  86         ARMV7M_PRIMASK,
  87         ARMV7M_BASEPRI,
  88         ARMV7M_FAULTMASK,
  89         ARMV7M_CONTROL,
  90 };
  91
  92 #define ARMV7M_COMMON_MAGIC 0x2A452A45
  93
  94 typedef struct armv7m_common_s
  95 {
  96         int common_magic;
  97         reg_cache_t *core_cache;
  98         enum armv7m_mode core_mode;
  99         int exception_number;
 100         swjdp_common_t swjdp_info;
 101
 102         /* Direct processor core register read and writes */
 103         int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
 104         int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
 105         /* register cache to processor synchronization */
 106         int (*read_core_reg)(struct target_s *target, int num);
 107         int (*write_core_reg)(struct target_s *target, int num);
 108
 109         int (*examine_debug_reason)(target_t *target);
 110         void (*post_debug_entry)(target_t *target);
 111
 112         void (*pre_restore_context)(target_t *target);
 113         void (*post_restore_context)(target_t *target);
 114 } armv7m_common_t;
 115
 116 static inline struct armv7m_common_s *
 117 target_to_armv7m(struct target_s *target)
 118 {
 119         return target->arch_info;
 120 }
 121
 122 typedef struct armv7m_algorithm_s
 123 {
 124         int common_magic;
 125
 126         enum armv7m_mode core_mode;
 127 } armv7m_algorithm_t;
 128
 129 typedef struct armv7m_core_reg_s
 130 {
 131         uint32_t num;
 132         enum armv7m_regtype type;
 133         target_t *target;
 134         armv7m_common_t *armv7m_common;
 135 } armv7m_core_reg_t;
 136
 137 reg_cache_t *armv7m_build_reg_cache(target_t *target);
 138 enum armv7m_mode armv7m_number_to_mode(int number);
 139 int armv7m_mode_to_number(enum armv7m_mode mode);
 140
 141 int armv7m_arch_state(struct target_s *target);
 142 int armv7m_get_gdb_reg_list(target_t *target,
 143                 reg_t **reg_list[], int *reg_list_size);
 144
 145 int armv7m_register_commands(struct command_context_s *cmd_ctx);
 146 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
 147
 148 int armv7m_run_algorithm(struct target_s *target,
 149                 int num_mem_params, mem_param_t *mem_params,
 150                 int num_reg_params, reg_param_t *reg_params,
 151                 uint32_t entry_point, uint32_t exit_point,
 152                 int timeout_ms, void *arch_info);
 153
 154 int armv7m_invalidate_core_regs(target_t *target);
 155
 156 int armv7m_restore_context(target_t *target);
 157
 158 int armv7m_checksum_memory(struct target_s *target,
 159                 uint32_t address, uint32_t count, uint32_t* checksum);
 160 int armv7m_blank_check_memory(struct target_s *target,
 161                 uint32_t address, uint32_t count, uint32_t* blank);
 162
 163 /* Thumb mode instructions
 164  */
 165
 166 /* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 167  * Rd: destination register
 168  * SYSm: source special register
 169  */
 170 #define ARMV7M_T_MRS(Rd, SYSm)  ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
 171
 172 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 173  * Rd: source register
 174  * SYSm: destination special register
 175  */
 176 #define ARMV7M_T_MSR(SYSm, Rn)  ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
 177
 178 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
 179  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
 180  * Rd: source register
 181  * IF:
 182  */
 183 #define I_FLAG 2
 184 #define F_FLAG 1
 185 #define ARMV7M_T_CPSID(IF)      ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
 186 #define ARMV7M_T_CPSIE(IF)      ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
 187
 188 /* Breakpoint (Thumb mode) v5 onwards
 189  * Im: immediate value used by debugger
 190  */
 191 #define ARMV7M_T_BKPT(Im)       ((0xBE00 | Im) | ((0xBE00 | Im) << 16))
 192
 193 /* Store register (Thumb mode)
 194  * Rd: source register
 195  * Rn: base register
 196  */
 197 #define ARMV7M_T_STR(Rd, Rn)    ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
 198
 199 /* Load register (Thumb state)
 200  * Rd: destination register
 201  * Rn: base register
 202  */
 203 #define ARMV7M_T_LDR(Rd, Rn)    ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
 204
 205 /* Load multiple (Thumb state)
 206  * Rn: base register
 207  * List: for each bit in list: store register
 208  */
 209 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
 210
 211 /* Load register with PC relative addressing
 212  * Rd: register to load
 213  */
 214 #define ARMV7M_T_LDR_PCREL(Rd)  ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
 215
 216 /* Move hi register (Thumb mode)
 217  * Rd: destination register
 218  * Rm: source register
 219  */
 220 #define ARMV7M_T_MOV(Rd, Rm)    ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
 221
 222 /* No operation (Thumb mode)
 223  */
 224 #define ARMV7M_T_NOP    (0x46c0 | (0x46c0 << 16))
 225
 226 /* Move immediate to register (Thumb state)
 227  * Rd: destination register
 228  * Im: 8-bit immediate value
 229  */
 230 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
 231
 232 /* Branch and Exchange
 233  * Rm: register containing branch target
 234  */
 235 #define ARMV7M_T_BX(Rm)         ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
 236
 237 /* Branch (Thumb state)
 238  * Imm: Branch target
 239  */
 240 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
 241
 242 #endif /* ARMV7M_H */