src/target/armv7m.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARMV7M_COMMON_H
  24 #define ARMV7M_COMMON_H
  25
  26 #include "register.h"
  27 #include "target.h"
  28 #include "arm_jtag.h"
  29
  30 /* define for enabling armv7 gdb workarounds */
  31 #if 1
  32 #define ARMV7_GDB_HACKS
  33 #endif
  34
  35 enum armv7m_mode
  36 {
  37         ARMV7M_MODE_THREAD = 0,
  38         ARMV7M_MODE_USER_THREAD = 1,
  39         ARMV7M_MODE_HANDLER = 2,
  40         ARMV7M_MODE_ANY = -1
  41 };
  42
  43 extern char* armv7m_mode_strings[];
  44
  45 enum armv7m_regtype
  46 {
  47         ARMV7M_REGISTER_CORE_GP,
  48         ARMV7M_REGISTER_CORE_SP,
  49         ARMV7M_REGISTER_MEMMAP
  50 };
  51
  52 extern char* armv7m_exception_strings[];
  53
  54 extern char *armv7m_exception_string(int number);
  55
  56 /* offsets into armv7m core register cache */
  57 enum
  58 {
  59         ARMV7M_PC = 15,
  60         ARMV7M_xPSR = 16,
  61         ARMV7M_MSP,
  62         ARMV7M_PSP,
  63         ARMV7M_PRIMASK,
  64         ARMV7M_BASEPRI,
  65         ARMV7M_FAULTMASK,
  66         ARMV7M_CONTROL,
  67         ARMV7NUMCOREREGS
  68 };
  69
  70 #define ARMV7M_COMMON_MAGIC 0x2A452A45
  71
  72 typedef struct armv7m_common_s
  73 {
  74         int common_magic;
  75         reg_cache_t *core_cache;
  76         enum armv7m_mode core_mode;
  77         int exception_number;
  78
  79         /* Direct processor core register read and writes */
  80         int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
  81         int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
  82         /* register cache to processor synchronization */
  83         int (*read_core_reg)(struct target_s *target, int num);
  84         int (*write_core_reg)(struct target_s *target, int num);
  85
  86         int (*examine_debug_reason)(target_t *target);
  87         void (*pre_debug_entry)(target_t *target);
  88         void (*post_debug_entry)(target_t *target);
  89
  90         void (*pre_restore_context)(target_t *target);
  91         void (*post_restore_context)(target_t *target);
  92
  93         void *arch_info;
  94 } armv7m_common_t;
  95
  96 typedef struct armv7m_algorithm_s
  97 {
  98         int common_magic;
  99
 100         enum armv7m_mode core_mode;
 101 } armv7m_algorithm_t;
 102
 103 typedef struct armv7m_core_reg_s
 104 {
 105         u32 num;
 106         enum armv7m_regtype type;
 107         enum armv7m_mode mode;
 108         target_t *target;
 109         armv7m_common_t *armv7m_common;
 110 } armv7m_core_reg_t;
 111
 112 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
 113 extern enum armv7m_mode armv7m_number_to_mode(int number);
 114 extern int armv7m_mode_to_number(enum armv7m_mode mode);
 115
 116 extern int armv7m_arch_state(struct target_s *target);
 117 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 118 extern int armv7m_invalidate_core_regs(target_t *target);
 119
 120 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
 121 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
 122
 123 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 124
 125 extern int armv7m_invalidate_core_regs(target_t *target);
 126
 127 extern int armv7m_restore_context(target_t *target);
 128
 129 extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 130 extern int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
 131
 132 /* Thumb mode instructions
 133  */
 134
 135 /* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 136  * Rd: destination register
 137  * SYSm: source special register
 138  */
 139 #define ARMV7M_T_MRS(Rd, SYSm)  ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
 140
 141 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 142  * Rd: source register
 143  * SYSm: destination special register
 144  */
 145 #define ARMV7M_T_MSR(SYSm, Rn)  ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
 146
 147 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
 148  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
 149  * Rd: source register
 150  * IF:
 151  */
 152 #define I_FLAG 2
 153 #define F_FLAG 1
 154 #define ARMV7M_T_CPSID(IF)      ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
 155 #define ARMV7M_T_CPSIE(IF)      ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
 156
 157 /* Breakpoint (Thumb mode) v5 onwards
 158  * Im: immediate value used by debugger
 159  */
 160 #define ARMV7M_T_BKPT(Im)       ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
 161
 162 /* Store register (Thumb mode)
 163  * Rd: source register
 164  * Rn: base register
 165  */
 166 #define ARMV7M_T_STR(Rd, Rn)    ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
 167
 168 /* Load register (Thumb state)
 169  * Rd: destination register
 170  * Rn: base register
 171  */
 172 #define ARMV7M_T_LDR(Rd, Rn)    ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
 173
 174 /* Load multiple (Thumb state)
 175  * Rn: base register
 176  * List: for each bit in list: store register
 177  */
 178 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
 179
 180 /* Load register with PC relative addressing
 181  * Rd: register to load
 182  */
 183 #define ARMV7M_T_LDR_PCREL(Rd)  ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
 184
 185 /* Move hi register (Thumb mode)
 186  * Rd: destination register
 187  * Rm: source register
 188  */
 189 #define ARMV7M_T_MOV(Rd, Rm)    ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
 190
 191 /* No operation (Thumb mode)
 192  */
 193 #define ARMV7M_T_NOP    (0x46c0 | (0x46c0 << 16))
 194
 195 /* Move immediate to register (Thumb state)
 196  * Rd: destination register
 197  * Im: 8-bit immediate value
 198  */
 199 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
 200
 201 /* Branch and Exchange
 202  * Rm: register containing branch target
 203  */
 204 #define ARMV7M_T_BX(Rm)         ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
 205
 206 /* Branch (Thumb state)
 207  * Imm: Branch target
 208  */
 209 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
 210
 211 #endif /* ARMV7M_H */