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aarch64: enable aarch32 debugging with arm gdb
[openocd.git] / src / target / armv8.c
1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include <helper/replacements.h>
24
25 #include "armv8.h"
26 #include "arm_disassembler.h"
27
28 #include "register.h"
29 #include <helper/binarybuffer.h>
30 #include <helper/command.h>
31
32 #include <stdlib.h>
33 #include <string.h>
34 #include <unistd.h>
35
36 #include "armv8_opcodes.h"
37 #include "target.h"
38 #include "target_type.h"
39
40 #define __unused __attribute__((unused))
41
42 static const char * const armv8_state_strings[] = {
43 "AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
44 };
45
46 static const struct {
47 const char *name;
48 unsigned psr;
49 /* For user and system modes, these list indices for all registers.
50 * otherwise they're just indices for the shadow registers and SPSR.
51 */
52 unsigned short n_indices;
53 const uint8_t *indices;
54 } armv8_mode_data[] = {
55 /* These special modes are currently only supported
56 * by ARMv6M and ARMv7M profiles */
57 {
58 .name = "USR",
59 .psr = ARM_MODE_USR,
60 },
61 {
62 .name = "FIQ",
63 .psr = ARM_MODE_FIQ,
64 },
65 {
66 .name = "IRQ",
67 .psr = ARM_MODE_IRQ,
68 },
69 {
70 .name = "SVC",
71 .psr = ARM_MODE_SVC,
72 },
73 {
74 .name = "MON",
75 .psr = ARM_MODE_MON,
76 },
77 {
78 .name = "ABT",
79 .psr = ARM_MODE_ABT,
80 },
81 {
82 .name = "EL0T",
83 .psr = ARMV8_64_EL0T,
84 },
85 {
86 .name = "EL1T",
87 .psr = ARMV8_64_EL1T,
88 },
89 {
90 .name = "EL1H",
91 .psr = ARMV8_64_EL1H,
92 },
93 {
94 .name = "EL2T",
95 .psr = ARMV8_64_EL2T,
96 },
97 {
98 .name = "EL2H",
99 .psr = ARMV8_64_EL2H,
100 },
101 {
102 .name = "EL3T",
103 .psr = ARMV8_64_EL3T,
104 },
105 {
106 .name = "EL3H",
107 .psr = ARMV8_64_EL3H,
108 },
109 };
110
111 /** Map PSR mode bits to the name of an ARM processor operating mode. */
112 const char *armv8_mode_name(unsigned psr_mode)
113 {
114 for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
115 if (armv8_mode_data[i].psr == psr_mode)
116 return armv8_mode_data[i].name;
117 }
118 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
119 return "UNRECOGNIZED";
120 }
121
122 int armv8_mode_to_number(enum arm_mode mode)
123 {
124 switch (mode) {
125 case ARM_MODE_ANY:
126 /* map MODE_ANY to user mode */
127 case ARM_MODE_USR:
128 return 0;
129 case ARM_MODE_FIQ:
130 return 1;
131 case ARM_MODE_IRQ:
132 return 2;
133 case ARM_MODE_SVC:
134 return 3;
135 case ARM_MODE_ABT:
136 return 4;
137 case ARM_MODE_UND:
138 return 5;
139 case ARM_MODE_SYS:
140 return 6;
141 case ARM_MODE_MON:
142 return 7;
143 case ARMV8_64_EL0T:
144 return 8;
145 case ARMV8_64_EL1T:
146 return 9;
147 case ARMV8_64_EL1H:
148 return 10;
149 case ARMV8_64_EL2T:
150 return 11;
151 case ARMV8_64_EL2H:
152 return 12;
153 case ARMV8_64_EL3T:
154 return 13;
155 case ARMV8_64_EL3H:
156 return 14;
157
158 default:
159 LOG_ERROR("invalid mode value encountered %d", mode);
160 return -1;
161 }
162 }
163
164 static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
165 {
166 struct arm_dpm *dpm = &armv8->dpm;
167 int retval;
168 uint32_t value;
169 uint64_t value_64;
170
171 switch (regnum) {
172 case 0 ... 30:
173 retval = dpm->instr_read_data_dcc_64(dpm,
174 ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, regnum), &value_64);
175 break;
176 case ARMV8_SP:
177 retval = dpm->instr_read_data_r0_64(dpm,
178 ARMV8_MOVFSP_64(0), &value_64);
179 break;
180 case ARMV8_PC:
181 retval = dpm->instr_read_data_r0_64(dpm,
182 ARMV8_MRS_DLR(0), &value_64);
183 break;
184 case ARMV8_xPSR:
185 retval = dpm->instr_read_data_r0(dpm,
186 ARMV8_MRS_DSPSR(0), &value);
187 value_64 = value;
188 break;
189 case ARMV8_ELR_EL1:
190 retval = dpm->instr_read_data_r0_64(dpm,
191 ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64);
192 break;
193 case ARMV8_ELR_EL2:
194 retval = dpm->instr_read_data_r0_64(dpm,
195 ARMV8_MRS(SYSTEM_ELR_EL2, 0), &value_64);
196 break;
197 case ARMV8_ELR_EL3:
198 retval = dpm->instr_read_data_r0_64(dpm,
199 ARMV8_MRS(SYSTEM_ELR_EL3, 0), &value_64);
200 break;
201 case ARMV8_ESR_EL1:
202 retval = dpm->instr_read_data_r0(dpm,
203 ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value);
204 value_64 = value;
205 break;
206 case ARMV8_ESR_EL2:
207 retval = dpm->instr_read_data_r0(dpm,
208 ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value);
209 value_64 = value;
210 break;
211 case ARMV8_ESR_EL3:
212 retval = dpm->instr_read_data_r0(dpm,
213 ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value);
214 value_64 = value;
215 break;
216 case ARMV8_SPSR_EL1:
217 retval = dpm->instr_read_data_r0(dpm,
218 ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value);
219 value_64 = value;
220 break;
221 case ARMV8_SPSR_EL2:
222 retval = dpm->instr_read_data_r0(dpm,
223 ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value);
224 value_64 = value;
225 break;
226 case ARMV8_SPSR_EL3:
227 retval = dpm->instr_read_data_r0(dpm,
228 ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value);
229 value_64 = value;
230 break;
231 default:
232 retval = ERROR_FAIL;
233 break;
234 }
235
236 if (retval == ERROR_OK && regval != NULL)
237 *regval = value_64;
238
239 return retval;
240 }
241
242 static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64)
243 {
244 struct arm_dpm *dpm = &armv8->dpm;
245 int retval;
246 uint32_t value;
247
248 switch (regnum) {
249 case 0 ... 30:
250 retval = dpm->instr_write_data_dcc_64(dpm,
251 ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, regnum),
252 value_64);
253 break;
254 case ARMV8_SP:
255 retval = dpm->instr_write_data_r0_64(dpm,
256 ARMV8_MOVTSP_64(0),
257 value_64);
258 break;
259 case ARMV8_PC:
260 retval = dpm->instr_write_data_r0_64(dpm,
261 ARMV8_MSR_DLR(0),
262 value_64);
263 break;
264 case ARMV8_xPSR:
265 value = value_64;
266 retval = dpm->instr_write_data_r0(dpm,
267 ARMV8_MSR_DSPSR(0),
268 value);
269 break;
270 /* registers clobbered by taking exception in debug state */
271 case ARMV8_ELR_EL1:
272 retval = dpm->instr_write_data_r0_64(dpm,
273 ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64);
274 break;
275 case ARMV8_ELR_EL2:
276 retval = dpm->instr_write_data_r0_64(dpm,
277 ARMV8_MSR_GP(SYSTEM_ELR_EL2, 0), value_64);
278 break;
279 case ARMV8_ELR_EL3:
280 retval = dpm->instr_write_data_r0_64(dpm,
281 ARMV8_MSR_GP(SYSTEM_ELR_EL3, 0), value_64);
282 break;
283 case ARMV8_ESR_EL1:
284 value = value_64;
285 retval = dpm->instr_write_data_r0(dpm,
286 ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value);
287 break;
288 case ARMV8_ESR_EL2:
289 value = value_64;
290 retval = dpm->instr_write_data_r0(dpm,
291 ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value);
292 break;
293 case ARMV8_ESR_EL3:
294 value = value_64;
295 retval = dpm->instr_write_data_r0(dpm,
296 ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value);
297 break;
298 case ARMV8_SPSR_EL1:
299 value = value_64;
300 retval = dpm->instr_write_data_r0(dpm,
301 ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value);
302 break;
303 case ARMV8_SPSR_EL2:
304 value = value_64;
305 retval = dpm->instr_write_data_r0(dpm,
306 ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value);
307 break;
308 case ARMV8_SPSR_EL3:
309 value = value_64;
310 retval = dpm->instr_write_data_r0(dpm,
311 ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value);
312 break;
313 default:
314 retval = ERROR_FAIL;
315 break;
316 }
317
318 return retval;
319 }
320
321 static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *regval)
322 {
323 struct arm_dpm *dpm = &armv8->dpm;
324 uint32_t value = 0;
325 int retval;
326
327 switch (regnum) {
328 case ARMV8_R0 ... ARMV8_R14:
329 /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
330 retval = dpm->instr_read_data_dcc(dpm,
331 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
332 &value);
333 break;
334 case ARMV8_SP:
335 retval = dpm->instr_read_data_dcc(dpm,
336 ARMV4_5_MCR(14, 0, 13, 0, 5, 0),
337 &value);
338 break;
339 case ARMV8_PC:
340 retval = dpm->instr_read_data_r0(dpm,
341 ARMV8_MRC_DLR(0),
342 &value);
343 break;
344 case ARMV8_xPSR:
345 retval = dpm->instr_read_data_r0(dpm,
346 ARMV8_MRC_DSPSR(0),
347 &value);
348 break;
349 case ARMV8_ELR_EL1: /* mapped to LR_svc */
350 retval = dpm->instr_read_data_dcc(dpm,
351 ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
352 &value);
353 break;
354 case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
355 retval = dpm->instr_read_data_r0(dpm,
356 ARMV8_MRS_T1(0, 14, 0, 1),
357 &value);
358 break;
359 case ARMV8_ELR_EL3: /* mapped to LR_mon */
360 retval = dpm->instr_read_data_dcc(dpm,
361 ARMV4_5_MCR(14, 0, 14, 0, 5, 0),
362 &value);
363 break;
364 case ARMV8_ESR_EL1: /* mapped to DFSR */
365 retval = dpm->instr_read_data_r0(dpm,
366 ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
367 &value);
368 break;
369 case ARMV8_ESR_EL2: /* mapped to HSR */
370 retval = dpm->instr_read_data_r0(dpm,
371 ARMV4_5_MRC(15, 4, 0, 5, 2, 0),
372 &value);
373 break;
374 case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
375 retval = ERROR_FAIL;
376 break;
377 case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
378 retval = dpm->instr_read_data_r0(dpm,
379 ARMV8_MRS_xPSR_T1(1, 0),
380 &value);
381 break;
382 case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
383 retval = dpm->instr_read_data_r0(dpm,
384 ARMV8_MRS_xPSR_T1(1, 0),
385 &value);
386 break;
387 case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
388 retval = dpm->instr_read_data_r0(dpm,
389 ARMV8_MRS_xPSR_T1(1, 0),
390 &value);
391 break;
392 default:
393 retval = ERROR_FAIL;
394 break;
395 }
396
397 if (retval == ERROR_OK && regval != NULL)
398 *regval = value;
399
400 return retval;
401 }
402
403 static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t value)
404 {
405 struct arm_dpm *dpm = &armv8->dpm;
406 int retval;
407
408 switch (regnum) {
409 case ARMV8_R0 ... ARMV8_R14:
410 /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
411 retval = dpm->instr_write_data_dcc(dpm,
412 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), value);
413 break;
414 case ARMV8_SP:
415 retval = dpm->instr_write_data_dcc(dpm,
416 ARMV4_5_MRC(14, 0, 13, 0, 5, 0),
417 value);
418 break;
419 case ARMV8_PC:/* PC
420 * read r0 from DCC; then "MOV pc, r0" */
421 retval = dpm->instr_write_data_r0(dpm,
422 ARMV8_MCR_DLR(0), value);
423 break;
424 case ARMV8_xPSR: /* CPSR */
425 /* read r0 from DCC, then "MCR r0, DSPSR" */
426 retval = dpm->instr_write_data_r0(dpm,
427 ARMV8_MCR_DSPSR(0), value);
428 break;
429 case ARMV8_ELR_EL1: /* mapped to LR_svc */
430 retval = dpm->instr_write_data_dcc(dpm,
431 ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
432 value);
433 break;
434 case ARMV8_ELR_EL2: /* mapped to ELR_hyp */
435 retval = dpm->instr_write_data_r0(dpm,
436 ARMV8_MSR_GP_T1(0, 14, 0, 1),
437 value);
438 break;
439 case ARMV8_ELR_EL3: /* mapped to LR_mon */
440 retval = dpm->instr_write_data_dcc(dpm,
441 ARMV4_5_MRC(14, 0, 14, 0, 5, 0),
442 value);
443 break;
444 case ARMV8_ESR_EL1: /* mapped to DFSR */
445 retval = dpm->instr_write_data_r0(dpm,
446 ARMV4_5_MCR(15, 0, 0, 5, 0, 0),
447 value);
448 break;
449 case ARMV8_ESR_EL2: /* mapped to HSR */
450 retval = dpm->instr_write_data_r0(dpm,
451 ARMV4_5_MCR(15, 4, 0, 5, 2, 0),
452 value);
453 break;
454 case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
455 retval = ERROR_FAIL;
456 break;
457 case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
458 retval = dpm->instr_write_data_r0(dpm,
459 ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
460 value);
461 break;
462 case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
463 retval = dpm->instr_write_data_r0(dpm,
464 ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
465 value);
466 break;
467 case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
468 retval = dpm->instr_write_data_r0(dpm,
469 ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
470 value);
471 break;
472 default:
473 retval = ERROR_FAIL;
474 break;
475 }
476
477 return retval;
478
479 }
480
481 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64)
482 {
483 if (is_aarch64) {
484 armv8->read_reg_u64 = armv8_read_reg;
485 armv8->write_reg_u64 = armv8_write_reg;
486 } else {
487 armv8->read_reg_u64 = armv8_read_reg32;
488 armv8->write_reg_u64 = armv8_write_reg32;
489 }
490 }
491
492 /* retrieve core id cluster id */
493 int armv8_read_mpidr(struct armv8_common *armv8)
494 {
495 int retval = ERROR_FAIL;
496 struct arm_dpm *dpm = armv8->arm.dpm;
497 uint32_t mpidr;
498
499 retval = dpm->prepare(dpm);
500 if (retval != ERROR_OK)
501 goto done;
502
503 retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
504 if (retval != ERROR_OK)
505 goto done;
506 if (mpidr & 1<<31) {
507 armv8->multi_processor_system = (mpidr >> 30) & 1;
508 armv8->cluster_id = (mpidr >> 8) & 0xf;
509 armv8->cpu_id = mpidr & 0x3;
510 LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
511 armv8->cluster_id,
512 armv8->cpu_id,
513 armv8->multi_processor_system == 0 ? "multi core" : "mono core");
514
515 } else
516 LOG_ERROR("mpdir not in multiprocessor format");
517
518 done:
519 dpm->finish(dpm);
520 return retval;
521 }
522
523 /**
524 * Configures host-side ARM records to reflect the specified CPSR.
525 * Later, code can use arm_reg_current() to map register numbers
526 * according to how they are exposed by this mode.
527 */
528 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
529 {
530 uint32_t mode = cpsr & 0x1F;
531
532 /* NOTE: this may be called very early, before the register
533 * cache is set up. We can't defend against many errors, in
534 * particular against CPSRs that aren't valid *here* ...
535 */
536 if (arm->cpsr) {
537 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
538 arm->cpsr->valid = 1;
539 arm->cpsr->dirty = 0;
540 }
541
542 /* Older ARMs won't have the J bit */
543 enum arm_state state = 0xFF;
544
545 if (((cpsr & 0x10) >> 4) == 0) {
546 state = ARM_STATE_AARCH64;
547 } else {
548 if (cpsr & (1 << 5)) { /* T */
549 if (cpsr & (1 << 24)) { /* J */
550 LOG_WARNING("ThumbEE -- incomplete support");
551 state = ARM_STATE_THUMB_EE;
552 } else
553 state = ARM_STATE_THUMB;
554 } else {
555 if (cpsr & (1 << 24)) { /* J */
556 LOG_ERROR("Jazelle state handling is BROKEN!");
557 state = ARM_STATE_JAZELLE;
558 } else
559 state = ARM_STATE_ARM;
560 }
561 }
562 arm->core_state = state;
563 if (arm->core_state == ARM_STATE_AARCH64)
564 arm->core_mode = (mode << 4) | 0xf;
565 else
566 arm->core_mode = mode;
567
568 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
569 armv8_mode_name(arm->core_mode),
570 armv8_state_strings[arm->core_state]);
571 }
572
573 static void armv8_show_fault_registers32(struct armv8_common *armv8)
574 {
575 uint32_t dfsr, ifsr, dfar, ifar;
576 struct arm_dpm *dpm = armv8->arm.dpm;
577 int retval;
578
579 retval = dpm->prepare(dpm);
580 if (retval != ERROR_OK)
581 return;
582
583 /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
584
585 /* c5/c0 - {data, instruction} fault status registers */
586 retval = dpm->instr_read_data_r0(dpm,
587 ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
588 &dfsr);
589 if (retval != ERROR_OK)
590 goto done;
591
592 retval = dpm->instr_read_data_r0(dpm,
593 ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
594 &ifsr);
595 if (retval != ERROR_OK)
596 goto done;
597
598 /* c6/c0 - {data, instruction} fault address registers */
599 retval = dpm->instr_read_data_r0(dpm,
600 ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
601 &dfar);
602 if (retval != ERROR_OK)
603 goto done;
604
605 retval = dpm->instr_read_data_r0(dpm,
606 ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
607 &ifar);
608 if (retval != ERROR_OK)
609 goto done;
610
611 LOG_USER("Data fault registers DFSR: %8.8" PRIx32
612 ", DFAR: %8.8" PRIx32, dfsr, dfar);
613 LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
614 ", IFAR: %8.8" PRIx32, ifsr, ifar);
615
616 done:
617 /* (void) */ dpm->finish(dpm);
618 }
619
620 static void armv8_show_fault_registers(struct target *target)
621 {
622 struct armv8_common *armv8 = target_to_armv8(target);
623
624 if (armv8->arm.core_state != ARM_STATE_AARCH64)
625 armv8_show_fault_registers32(armv8);
626 }
627
628 static uint8_t armv8_pa_size(uint32_t ps)
629 {
630 uint8_t ret = 0;
631 switch (ps) {
632 case 0:
633 ret = 32;
634 break;
635 case 1:
636 ret = 36;
637 break;
638 case 2:
639 ret = 40;
640 break;
641 case 3:
642 ret = 42;
643 break;
644 case 4:
645 ret = 44;
646 break;
647 case 5:
648 ret = 48;
649 break;
650 default:
651 LOG_INFO("Unknow physicall address size");
652 break;
653 }
654 return ret;
655 }
656
657 static __unused int armv8_read_ttbcr32(struct target *target)
658 {
659 struct armv8_common *armv8 = target_to_armv8(target);
660 struct arm_dpm *dpm = armv8->arm.dpm;
661 uint32_t ttbcr, ttbcr_n;
662 int retval = dpm->prepare(dpm);
663 if (retval != ERROR_OK)
664 goto done;
665 /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
666 retval = dpm->instr_read_data_r0(dpm,
667 ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
668 &ttbcr);
669 if (retval != ERROR_OK)
670 goto done;
671
672 LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
673
674 ttbcr_n = ttbcr & 0x7;
675 armv8->armv8_mmu.ttbcr = ttbcr;
676
677 /*
678 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
679 * document # ARM DDI 0406C
680 */
681 armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
682 armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
683 armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
684 armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
685
686 LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
687 (ttbcr_n != 0) ? "used" : "not used",
688 armv8->armv8_mmu.ttbr_mask[0],
689 armv8->armv8_mmu.ttbr_mask[1]);
690
691 done:
692 dpm->finish(dpm);
693 return retval;
694 }
695
696 static __unused int armv8_read_ttbcr(struct target *target)
697 {
698 struct armv8_common *armv8 = target_to_armv8(target);
699 struct arm_dpm *dpm = armv8->arm.dpm;
700 struct arm *arm = &armv8->arm;
701 uint32_t ttbcr;
702 uint64_t ttbcr_64;
703
704 int retval = dpm->prepare(dpm);
705 if (retval != ERROR_OK)
706 goto done;
707
708 /* claaer ttrr1_used and ttbr0_mask */
709 memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
710 memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
711
712 switch (armv8_curel_from_core_mode(arm->core_mode)) {
713 case SYSTEM_CUREL_EL3:
714 retval = dpm->instr_read_data_r0(dpm,
715 ARMV8_MRS(SYSTEM_TCR_EL3, 0),
716 &ttbcr);
717 retval += dpm->instr_read_data_r0_64(dpm,
718 ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
719 &armv8->ttbr_base);
720 if (retval != ERROR_OK)
721 goto done;
722 armv8->va_size = 64 - (ttbcr & 0x3F);
723 armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
724 armv8->page_size = (ttbcr >> 14) & 3;
725 break;
726 case SYSTEM_CUREL_EL2:
727 retval = dpm->instr_read_data_r0(dpm,
728 ARMV8_MRS(SYSTEM_TCR_EL2, 0),
729 &ttbcr);
730 retval += dpm->instr_read_data_r0_64(dpm,
731 ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
732 &armv8->ttbr_base);
733 if (retval != ERROR_OK)
734 goto done;
735 armv8->va_size = 64 - (ttbcr & 0x3F);
736 armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
737 armv8->page_size = (ttbcr >> 14) & 3;
738 break;
739 case SYSTEM_CUREL_EL0:
740 armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
741 /* fall through */
742 case SYSTEM_CUREL_EL1:
743 retval = dpm->instr_read_data_r0_64(dpm,
744 ARMV8_MRS(SYSTEM_TCR_EL1, 0),
745 &ttbcr_64);
746 armv8->va_size = 64 - (ttbcr_64 & 0x3F);
747 armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
748 armv8->page_size = (ttbcr_64 >> 14) & 3;
749 armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
750 armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF;
751 retval += dpm->instr_read_data_r0_64(dpm,
752 ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
753 &armv8->ttbr_base);
754 if (retval != ERROR_OK)
755 goto done;
756 break;
757 default:
758 LOG_ERROR("unknow core state");
759 retval = ERROR_FAIL;
760 break;
761 }
762 if (retval != ERROR_OK)
763 goto done;
764
765 if (armv8->armv8_mmu.ttbr1_used == 1)
766 LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
767
768 done:
769 armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
770 dpm->finish(dpm);
771 return retval;
772 }
773
774 /* method adapted to cortex A : reused arm v4 v5 method*/
775 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
776 {
777 return ERROR_OK;
778 }
779
780 /* V8 method VA TO PA */
781 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
782 target_addr_t *val, int meminfo)
783 {
784 struct armv8_common *armv8 = target_to_armv8(target);
785 struct arm *arm = target_to_arm(target);
786 struct arm_dpm *dpm = &armv8->dpm;
787 enum arm_mode target_mode = ARM_MODE_ANY;
788 uint32_t retval;
789 uint32_t instr = 0;
790 uint64_t par;
791
792 static const char * const shared_name[] = {
793 "Non-", "UNDEFINED ", "Outer ", "Inner "
794 };
795
796 static const char * const secure_name[] = {
797 "Secure", "Not Secure"
798 };
799
800 retval = dpm->prepare(dpm);
801 if (retval != ERROR_OK)
802 return retval;
803
804 switch (armv8_curel_from_core_mode(arm->core_mode)) {
805 case SYSTEM_CUREL_EL0:
806 instr = ARMV8_SYS(SYSTEM_ATS12E0R, 0);
807 /* can only execute instruction at EL2 */
808 target_mode = ARMV8_64_EL2H;
809 break;
810 case SYSTEM_CUREL_EL1:
811 instr = ARMV8_SYS(SYSTEM_ATS12E1R, 0);
812 /* can only execute instruction at EL2 */
813 target_mode = ARMV8_64_EL2H;
814 break;
815 case SYSTEM_CUREL_EL2:
816 instr = ARMV8_SYS(SYSTEM_ATS1E2R, 0);
817 break;
818 case SYSTEM_CUREL_EL3:
819 instr = ARMV8_SYS(SYSTEM_ATS1E3R, 0);
820 break;
821
822 default:
823 break;
824 };
825
826 if (target_mode != ARM_MODE_ANY)
827 armv8_dpm_modeswitch(dpm, target_mode);
828
829 /* write VA to R0 and execute translation instruction */
830 retval = dpm->instr_write_data_r0_64(dpm, instr, (uint64_t)va);
831 /* read result from PAR_EL1 */
832 if (retval == ERROR_OK)
833 retval = dpm->instr_read_data_r0_64(dpm, ARMV8_MRS(SYSTEM_PAR_EL1, 0), &par);
834
835 /* switch back to saved PE mode */
836 if (target_mode != ARM_MODE_ANY)
837 armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
838
839 dpm->finish(dpm);
840
841 if (retval != ERROR_OK)
842 return retval;
843
844 if (retval != ERROR_OK)
845 return retval;
846
847 if (par & 1) {
848 LOG_ERROR("Address translation failed at stage %i, FST=%x, PTW=%i",
849 ((int)(par >> 9) & 1)+1, (int)(par >> 1) & 0x3f, (int)(par >> 8) & 1);
850
851 *val = 0;
852 retval = ERROR_FAIL;
853 } else {
854 *val = (par & 0xFFFFFFFFF000UL) | (va & 0xFFF);
855 if (meminfo) {
856 int SH = (par >> 7) & 3;
857 int NS = (par >> 9) & 1;
858 int ATTR = (par >> 56) & 0xFF;
859
860 char *memtype = (ATTR & 0xF0) == 0 ? "Device Memory" : "Normal Memory";
861
862 LOG_USER("%sshareable, %s",
863 shared_name[SH], secure_name[NS]);
864 LOG_USER("%s", memtype);
865 }
866 }
867
868 return retval;
869 }
870
871 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
872 struct armv8_cache_common *armv8_cache)
873 {
874 if (armv8_cache->info == -1) {
875 command_print(cmd_ctx, "cache not yet identified");
876 return ERROR_OK;
877 }
878
879 if (armv8_cache->display_cache_info)
880 armv8_cache->display_cache_info(cmd_ctx, armv8_cache);
881 return ERROR_OK;
882 }
883
884 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
885 {
886 struct arm *arm = &armv8->arm;
887 arm->arch_info = armv8;
888 target->arch_info = &armv8->arm;
889 /* target is useful in all function arm v4 5 compatible */
890 armv8->arm.target = target;
891 armv8->arm.common_magic = ARM_COMMON_MAGIC;
892 armv8->common_magic = ARMV8_COMMON_MAGIC;
893
894 armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
895 armv8->armv8_mmu.armv8_cache.info = -1;
896 armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
897 armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
898 return ERROR_OK;
899 }
900
901 int armv8_aarch64_state(struct target *target)
902 {
903 struct arm *arm = target_to_arm(target);
904
905 if (arm->common_magic != ARM_COMMON_MAGIC) {
906 LOG_ERROR("BUG: called for a non-ARM target");
907 return ERROR_FAIL;
908 }
909
910 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
911 "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
912 armv8_state_strings[arm->core_state],
913 debug_reason_name(target),
914 armv8_mode_name(arm->core_mode),
915 buf_get_u32(arm->cpsr->value, 0, 32),
916 buf_get_u64(arm->pc->value, 0, 64),
917 arm->is_semihosting ? ", semihosting" : "");
918
919 return ERROR_OK;
920 }
921
922 int armv8_arch_state(struct target *target)
923 {
924 static const char * const state[] = {
925 "disabled", "enabled"
926 };
927
928 struct armv8_common *armv8 = target_to_armv8(target);
929 struct arm *arm = &armv8->arm;
930
931 if (armv8->common_magic != ARMV8_COMMON_MAGIC) {
932 LOG_ERROR("BUG: called for a non-Armv8 target");
933 return ERROR_COMMAND_SYNTAX_ERROR;
934 }
935
936 if (arm->core_state == ARM_STATE_AARCH64)
937 armv8_aarch64_state(target);
938 else
939 arm_arch_state(target);
940
941 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
942 state[armv8->armv8_mmu.mmu_enabled],
943 state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
944 state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
945
946 if (arm->core_mode == ARM_MODE_ABT)
947 armv8_show_fault_registers(target);
948
949 if (target->debug_reason == DBG_REASON_WATCHPOINT)
950 LOG_USER("Watchpoint triggered at PC %#08x",
951 (unsigned) armv8->dpm.wp_pc);
952
953 return ERROR_OK;
954 }
955
956 static const struct {
957 unsigned id;
958 const char *name;
959 unsigned bits;
960 enum arm_mode mode;
961 enum reg_type type;
962 const char *group;
963 const char *feature;
964 } armv8_regs[] = {
965 { ARMV8_R0, "x0", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
966 { ARMV8_R1, "x1", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
967 { ARMV8_R2, "x2", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
968 { ARMV8_R3, "x3", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
969 { ARMV8_R4, "x4", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
970 { ARMV8_R5, "x5", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
971 { ARMV8_R6, "x6", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
972 { ARMV8_R7, "x7", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
973 { ARMV8_R8, "x8", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
974 { ARMV8_R9, "x9", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
975 { ARMV8_R10, "x10", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
976 { ARMV8_R11, "x11", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
977 { ARMV8_R12, "x12", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
978 { ARMV8_R13, "x13", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
979 { ARMV8_R14, "x14", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
980 { ARMV8_R15, "x15", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
981 { ARMV8_R16, "x16", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
982 { ARMV8_R17, "x17", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
983 { ARMV8_R18, "x18", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
984 { ARMV8_R19, "x19", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
985 { ARMV8_R20, "x20", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
986 { ARMV8_R21, "x21", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
987 { ARMV8_R22, "x22", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
988 { ARMV8_R23, "x23", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
989 { ARMV8_R24, "x24", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
990 { ARMV8_R25, "x25", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
991 { ARMV8_R26, "x26", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
992 { ARMV8_R27, "x27", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
993 { ARMV8_R28, "x28", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
994 { ARMV8_R29, "x29", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
995 { ARMV8_R30, "x30", 64, ARM_MODE_ANY, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
996
997 { ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
998 { ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
999
1000 { ARMV8_xPSR, "CPSR", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.aarch64.core" },
1001
1002 { ARMV8_ELR_EL1, "ELR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked" },
1003 { ARMV8_ESR_EL1, "ESR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
1004 { ARMV8_SPSR_EL1, "SPSR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
1005
1006 { ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked" },
1007 { ARMV8_ESR_EL2, "ESR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
1008 { ARMV8_SPSR_EL2, "SPSR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
1009
1010 { ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked" },
1011 { ARMV8_ESR_EL3, "ESR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
1012 { ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
1013 };
1014
1015 static const struct {
1016 unsigned id;
1017 const char *name;
1018 unsigned bits;
1019 enum arm_mode mode;
1020 enum reg_type type;
1021 const char *group;
1022 const char *feature;
1023 } armv8_regs32[] = {
1024 { ARMV8_R0, "r0", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1025 { ARMV8_R1, "r1", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1026 { ARMV8_R2, "r2", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1027 { ARMV8_R3, "r3", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1028 { ARMV8_R4, "r4", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1029 { ARMV8_R5, "r5", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1030 { ARMV8_R6, "r6", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1031 { ARMV8_R7, "r7", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1032 { ARMV8_R8, "r8", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1033 { ARMV8_R9, "r9", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1034 { ARMV8_R10, "r10", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1035 { ARMV8_R11, "r11", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1036 { ARMV8_R12, "r12", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1037 { ARMV8_R13, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
1038 { ARMV8_R14, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
1039 { ARMV8_PC, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
1040 { ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
1041 };
1042
1043 #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
1044 #define ARMV8_NUM_REGS32 ARRAY_SIZE(armv8_regs32)
1045
1046 static int armv8_get_core_reg(struct reg *reg)
1047 {
1048 struct arm_reg *armv8_reg = reg->arch_info;
1049 struct target *target = armv8_reg->target;
1050 struct arm *arm = target_to_arm(target);
1051
1052 if (target->state != TARGET_HALTED)
1053 return ERROR_TARGET_NOT_HALTED;
1054
1055 return arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
1056 }
1057
1058 static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
1059 {
1060 struct arm_reg *armv8_reg = reg->arch_info;
1061 struct target *target = armv8_reg->target;
1062 struct arm *arm = target_to_arm(target);
1063 uint64_t value = buf_get_u64(buf, 0, 64);
1064
1065 if (target->state != TARGET_HALTED)
1066 return ERROR_TARGET_NOT_HALTED;
1067
1068 if (reg == arm->cpsr) {
1069 armv8_set_cpsr(arm, (uint32_t)value);
1070 } else {
1071 buf_set_u64(reg->value, 0, 64, value);
1072 reg->valid = 1;
1073 }
1074
1075 reg->dirty = 1;
1076
1077 return ERROR_OK;
1078 }
1079
1080 static const struct reg_arch_type armv8_reg_type = {
1081 .get = armv8_get_core_reg,
1082 .set = armv8_set_core_reg,
1083 };
1084
1085 static int armv8_get_core_reg32(struct reg *reg)
1086 {
1087 struct arm_reg *armv8_reg = reg->arch_info;
1088 struct target *target = armv8_reg->target;
1089 struct arm *arm = target_to_arm(target);
1090 struct reg_cache *cache = arm->core_cache;
1091 struct reg *reg64;
1092 int retval;
1093
1094 LOG_DEBUG("reg.name:%s number:%i arm.num:%i value:0x%08" PRIx64,
1095 reg->name, reg->number, armv8_reg->num, buf_get_u64(reg->value, 0, 32));
1096
1097 /* get the corresponding Aarch64 register */
1098 reg64 = cache->reg_list + armv8_reg->num;
1099 if (reg64->valid) {
1100 reg->valid = true;
1101 return ERROR_OK;
1102 }
1103
1104 retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
1105 if (retval == ERROR_OK)
1106 reg->valid = reg64->valid;
1107
1108 return retval;
1109 }
1110
1111 static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
1112 {
1113 struct arm_reg *armv8_reg = reg->arch_info;
1114 struct target *target = armv8_reg->target;
1115 struct arm *arm = target_to_arm(target);
1116 struct reg_cache *cache = arm->core_cache;
1117 struct reg *reg64 = cache->reg_list + armv8_reg->num;
1118 uint32_t value = buf_get_u32(buf, 0, 32);
1119
1120 if (target->state != TARGET_HALTED)
1121 return ERROR_TARGET_NOT_HALTED;
1122
1123 if (reg64 == arm->cpsr) {
1124 armv8_set_cpsr(arm, value);
1125 } else {
1126 buf_set_u32(reg->value, 0, 32, value);
1127 reg->valid = 1;
1128 reg64->valid = 1;
1129 }
1130
1131 reg64->dirty = 1;
1132
1133 return ERROR_OK;
1134 }
1135
1136 static const struct reg_arch_type armv8_reg32_type = {
1137 .get = armv8_get_core_reg32,
1138 .set = armv8_set_core_reg32,
1139 };
1140
1141 /** Builds cache of architecturally defined registers. */
1142 struct reg_cache *armv8_build_reg_cache(struct target *target)
1143 {
1144 struct armv8_common *armv8 = target_to_armv8(target);
1145 struct arm *arm = &armv8->arm;
1146 int num_regs = ARMV8_NUM_REGS;
1147 int num_regs32 = ARMV8_NUM_REGS32;
1148 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1149 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
1150 struct reg_cache *cache32 = malloc(sizeof(struct reg_cache));
1151 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
1152 struct reg *reg_list32 = calloc(num_regs32, sizeof(struct reg));
1153 struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
1154 struct reg_feature *feature;
1155 int i;
1156
1157 /* Build the process context cache */
1158 cache->name = "Aarch64 registers";
1159 cache->next = cache32;
1160 cache->reg_list = reg_list;
1161 cache->num_regs = num_regs;
1162
1163 for (i = 0; i < num_regs; i++) {
1164 arch_info[i].num = armv8_regs[i].id;
1165 arch_info[i].mode = armv8_regs[i].mode;
1166 arch_info[i].target = target;
1167 arch_info[i].arm = arm;
1168
1169 reg_list[i].name = armv8_regs[i].name;
1170 reg_list[i].size = armv8_regs[i].bits;
1171 reg_list[i].value = calloc(1, 8);
1172 reg_list[i].type = &armv8_reg_type;
1173 reg_list[i].arch_info = &arch_info[i];
1174
1175 reg_list[i].group = armv8_regs[i].group;
1176 reg_list[i].number = i;
1177 reg_list[i].exist = true;
1178 reg_list[i].caller_save = true; /* gdb defaults to true */
1179
1180 feature = calloc(1, sizeof(struct reg_feature));
1181 if (feature) {
1182 feature->name = armv8_regs[i].feature;
1183 reg_list[i].feature = feature;
1184 } else
1185 LOG_ERROR("unable to allocate feature list");
1186
1187 reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
1188 if (reg_list[i].reg_data_type)
1189 reg_list[i].reg_data_type->type = armv8_regs[i].type;
1190 else
1191 LOG_ERROR("unable to allocate reg type list");
1192 }
1193
1194 arm->cpsr = reg_list + ARMV8_xPSR;
1195 arm->pc = reg_list + ARMV8_PC;
1196 arm->core_cache = cache;
1197
1198 /* shadow cache for ARM mode registers */
1199 cache32->name = "Aarch32 registers";
1200 cache32->next = NULL;
1201 cache32->reg_list = reg_list32;
1202 cache32->num_regs = num_regs32;
1203
1204 for (i = 0; i < num_regs32; i++) {
1205 reg_list32[i].name = armv8_regs32[i].name;
1206 reg_list32[i].size = armv8_regs32[i].bits;
1207 reg_list32[i].value = &arch_info[armv8_regs32[i].id].value[0];
1208 reg_list32[i].type = &armv8_reg32_type;
1209 reg_list32[i].arch_info = &arch_info[armv8_regs32[i].id];
1210 reg_list32[i].group = armv8_regs32[i].group;
1211 reg_list32[i].number = i;
1212 reg_list32[i].exist = true;
1213 reg_list32[i].caller_save = true;
1214
1215 feature = calloc(1, sizeof(struct reg_feature));
1216 if (feature) {
1217 feature->name = armv8_regs32[i].feature;
1218 reg_list32[i].feature = feature;
1219 } else
1220 LOG_ERROR("unable to allocate feature list");
1221
1222 reg_list32[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
1223 if (reg_list32[i].reg_data_type)
1224 reg_list32[i].reg_data_type->type = armv8_regs32[i].type;
1225 else
1226 LOG_ERROR("unable to allocate reg type list");
1227 }
1228
1229 (*cache_p) = cache;
1230 return cache;
1231 }
1232
1233 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum)
1234 {
1235 struct reg *r;
1236
1237 if (regnum > (ARMV8_LAST_REG - 1))
1238 return NULL;
1239
1240 r = arm->core_cache->reg_list + regnum;
1241 return r;
1242 }
1243
1244 const struct command_registration armv8_command_handlers[] = {
1245 {
1246 .chain = dap_command_handlers,
1247 },
1248 COMMAND_REGISTRATION_DONE
1249 };
1250
1251
1252 int armv8_get_gdb_reg_list(struct target *target,
1253 struct reg **reg_list[], int *reg_list_size,
1254 enum target_register_class reg_class)
1255 {
1256 struct arm *arm = target_to_arm(target);
1257 int i;
1258
1259 if (arm->core_state == ARM_STATE_AARCH64) {
1260
1261 LOG_DEBUG("Creating Aarch64 register list");
1262
1263 switch (reg_class) {
1264 case REG_CLASS_GENERAL:
1265 *reg_list_size = ARMV8_ELR_EL1;
1266 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1267
1268 for (i = 0; i < *reg_list_size; i++)
1269 (*reg_list)[i] = armv8_reg_current(arm, i);
1270 return ERROR_OK;
1271
1272 case REG_CLASS_ALL:
1273 *reg_list_size = ARMV8_LAST_REG;
1274 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1275
1276 for (i = 0; i < *reg_list_size; i++)
1277 (*reg_list)[i] = armv8_reg_current(arm, i);
1278
1279 return ERROR_OK;
1280
1281 default:
1282 LOG_ERROR("not a valid register class type in query.");
1283 return ERROR_FAIL;
1284 }
1285 } else {
1286 struct reg_cache *cache32 = arm->core_cache->next;
1287
1288 LOG_DEBUG("Creating Aarch32 register list");
1289
1290 switch (reg_class) {
1291 case REG_CLASS_GENERAL:
1292 case REG_CLASS_ALL:
1293 *reg_list_size = cache32->num_regs;
1294 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1295
1296 for (i = 0; i < *reg_list_size; i++)
1297 (*reg_list)[i] = cache32->reg_list + i;
1298
1299 return ERROR_OK;
1300 default:
1301 LOG_ERROR("not a valid register class type in query.");
1302 return ERROR_FAIL;
1303 }
1304 }
1305 }
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