1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex-R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
39 * Cortex-A8(tm) TRM, ARM DDI 0344H *
40 * Cortex-A9(tm) TRM, ARM DDI 0407F *
41 * Cortex-A4(tm) TRM, ARM DDI 0363E *
42 * Cortex-A15(tm)TRM, ARM DDI 0438C *
44 ***************************************************************************/
50 #include "breakpoints.h"
53 #include "target_request.h"
54 #include "target_type.h"
55 #include "arm_opcodes.h"
56 #include "arm_semihosting.h"
57 #include "transport/transport.h"
58 #include <helper/time_support.h>
60 #define foreach_smp_target(pos, head) \
61 for (pos = head; (pos != NULL); pos = pos->next)
63 static int cortex_a_poll(struct target
*target
);
64 static int cortex_a_debug_entry(struct target
*target
);
65 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
66 static int cortex_a_set_breakpoint(struct target
*target
,
67 struct breakpoint
*breakpoint
, uint8_t matchmode
);
68 static int cortex_a_set_context_breakpoint(struct target
*target
,
69 struct breakpoint
*breakpoint
, uint8_t matchmode
);
70 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
71 struct breakpoint
*breakpoint
);
72 static int cortex_a_unset_breakpoint(struct target
*target
,
73 struct breakpoint
*breakpoint
);
74 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
75 uint32_t *value
, int regnum
);
76 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
77 uint32_t value
, int regnum
);
78 static int cortex_a_mmu(struct target
*target
, int *enabled
);
79 static int cortex_a_mmu_modify(struct target
*target
, int enable
);
80 static int cortex_a_virt2phys(struct target
*target
,
81 target_addr_t virt
, target_addr_t
*phys
);
82 static int cortex_a_read_cpu_memory(struct target
*target
,
83 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
86 /* restore cp15_control_reg at resume */
87 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
89 int retval
= ERROR_OK
;
90 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
91 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
93 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
94 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
95 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
96 retval
= armv7a
->arm
.mcr(target
, 15,
99 cortex_a
->cp15_control_reg
);
105 * Set up ARM core for memory access.
106 * If !phys_access, switch to SVC mode and make sure MMU is on
107 * If phys_access, switch off mmu
109 static int cortex_a_prep_memaccess(struct target
*target
, int phys_access
)
111 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
112 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
115 if (phys_access
== 0) {
116 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
117 cortex_a_mmu(target
, &mmu_enabled
);
119 cortex_a_mmu_modify(target
, 1);
120 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
121 /* overwrite DACR to all-manager */
122 armv7a
->arm
.mcr(target
, 15,
127 cortex_a_mmu(target
, &mmu_enabled
);
129 cortex_a_mmu_modify(target
, 0);
135 * Restore ARM core after memory access.
136 * If !phys_access, switch to previous mode
137 * If phys_access, restore MMU setting
139 static int cortex_a_post_memaccess(struct target
*target
, int phys_access
)
141 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
142 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
144 if (phys_access
== 0) {
145 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
147 armv7a
->arm
.mcr(target
, 15,
149 cortex_a
->cp15_dacr_reg
);
151 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
154 cortex_a_mmu(target
, &mmu_enabled
);
156 cortex_a_mmu_modify(target
, 1);
162 /* modify cp15_control_reg in order to enable or disable mmu for :
163 * - virt2phys address conversion
164 * - read or write memory in phys or virt address */
165 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
167 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
168 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
169 int retval
= ERROR_OK
;
173 /* if mmu enabled at target stop and mmu not enable */
174 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
175 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
178 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0) {
179 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
183 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0x1U
) {
184 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
190 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32
,
191 enable
? "enable mmu" : "disable mmu",
192 cortex_a
->cp15_control_reg_curr
);
194 retval
= armv7a
->arm
.mcr(target
, 15,
197 cortex_a
->cp15_control_reg_curr
);
203 * Cortex-A Basic debug access, very low level assumes state is saved
205 static int cortex_a_init_debug_access(struct target
*target
)
207 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
210 /* lock memory-mapped access to debug registers to prevent
211 * software interference */
212 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
213 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0);
214 if (retval
!= ERROR_OK
)
217 /* Disable cacheline fills and force cache write-through in debug state */
218 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
219 armv7a
->debug_base
+ CPUDBG_DSCCR
, 0);
220 if (retval
!= ERROR_OK
)
223 /* Disable TLB lookup and refill/eviction in debug state */
224 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
225 armv7a
->debug_base
+ CPUDBG_DSMCR
, 0);
226 if (retval
!= ERROR_OK
)
229 retval
= dap_run(armv7a
->debug_ap
->dap
);
230 if (retval
!= ERROR_OK
)
233 /* Enabling of instruction execution in debug mode is done in debug_entry code */
235 /* Resync breakpoint registers */
237 /* Since this is likely called from init or reset, update target state information*/
238 return cortex_a_poll(target
);
241 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
243 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
244 * Writes final value of DSCR into *dscr. Pass force to force always
245 * reading DSCR at least once. */
246 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
247 int64_t then
= timeval_ms();
248 while ((*dscr
& DSCR_INSTR_COMP
) == 0 || force
) {
250 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
251 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
252 if (retval
!= ERROR_OK
) {
253 LOG_ERROR("Could not read DSCR register");
256 if (timeval_ms() > then
+ 1000) {
257 LOG_ERROR("Timeout waiting for InstrCompl=1");
264 /* To reduce needless round-trips, pass in a pointer to the current
265 * DSCR value. Initialize it to zero if you just need to know the
266 * value on return from this function; or DSCR_INSTR_COMP if you
267 * happen to know that no instruction is pending.
269 static int cortex_a_exec_opcode(struct target
*target
,
270 uint32_t opcode
, uint32_t *dscr_p
)
274 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
276 dscr
= dscr_p
? *dscr_p
: 0;
278 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
280 /* Wait for InstrCompl bit to be set */
281 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
282 if (retval
!= ERROR_OK
)
285 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
286 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
287 if (retval
!= ERROR_OK
)
290 int64_t then
= timeval_ms();
292 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
293 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
294 if (retval
!= ERROR_OK
) {
295 LOG_ERROR("Could not read DSCR register");
298 if (timeval_ms() > then
+ 1000) {
299 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
302 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
310 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
311 uint32_t *value
, int regnum
)
313 int retval
= ERROR_OK
;
314 uint8_t reg
= regnum
&0xFF;
316 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
322 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
323 retval
= cortex_a_exec_opcode(target
,
324 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
326 if (retval
!= ERROR_OK
)
328 } else if (reg
== 15) {
329 /* "MOV r0, r15"; then move r0 to DCCTX */
330 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
331 if (retval
!= ERROR_OK
)
333 retval
= cortex_a_exec_opcode(target
,
334 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
336 if (retval
!= ERROR_OK
)
339 /* "MRS r0, CPSR" or "MRS r0, SPSR"
340 * then move r0 to DCCTX
342 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
343 if (retval
!= ERROR_OK
)
345 retval
= cortex_a_exec_opcode(target
,
346 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
348 if (retval
!= ERROR_OK
)
352 /* Wait for DTRRXfull then read DTRRTX */
353 int64_t then
= timeval_ms();
354 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
355 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
356 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
357 if (retval
!= ERROR_OK
)
359 if (timeval_ms() > then
+ 1000) {
360 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
365 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
366 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
367 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
372 __attribute__((unused
))
373 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
374 uint32_t value
, int regnum
)
376 int retval
= ERROR_OK
;
377 uint8_t Rd
= regnum
&0xFF;
379 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
381 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
383 /* Check that DCCRX is not full */
384 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
385 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
386 if (retval
!= ERROR_OK
)
388 if (dscr
& DSCR_DTR_RX_FULL
) {
389 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
390 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
391 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
393 if (retval
!= ERROR_OK
)
400 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
401 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
402 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
403 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
404 if (retval
!= ERROR_OK
)
408 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
409 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
412 if (retval
!= ERROR_OK
)
414 } else if (Rd
== 15) {
415 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
418 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
420 if (retval
!= ERROR_OK
)
422 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
423 if (retval
!= ERROR_OK
)
426 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
427 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
429 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
431 if (retval
!= ERROR_OK
)
433 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
435 if (retval
!= ERROR_OK
)
438 /* "Prefetch flush" after modifying execution status in CPSR */
440 retval
= cortex_a_exec_opcode(target
,
441 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
443 if (retval
!= ERROR_OK
)
451 /* Write to memory mapped registers directly with no cache or mmu handling */
452 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
457 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
459 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
, address
, value
);
465 * Cortex-A implementation of Debug Programmer's Model
467 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
468 * so there's no need to poll for it before executing an instruction.
470 * NOTE that in several of these cases the "stall" mode might be useful.
471 * It'd let us queue a few operations together... prepare/finish might
472 * be the places to enable/disable that mode.
475 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
477 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
480 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
482 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
483 return mem_ap_write_u32(a
->armv7a_common
.debug_ap
,
484 a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
487 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
490 uint32_t dscr
= DSCR_INSTR_COMP
;
496 /* Wait for DTRRXfull */
497 int64_t then
= timeval_ms();
498 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
499 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
500 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
502 if (retval
!= ERROR_OK
)
504 if (timeval_ms() > then
+ 1000) {
505 LOG_ERROR("Timeout waiting for read dcc");
510 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
511 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
512 if (retval
!= ERROR_OK
)
514 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
522 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
524 struct cortex_a_common
*a
= dpm_to_a(dpm
);
528 /* set up invariant: INSTR_COMP is set after ever DPM operation */
529 int64_t then
= timeval_ms();
531 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
532 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
534 if (retval
!= ERROR_OK
)
536 if ((dscr
& DSCR_INSTR_COMP
) != 0)
538 if (timeval_ms() > then
+ 1000) {
539 LOG_ERROR("Timeout waiting for dpm prepare");
544 /* this "should never happen" ... */
545 if (dscr
& DSCR_DTR_RX_FULL
) {
546 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
548 retval
= cortex_a_exec_opcode(
549 a
->armv7a_common
.arm
.target
,
550 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
552 if (retval
!= ERROR_OK
)
559 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
561 /* REVISIT what could be done here? */
565 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
566 uint32_t opcode
, uint32_t data
)
568 struct cortex_a_common
*a
= dpm_to_a(dpm
);
570 uint32_t dscr
= DSCR_INSTR_COMP
;
572 retval
= cortex_a_write_dcc(a
, data
);
573 if (retval
!= ERROR_OK
)
576 return cortex_a_exec_opcode(
577 a
->armv7a_common
.arm
.target
,
582 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
583 uint32_t opcode
, uint32_t data
)
585 struct cortex_a_common
*a
= dpm_to_a(dpm
);
586 uint32_t dscr
= DSCR_INSTR_COMP
;
589 retval
= cortex_a_write_dcc(a
, data
);
590 if (retval
!= ERROR_OK
)
593 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
594 retval
= cortex_a_exec_opcode(
595 a
->armv7a_common
.arm
.target
,
596 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
598 if (retval
!= ERROR_OK
)
601 /* then the opcode, taking data from R0 */
602 retval
= cortex_a_exec_opcode(
603 a
->armv7a_common
.arm
.target
,
610 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
612 struct target
*target
= dpm
->arm
->target
;
613 uint32_t dscr
= DSCR_INSTR_COMP
;
615 /* "Prefetch flush" after modifying execution status in CPSR */
616 return cortex_a_exec_opcode(target
,
617 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
621 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
622 uint32_t opcode
, uint32_t *data
)
624 struct cortex_a_common
*a
= dpm_to_a(dpm
);
626 uint32_t dscr
= DSCR_INSTR_COMP
;
628 /* the opcode, writing data to DCC */
629 retval
= cortex_a_exec_opcode(
630 a
->armv7a_common
.arm
.target
,
633 if (retval
!= ERROR_OK
)
636 return cortex_a_read_dcc(a
, data
, &dscr
);
640 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
641 uint32_t opcode
, uint32_t *data
)
643 struct cortex_a_common
*a
= dpm_to_a(dpm
);
644 uint32_t dscr
= DSCR_INSTR_COMP
;
647 /* the opcode, writing data to R0 */
648 retval
= cortex_a_exec_opcode(
649 a
->armv7a_common
.arm
.target
,
652 if (retval
!= ERROR_OK
)
655 /* write R0 to DCC */
656 retval
= cortex_a_exec_opcode(
657 a
->armv7a_common
.arm
.target
,
658 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
660 if (retval
!= ERROR_OK
)
663 return cortex_a_read_dcc(a
, data
, &dscr
);
666 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
667 uint32_t addr
, uint32_t control
)
669 struct cortex_a_common
*a
= dpm_to_a(dpm
);
670 uint32_t vr
= a
->armv7a_common
.debug_base
;
671 uint32_t cr
= a
->armv7a_common
.debug_base
;
675 case 0 ... 15: /* breakpoints */
676 vr
+= CPUDBG_BVR_BASE
;
677 cr
+= CPUDBG_BCR_BASE
;
679 case 16 ... 31: /* watchpoints */
680 vr
+= CPUDBG_WVR_BASE
;
681 cr
+= CPUDBG_WCR_BASE
;
690 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
691 (unsigned) vr
, (unsigned) cr
);
693 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
695 if (retval
!= ERROR_OK
)
697 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
702 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
704 struct cortex_a_common
*a
= dpm_to_a(dpm
);
709 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
712 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
720 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
722 /* clear control register */
723 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
726 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
728 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
731 dpm
->arm
= &a
->armv7a_common
.arm
;
734 dpm
->prepare
= cortex_a_dpm_prepare
;
735 dpm
->finish
= cortex_a_dpm_finish
;
737 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
738 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
739 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
741 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
742 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
744 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
745 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
747 retval
= arm_dpm_setup(dpm
);
748 if (retval
== ERROR_OK
)
749 retval
= arm_dpm_initialize(dpm
);
753 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
755 struct target_list
*head
;
759 while (head
!= (struct target_list
*)NULL
) {
761 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
767 static int cortex_a_halt(struct target
*target
);
769 static int cortex_a_halt_smp(struct target
*target
)
772 struct target_list
*head
;
775 while (head
!= (struct target_list
*)NULL
) {
777 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
)
778 && target_was_examined(curr
))
779 retval
+= cortex_a_halt(curr
);
785 static int update_halt_gdb(struct target
*target
)
787 struct target
*gdb_target
= NULL
;
788 struct target_list
*head
;
792 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
793 target
->gdb_service
->target
= target
;
794 target
->gdb_service
->core
[0] = target
->coreid
;
795 retval
+= cortex_a_halt_smp(target
);
798 if (target
->gdb_service
)
799 gdb_target
= target
->gdb_service
->target
;
801 foreach_smp_target(head
, target
->head
) {
803 /* skip calling context */
806 if (!target_was_examined(curr
))
808 /* skip targets that were already halted */
809 if (curr
->state
== TARGET_HALTED
)
811 /* Skip gdb_target; it alerts GDB so has to be polled as last one */
812 if (curr
== gdb_target
)
815 /* avoid recursion in cortex_a_poll() */
821 /* after all targets were updated, poll the gdb serving target */
822 if (gdb_target
!= NULL
&& gdb_target
!= target
)
823 cortex_a_poll(gdb_target
);
828 * Cortex-A Run control
831 static int cortex_a_poll(struct target
*target
)
833 int retval
= ERROR_OK
;
835 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
836 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
837 enum target_state prev_target_state
= target
->state
;
838 /* toggle to another core is done by gdb as follow */
839 /* maint packet J core_id */
841 /* the next polling trigger an halt event sent to gdb */
842 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
843 (target
->gdb_service
) &&
844 (target
->gdb_service
->target
== NULL
)) {
845 target
->gdb_service
->target
=
846 get_cortex_a(target
, target
->gdb_service
->core
[1]);
847 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
850 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
851 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
852 if (retval
!= ERROR_OK
)
854 cortex_a
->cpudbg_dscr
= dscr
;
856 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
857 if (prev_target_state
!= TARGET_HALTED
) {
858 /* We have a halting debug event */
859 LOG_DEBUG("Target halted");
860 target
->state
= TARGET_HALTED
;
861 if ((prev_target_state
== TARGET_RUNNING
)
862 || (prev_target_state
== TARGET_UNKNOWN
)
863 || (prev_target_state
== TARGET_RESET
)) {
864 retval
= cortex_a_debug_entry(target
);
865 if (retval
!= ERROR_OK
)
868 retval
= update_halt_gdb(target
);
869 if (retval
!= ERROR_OK
)
873 if (arm_semihosting(target
, &retval
) != 0)
876 target_call_event_callbacks(target
,
877 TARGET_EVENT_HALTED
);
879 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
882 retval
= cortex_a_debug_entry(target
);
883 if (retval
!= ERROR_OK
)
886 retval
= update_halt_gdb(target
);
887 if (retval
!= ERROR_OK
)
891 target_call_event_callbacks(target
,
892 TARGET_EVENT_DEBUG_HALTED
);
896 target
->state
= TARGET_RUNNING
;
901 static int cortex_a_halt(struct target
*target
)
903 int retval
= ERROR_OK
;
905 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
908 * Tell the core to be halted by writing DRCR with 0x1
909 * and then wait for the core to be halted.
911 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
912 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
913 if (retval
!= ERROR_OK
)
917 * enter halting debug mode
919 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
920 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
921 if (retval
!= ERROR_OK
)
924 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
925 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
926 if (retval
!= ERROR_OK
)
929 int64_t then
= timeval_ms();
931 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
932 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
933 if (retval
!= ERROR_OK
)
935 if ((dscr
& DSCR_CORE_HALTED
) != 0)
937 if (timeval_ms() > then
+ 1000) {
938 LOG_ERROR("Timeout waiting for halt");
943 target
->debug_reason
= DBG_REASON_DBGRQ
;
948 static int cortex_a_internal_restore(struct target
*target
, int current
,
949 target_addr_t
*address
, int handle_breakpoints
, int debug_execution
)
951 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
952 struct arm
*arm
= &armv7a
->arm
;
956 if (!debug_execution
)
957 target_free_all_working_areas(target
);
960 if (debug_execution
) {
961 /* Disable interrupts */
962 /* We disable interrupts in the PRIMASK register instead of
963 * masking with C_MASKINTS,
964 * This is probably the same issue as Cortex-M3 Errata 377493:
965 * C_MASKINTS in parallel with disabled interrupts can cause
966 * local faults to not be taken. */
967 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
968 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
969 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
971 /* Make sure we are in Thumb mode */
972 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
973 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
975 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
976 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
980 /* current = 1: continue on current pc, otherwise continue at <address> */
981 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
983 resume_pc
= *address
;
985 *address
= resume_pc
;
987 /* Make sure that the Armv7 gdb thumb fixups does not
988 * kill the return address
990 switch (arm
->core_state
) {
992 resume_pc
&= 0xFFFFFFFC;
994 case ARM_STATE_THUMB
:
995 case ARM_STATE_THUMB_EE
:
996 /* When the return address is loaded into PC
997 * bit 0 must be 1 to stay in Thumb state
1001 case ARM_STATE_JAZELLE
:
1002 LOG_ERROR("How do I resume into Jazelle state??");
1004 case ARM_STATE_AARCH64
:
1005 LOG_ERROR("Shoudn't be in AARCH64 state");
1008 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
1009 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1013 /* restore dpm_mode at system halt */
1014 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1015 /* called it now before restoring context because it uses cpu
1016 * register r0 for restoring cp15 control register */
1017 retval
= cortex_a_restore_cp15_control_reg(target
);
1018 if (retval
!= ERROR_OK
)
1020 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1021 if (retval
!= ERROR_OK
)
1023 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1024 target
->state
= TARGET_RUNNING
;
1026 /* registers are now invalid */
1027 register_cache_invalidate(arm
->core_cache
);
1030 /* the front-end may request us not to handle breakpoints */
1031 if (handle_breakpoints
) {
1032 /* Single step past breakpoint at current address */
1033 breakpoint
= breakpoint_find(target
, resume_pc
);
1035 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1036 cortex_m3_unset_breakpoint(target
, breakpoint
);
1037 cortex_m3_single_step_core(target
);
1038 cortex_m3_set_breakpoint(target
, breakpoint
);
1046 static int cortex_a_internal_restart(struct target
*target
)
1048 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1049 struct arm
*arm
= &armv7a
->arm
;
1053 * * Restart core and wait for it to be started. Clear ITRen and sticky
1054 * * exception flags: see ARMv7 ARM, C5.9.
1056 * REVISIT: for single stepping, we probably want to
1057 * disable IRQs by default, with optional override...
1060 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1061 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1062 if (retval
!= ERROR_OK
)
1065 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1066 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1068 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1069 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1070 if (retval
!= ERROR_OK
)
1073 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1074 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1075 DRCR_CLEAR_EXCEPTIONS
);
1076 if (retval
!= ERROR_OK
)
1079 int64_t then
= timeval_ms();
1081 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1082 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1083 if (retval
!= ERROR_OK
)
1085 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1087 if (timeval_ms() > then
+ 1000) {
1088 LOG_ERROR("Timeout waiting for resume");
1093 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1094 target
->state
= TARGET_RUNNING
;
1096 /* registers are now invalid */
1097 register_cache_invalidate(arm
->core_cache
);
1102 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1105 struct target_list
*head
;
1106 struct target
*curr
;
1107 target_addr_t address
;
1108 head
= target
->head
;
1109 while (head
!= (struct target_list
*)NULL
) {
1110 curr
= head
->target
;
1111 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)
1112 && target_was_examined(curr
)) {
1113 /* resume current address , not in step mode */
1114 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1115 handle_breakpoints
, 0);
1116 retval
+= cortex_a_internal_restart(curr
);
1124 static int cortex_a_resume(struct target
*target
, int current
,
1125 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1128 /* dummy resume for smp toggle in order to reduce gdb impact */
1129 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1130 /* simulate a start and halt of target */
1131 target
->gdb_service
->target
= NULL
;
1132 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1133 /* fake resume at next poll we play the target core[1], see poll*/
1134 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1137 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1139 target
->gdb_service
->core
[0] = -1;
1140 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1141 if (retval
!= ERROR_OK
)
1144 cortex_a_internal_restart(target
);
1146 if (!debug_execution
) {
1147 target
->state
= TARGET_RUNNING
;
1148 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1149 LOG_DEBUG("target resumed at " TARGET_ADDR_FMT
, address
);
1151 target
->state
= TARGET_DEBUG_RUNNING
;
1152 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1153 LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT
, address
);
1159 static int cortex_a_debug_entry(struct target
*target
)
1161 uint32_t spsr
, dscr
;
1162 int retval
= ERROR_OK
;
1163 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1164 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1165 struct arm
*arm
= &armv7a
->arm
;
1168 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1170 /* REVISIT surely we should not re-read DSCR !! */
1171 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1172 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1173 if (retval
!= ERROR_OK
)
1176 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1177 * imprecise data aborts get discarded by issuing a Data
1178 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1181 /* Enable the ITR execution once we are in debug mode */
1182 dscr
|= DSCR_ITR_EN
;
1183 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1184 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1185 if (retval
!= ERROR_OK
)
1188 /* Examine debug reason */
1189 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1191 /* save address of instruction that triggered the watchpoint? */
1192 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1195 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1196 armv7a
->debug_base
+ CPUDBG_WFAR
,
1198 if (retval
!= ERROR_OK
)
1200 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1203 /* First load register accessible through core debug port */
1204 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1205 if (retval
!= ERROR_OK
)
1209 /* read Saved PSR */
1210 retval
= cortex_a_dap_read_coreregister_u32(target
, &spsr
, 17);
1211 /* store current spsr */
1212 if (retval
!= ERROR_OK
)
1216 buf_set_u32(reg
->value
, 0, 32, spsr
);
1222 /* TODO, Move this */
1223 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1224 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1225 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1227 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1228 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1230 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1231 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1234 /* Are we in an exception handler */
1235 /* armv4_5->exception_number = 0; */
1236 if (armv7a
->post_debug_entry
) {
1237 retval
= armv7a
->post_debug_entry(target
);
1238 if (retval
!= ERROR_OK
)
1245 static int cortex_a_post_debug_entry(struct target
*target
)
1247 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1248 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1251 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1252 retval
= armv7a
->arm
.mrc(target
, 15,
1253 0, 0, /* op1, op2 */
1254 1, 0, /* CRn, CRm */
1255 &cortex_a
->cp15_control_reg
);
1256 if (retval
!= ERROR_OK
)
1258 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1259 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1261 if (!armv7a
->is_armv7r
)
1262 armv7a_read_ttbcr(target
);
1264 if (armv7a
->armv7a_mmu
.armv7a_cache
.info
== -1)
1265 armv7a_identify_cache(target
);
1267 if (armv7a
->is_armv7r
) {
1268 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1270 armv7a
->armv7a_mmu
.mmu_enabled
=
1271 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1273 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1274 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1275 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1276 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1277 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1279 /* switch to SVC mode to read DACR */
1280 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
1281 armv7a
->arm
.mrc(target
, 15,
1283 &cortex_a
->cp15_dacr_reg
);
1285 LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32
,
1286 cortex_a
->cp15_dacr_reg
);
1288 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1292 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1294 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1298 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1299 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1300 if (ERROR_OK
!= retval
)
1303 /* clear bitfield */
1306 dscr
|= value
& bit_mask
;
1308 /* write new DSCR */
1309 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1310 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1314 static int cortex_a_step(struct target
*target
, int current
, target_addr_t address
,
1315 int handle_breakpoints
)
1317 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1318 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1319 struct arm
*arm
= &armv7a
->arm
;
1320 struct breakpoint
*breakpoint
= NULL
;
1321 struct breakpoint stepbreakpoint
;
1325 if (target
->state
!= TARGET_HALTED
) {
1326 LOG_WARNING("target not halted");
1327 return ERROR_TARGET_NOT_HALTED
;
1330 /* current = 1: continue on current pc, otherwise continue at <address> */
1333 buf_set_u32(r
->value
, 0, 32, address
);
1335 address
= buf_get_u32(r
->value
, 0, 32);
1337 /* The front-end may request us not to handle breakpoints.
1338 * But since Cortex-A uses breakpoint for single step,
1339 * we MUST handle breakpoints.
1341 handle_breakpoints
= 1;
1342 if (handle_breakpoints
) {
1343 breakpoint
= breakpoint_find(target
, address
);
1345 cortex_a_unset_breakpoint(target
, breakpoint
);
1348 /* Setup single step breakpoint */
1349 stepbreakpoint
.address
= address
;
1350 stepbreakpoint
.asid
= 0;
1351 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1353 stepbreakpoint
.type
= BKPT_HARD
;
1354 stepbreakpoint
.set
= 0;
1356 /* Disable interrupts during single step if requested */
1357 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1358 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1359 if (ERROR_OK
!= retval
)
1363 /* Break on IVA mismatch */
1364 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1366 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1368 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1369 if (retval
!= ERROR_OK
)
1372 int64_t then
= timeval_ms();
1373 while (target
->state
!= TARGET_HALTED
) {
1374 retval
= cortex_a_poll(target
);
1375 if (retval
!= ERROR_OK
)
1377 if (timeval_ms() > then
+ 1000) {
1378 LOG_ERROR("timeout waiting for target halt");
1383 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1385 /* Re-enable interrupts if they were disabled */
1386 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1387 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1388 if (ERROR_OK
!= retval
)
1393 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1396 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1398 if (target
->state
!= TARGET_HALTED
)
1399 LOG_DEBUG("target stepped");
1404 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1406 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1410 if (armv7a
->pre_restore_context
)
1411 armv7a
->pre_restore_context(target
);
1413 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1417 * Cortex-A Breakpoint and watchpoint functions
1420 /* Setup hardware Breakpoint Register Pair */
1421 static int cortex_a_set_breakpoint(struct target
*target
,
1422 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1427 uint8_t byte_addr_select
= 0x0F;
1428 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1429 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1430 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1432 if (breakpoint
->set
) {
1433 LOG_WARNING("breakpoint already set");
1437 if (breakpoint
->type
== BKPT_HARD
) {
1438 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1440 if (brp_i
>= cortex_a
->brp_num
) {
1441 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1444 breakpoint
->set
= brp_i
+ 1;
1445 if (breakpoint
->length
== 2)
1446 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1447 control
= ((matchmode
& 0x7) << 20)
1448 | (byte_addr_select
<< 5)
1450 brp_list
[brp_i
].used
= 1;
1451 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1452 brp_list
[brp_i
].control
= control
;
1453 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1454 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1455 brp_list
[brp_i
].value
);
1456 if (retval
!= ERROR_OK
)
1458 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1459 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1460 brp_list
[brp_i
].control
);
1461 if (retval
!= ERROR_OK
)
1463 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1464 brp_list
[brp_i
].control
,
1465 brp_list
[brp_i
].value
);
1466 } else if (breakpoint
->type
== BKPT_SOFT
) {
1468 /* length == 2: Thumb breakpoint */
1469 if (breakpoint
->length
== 2)
1470 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1472 /* length == 3: Thumb-2 breakpoint, actual encoding is
1473 * a regular Thumb BKPT instruction but we replace a
1474 * 32bit Thumb-2 instruction, so fix-up the breakpoint
1477 if (breakpoint
->length
== 3) {
1478 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1479 breakpoint
->length
= 4;
1481 /* length == 4, normal ARM breakpoint */
1482 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1484 retval
= target_read_memory(target
,
1485 breakpoint
->address
& 0xFFFFFFFE,
1486 breakpoint
->length
, 1,
1487 breakpoint
->orig_instr
);
1488 if (retval
!= ERROR_OK
)
1491 /* make sure data cache is cleaned & invalidated down to PoC */
1492 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1493 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1494 breakpoint
->length
);
1497 retval
= target_write_memory(target
,
1498 breakpoint
->address
& 0xFFFFFFFE,
1499 breakpoint
->length
, 1, code
);
1500 if (retval
!= ERROR_OK
)
1503 /* update i-cache at breakpoint location */
1504 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1505 breakpoint
->length
);
1506 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1507 breakpoint
->length
);
1509 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1515 static int cortex_a_set_context_breakpoint(struct target
*target
,
1516 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1518 int retval
= ERROR_FAIL
;
1521 uint8_t byte_addr_select
= 0x0F;
1522 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1523 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1524 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1526 if (breakpoint
->set
) {
1527 LOG_WARNING("breakpoint already set");
1530 /*check available context BRPs*/
1531 while ((brp_list
[brp_i
].used
||
1532 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1535 if (brp_i
>= cortex_a
->brp_num
) {
1536 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1540 breakpoint
->set
= brp_i
+ 1;
1541 control
= ((matchmode
& 0x7) << 20)
1542 | (byte_addr_select
<< 5)
1544 brp_list
[brp_i
].used
= 1;
1545 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1546 brp_list
[brp_i
].control
= control
;
1547 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1548 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1549 brp_list
[brp_i
].value
);
1550 if (retval
!= ERROR_OK
)
1552 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1553 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1554 brp_list
[brp_i
].control
);
1555 if (retval
!= ERROR_OK
)
1557 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1558 brp_list
[brp_i
].control
,
1559 brp_list
[brp_i
].value
);
1564 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1566 int retval
= ERROR_FAIL
;
1567 int brp_1
= 0; /* holds the contextID pair */
1568 int brp_2
= 0; /* holds the IVA pair */
1569 uint32_t control_CTX
, control_IVA
;
1570 uint8_t CTX_byte_addr_select
= 0x0F;
1571 uint8_t IVA_byte_addr_select
= 0x0F;
1572 uint8_t CTX_machmode
= 0x03;
1573 uint8_t IVA_machmode
= 0x01;
1574 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1575 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1576 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1578 if (breakpoint
->set
) {
1579 LOG_WARNING("breakpoint already set");
1582 /*check available context BRPs*/
1583 while ((brp_list
[brp_1
].used
||
1584 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1587 printf("brp(CTX) found num: %d\n", brp_1
);
1588 if (brp_1
>= cortex_a
->brp_num
) {
1589 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1593 while ((brp_list
[brp_2
].used
||
1594 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1597 printf("brp(IVA) found num: %d\n", brp_2
);
1598 if (brp_2
>= cortex_a
->brp_num
) {
1599 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1603 breakpoint
->set
= brp_1
+ 1;
1604 breakpoint
->linked_BRP
= brp_2
;
1605 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1608 | (CTX_byte_addr_select
<< 5)
1610 brp_list
[brp_1
].used
= 1;
1611 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1612 brp_list
[brp_1
].control
= control_CTX
;
1613 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1614 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1615 brp_list
[brp_1
].value
);
1616 if (retval
!= ERROR_OK
)
1618 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1619 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1620 brp_list
[brp_1
].control
);
1621 if (retval
!= ERROR_OK
)
1624 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1626 | (IVA_byte_addr_select
<< 5)
1628 brp_list
[brp_2
].used
= 1;
1629 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1630 brp_list
[brp_2
].control
= control_IVA
;
1631 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1632 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1633 brp_list
[brp_2
].value
);
1634 if (retval
!= ERROR_OK
)
1636 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1637 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1638 brp_list
[brp_2
].control
);
1639 if (retval
!= ERROR_OK
)
1645 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1648 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1649 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1650 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1652 if (!breakpoint
->set
) {
1653 LOG_WARNING("breakpoint not set");
1657 if (breakpoint
->type
== BKPT_HARD
) {
1658 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1659 int brp_i
= breakpoint
->set
- 1;
1660 int brp_j
= breakpoint
->linked_BRP
;
1661 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1662 LOG_DEBUG("Invalid BRP number in breakpoint");
1665 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1666 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1667 brp_list
[brp_i
].used
= 0;
1668 brp_list
[brp_i
].value
= 0;
1669 brp_list
[brp_i
].control
= 0;
1670 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1671 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1672 brp_list
[brp_i
].control
);
1673 if (retval
!= ERROR_OK
)
1675 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1676 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1677 brp_list
[brp_i
].value
);
1678 if (retval
!= ERROR_OK
)
1680 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1681 LOG_DEBUG("Invalid BRP number in breakpoint");
1684 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1685 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1686 brp_list
[brp_j
].used
= 0;
1687 brp_list
[brp_j
].value
= 0;
1688 brp_list
[brp_j
].control
= 0;
1689 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1690 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1691 brp_list
[brp_j
].control
);
1692 if (retval
!= ERROR_OK
)
1694 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1695 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1696 brp_list
[brp_j
].value
);
1697 if (retval
!= ERROR_OK
)
1699 breakpoint
->linked_BRP
= 0;
1700 breakpoint
->set
= 0;
1704 int brp_i
= breakpoint
->set
- 1;
1705 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1706 LOG_DEBUG("Invalid BRP number in breakpoint");
1709 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1710 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1711 brp_list
[brp_i
].used
= 0;
1712 brp_list
[brp_i
].value
= 0;
1713 brp_list
[brp_i
].control
= 0;
1714 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1715 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1716 brp_list
[brp_i
].control
);
1717 if (retval
!= ERROR_OK
)
1719 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1720 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1721 brp_list
[brp_i
].value
);
1722 if (retval
!= ERROR_OK
)
1724 breakpoint
->set
= 0;
1729 /* make sure data cache is cleaned & invalidated down to PoC */
1730 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1731 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1732 breakpoint
->length
);
1735 /* restore original instruction (kept in target endianness) */
1736 if (breakpoint
->length
== 4) {
1737 retval
= target_write_memory(target
,
1738 breakpoint
->address
& 0xFFFFFFFE,
1739 4, 1, breakpoint
->orig_instr
);
1740 if (retval
!= ERROR_OK
)
1743 retval
= target_write_memory(target
,
1744 breakpoint
->address
& 0xFFFFFFFE,
1745 2, 1, breakpoint
->orig_instr
);
1746 if (retval
!= ERROR_OK
)
1750 /* update i-cache at breakpoint location */
1751 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1752 breakpoint
->length
);
1753 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1754 breakpoint
->length
);
1756 breakpoint
->set
= 0;
1761 static int cortex_a_add_breakpoint(struct target
*target
,
1762 struct breakpoint
*breakpoint
)
1764 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1766 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1767 LOG_INFO("no hardware breakpoint available");
1768 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1771 if (breakpoint
->type
== BKPT_HARD
)
1772 cortex_a
->brp_num_available
--;
1774 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1777 static int cortex_a_add_context_breakpoint(struct target
*target
,
1778 struct breakpoint
*breakpoint
)
1780 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1782 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1783 LOG_INFO("no hardware breakpoint available");
1784 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1787 if (breakpoint
->type
== BKPT_HARD
)
1788 cortex_a
->brp_num_available
--;
1790 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1793 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1794 struct breakpoint
*breakpoint
)
1796 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1798 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1799 LOG_INFO("no hardware breakpoint available");
1800 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1803 if (breakpoint
->type
== BKPT_HARD
)
1804 cortex_a
->brp_num_available
--;
1806 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1810 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1812 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1815 /* It is perfectly possible to remove breakpoints while the target is running */
1816 if (target
->state
!= TARGET_HALTED
) {
1817 LOG_WARNING("target not halted");
1818 return ERROR_TARGET_NOT_HALTED
;
1822 if (breakpoint
->set
) {
1823 cortex_a_unset_breakpoint(target
, breakpoint
);
1824 if (breakpoint
->type
== BKPT_HARD
)
1825 cortex_a
->brp_num_available
++;
1833 * Cortex-A Reset functions
1836 static int cortex_a_assert_reset(struct target
*target
)
1838 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1842 /* FIXME when halt is requested, make it work somehow... */
1844 /* This function can be called in "target not examined" state */
1846 /* Issue some kind of warm reset. */
1847 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1848 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1849 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1850 /* REVISIT handle "pulls" cases, if there's
1851 * hardware that needs them to work.
1855 * FIXME: fix reset when transport is SWD. This is a temporary
1856 * work-around for release v0.10 that is not intended to stay!
1858 if (transport_is_swd() ||
1859 (target
->reset_halt
&& (jtag_get_reset_config() & RESET_SRST_NO_GATING
)))
1860 jtag_add_reset(0, 1);
1863 LOG_ERROR("%s: how to reset?", target_name(target
));
1867 /* registers are now invalid */
1868 if (target_was_examined(target
))
1869 register_cache_invalidate(armv7a
->arm
.core_cache
);
1871 target
->state
= TARGET_RESET
;
1876 static int cortex_a_deassert_reset(struct target
*target
)
1882 /* be certain SRST is off */
1883 jtag_add_reset(0, 0);
1885 if (target_was_examined(target
)) {
1886 retval
= cortex_a_poll(target
);
1887 if (retval
!= ERROR_OK
)
1891 if (target
->reset_halt
) {
1892 if (target
->state
!= TARGET_HALTED
) {
1893 LOG_WARNING("%s: ran after reset and before halt ...",
1894 target_name(target
));
1895 if (target_was_examined(target
)) {
1896 retval
= target_halt(target
);
1897 if (retval
!= ERROR_OK
)
1900 target
->state
= TARGET_UNKNOWN
;
1907 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1909 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1910 * New desired mode must be in mode. Current value of DSCR must be in
1911 * *dscr, which is updated with new value.
1913 * This function elides actually sending the mode-change over the debug
1914 * interface if the mode is already set as desired.
1916 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1917 if (new_dscr
!= *dscr
) {
1918 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1919 int retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1920 armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1921 if (retval
== ERROR_OK
)
1929 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
1930 uint32_t value
, uint32_t *dscr
)
1932 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1933 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1934 int64_t then
= timeval_ms();
1937 while ((*dscr
& mask
) != value
) {
1938 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1939 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1940 if (retval
!= ERROR_OK
)
1942 if (timeval_ms() > then
+ 1000) {
1943 LOG_ERROR("timeout waiting for DSCR bit change");
1950 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
1951 uint32_t *data
, uint32_t *dscr
)
1954 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1956 /* Move from coprocessor to R0. */
1957 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1958 if (retval
!= ERROR_OK
)
1961 /* Move from R0 to DTRTX. */
1962 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
1963 if (retval
!= ERROR_OK
)
1966 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
1967 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1968 * must also check TXfull_l). Most of the time this will be free
1969 * because TXfull_l will be set immediately and cached in dscr. */
1970 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
1971 DSCR_DTRTX_FULL_LATCHED
, dscr
);
1972 if (retval
!= ERROR_OK
)
1975 /* Read the value transferred to DTRTX. */
1976 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1977 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
1978 if (retval
!= ERROR_OK
)
1984 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
1985 uint32_t *dfsr
, uint32_t *dscr
)
1990 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
1991 if (retval
!= ERROR_OK
)
1996 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
1997 if (retval
!= ERROR_OK
)
2004 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
2005 uint32_t data
, uint32_t *dscr
)
2008 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2010 /* Write the value into DTRRX. */
2011 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2012 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2013 if (retval
!= ERROR_OK
)
2016 /* Move from DTRRX to R0. */
2017 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
2018 if (retval
!= ERROR_OK
)
2021 /* Move from R0 to coprocessor. */
2022 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2023 if (retval
!= ERROR_OK
)
2026 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2027 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2028 * check RXfull_l). Most of the time this will be free because RXfull_l
2029 * will be cleared immediately and cached in dscr. */
2030 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2031 if (retval
!= ERROR_OK
)
2037 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
2038 uint32_t dfsr
, uint32_t *dscr
)
2042 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2043 if (retval
!= ERROR_OK
)
2046 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2047 if (retval
!= ERROR_OK
)
2053 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
2055 uint32_t status
, upper4
;
2057 if (dfsr
& (1 << 9)) {
2059 status
= dfsr
& 0x3f;
2060 upper4
= status
>> 2;
2061 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
2062 return ERROR_TARGET_TRANSLATION_FAULT
;
2063 else if (status
== 33)
2064 return ERROR_TARGET_UNALIGNED_ACCESS
;
2066 return ERROR_TARGET_DATA_ABORT
;
2068 /* Normal format. */
2069 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
2071 return ERROR_TARGET_UNALIGNED_ACCESS
;
2072 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
2073 status
== 9 || status
== 11 || status
== 13 || status
== 15)
2074 return ERROR_TARGET_TRANSLATION_FAULT
;
2076 return ERROR_TARGET_DATA_ABORT
;
2080 static int cortex_a_write_cpu_memory_slow(struct target
*target
,
2081 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2083 /* Writes count objects of size size from *buffer. Old value of DSCR must
2084 * be in *dscr; updated to new value. This is slow because it works for
2085 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2086 * the address is aligned, cortex_a_write_cpu_memory_fast should be
2089 * - Address is in R0.
2090 * - R0 is marked dirty.
2092 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2093 struct arm
*arm
= &armv7a
->arm
;
2096 /* Mark register R1 as dirty, to use for transferring data. */
2097 arm_reg_current(arm
, 1)->dirty
= true;
2099 /* Switch to non-blocking mode if not already in that mode. */
2100 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2101 if (retval
!= ERROR_OK
)
2104 /* Go through the objects. */
2106 /* Write the value to store into DTRRX. */
2107 uint32_t data
, opcode
;
2111 data
= target_buffer_get_u16(target
, buffer
);
2113 data
= target_buffer_get_u32(target
, buffer
);
2114 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2115 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2116 if (retval
!= ERROR_OK
)
2119 /* Transfer the value from DTRRX to R1. */
2120 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
2121 if (retval
!= ERROR_OK
)
2124 /* Write the value transferred to R1 into memory. */
2126 opcode
= ARMV4_5_STRB_IP(1, 0);
2128 opcode
= ARMV4_5_STRH_IP(1, 0);
2130 opcode
= ARMV4_5_STRW_IP(1, 0);
2131 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2132 if (retval
!= ERROR_OK
)
2135 /* Check for faults and return early. */
2136 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2137 return ERROR_OK
; /* A data fault is not considered a system failure. */
2139 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2140 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2141 * must also check RXfull_l). Most of the time this will be free
2142 * because RXfull_l will be cleared immediately and cached in dscr. */
2143 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2144 if (retval
!= ERROR_OK
)
2155 static int cortex_a_write_cpu_memory_fast(struct target
*target
,
2156 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2158 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2159 * in *dscr; updated to new value. This is fast but only works for
2160 * word-sized objects at aligned addresses.
2162 * - Address is in R0 and must be a multiple of 4.
2163 * - R0 is marked dirty.
2165 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2168 /* Switch to fast mode if not already in that mode. */
2169 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2170 if (retval
!= ERROR_OK
)
2173 /* Latch STC instruction. */
2174 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2175 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2176 if (retval
!= ERROR_OK
)
2179 /* Transfer all the data and issue all the instructions. */
2180 return mem_ap_write_buf_noincr(armv7a
->debug_ap
, buffer
,
2181 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
2184 static int cortex_a_write_cpu_memory(struct target
*target
,
2185 uint32_t address
, uint32_t size
,
2186 uint32_t count
, const uint8_t *buffer
)
2188 /* Write memory through the CPU. */
2189 int retval
, final_retval
;
2190 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2191 struct arm
*arm
= &armv7a
->arm
;
2192 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2194 LOG_DEBUG("Writing CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2195 address
, size
, count
);
2196 if (target
->state
!= TARGET_HALTED
) {
2197 LOG_WARNING("target not halted");
2198 return ERROR_TARGET_NOT_HALTED
;
2204 /* Clear any abort. */
2205 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2206 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2207 if (retval
!= ERROR_OK
)
2211 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2212 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2213 if (retval
!= ERROR_OK
)
2216 /* Switch to non-blocking mode if not already in that mode. */
2217 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2218 if (retval
!= ERROR_OK
)
2221 /* Mark R0 as dirty. */
2222 arm_reg_current(arm
, 0)->dirty
= true;
2224 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2225 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2226 if (retval
!= ERROR_OK
)
2229 /* Get the memory address into R0. */
2230 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2231 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2232 if (retval
!= ERROR_OK
)
2234 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2235 if (retval
!= ERROR_OK
)
2238 if (size
== 4 && (address
% 4) == 0) {
2239 /* We are doing a word-aligned transfer, so use fast mode. */
2240 retval
= cortex_a_write_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2242 /* Use slow path. */
2243 retval
= cortex_a_write_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2247 final_retval
= retval
;
2249 /* Switch to non-blocking mode if not already in that mode. */
2250 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2251 if (final_retval
== ERROR_OK
)
2252 final_retval
= retval
;
2254 /* Wait for last issued instruction to complete. */
2255 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2256 if (final_retval
== ERROR_OK
)
2257 final_retval
= retval
;
2259 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2260 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2261 * check RXfull_l). Most of the time this will be free because RXfull_l
2262 * will be cleared immediately and cached in dscr. However, don't do this
2263 * if there is fault, because then the instruction might not have completed
2265 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2266 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2267 if (retval
!= ERROR_OK
)
2271 /* If there were any sticky abort flags, clear them. */
2272 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2274 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2275 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2276 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2281 /* Handle synchronous data faults. */
2282 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2283 if (final_retval
== ERROR_OK
) {
2284 /* Final return value will reflect cause of fault. */
2285 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2286 if (retval
== ERROR_OK
) {
2287 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2288 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2290 final_retval
= retval
;
2292 /* Fault destroyed DFAR/DFSR; restore them. */
2293 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2294 if (retval
!= ERROR_OK
)
2295 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2298 /* Handle asynchronous data faults. */
2299 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2300 if (final_retval
== ERROR_OK
)
2301 /* No other error has been recorded so far, so keep this one. */
2302 final_retval
= ERROR_TARGET_DATA_ABORT
;
2305 /* If the DCC is nonempty, clear it. */
2306 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2308 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2309 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2310 if (final_retval
== ERROR_OK
)
2311 final_retval
= retval
;
2313 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2314 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2315 if (final_retval
== ERROR_OK
)
2316 final_retval
= retval
;
2320 return final_retval
;
2323 static int cortex_a_read_cpu_memory_slow(struct target
*target
,
2324 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2326 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2327 * in *dscr; updated to new value. This is slow because it works for
2328 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2329 * the address is aligned, cortex_a_read_cpu_memory_fast should be
2332 * - Address is in R0.
2333 * - R0 is marked dirty.
2335 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2336 struct arm
*arm
= &armv7a
->arm
;
2339 /* Mark register R1 as dirty, to use for transferring data. */
2340 arm_reg_current(arm
, 1)->dirty
= true;
2342 /* Switch to non-blocking mode if not already in that mode. */
2343 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2344 if (retval
!= ERROR_OK
)
2347 /* Go through the objects. */
2349 /* Issue a load of the appropriate size to R1. */
2350 uint32_t opcode
, data
;
2352 opcode
= ARMV4_5_LDRB_IP(1, 0);
2354 opcode
= ARMV4_5_LDRH_IP(1, 0);
2356 opcode
= ARMV4_5_LDRW_IP(1, 0);
2357 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2358 if (retval
!= ERROR_OK
)
2361 /* Issue a write of R1 to DTRTX. */
2362 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2363 if (retval
!= ERROR_OK
)
2366 /* Check for faults and return early. */
2367 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2368 return ERROR_OK
; /* A data fault is not considered a system failure. */
2370 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2371 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2372 * must also check TXfull_l). Most of the time this will be free
2373 * because TXfull_l will be set immediately and cached in dscr. */
2374 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2375 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2376 if (retval
!= ERROR_OK
)
2379 /* Read the value transferred to DTRTX into the buffer. */
2380 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2381 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2382 if (retval
!= ERROR_OK
)
2385 *buffer
= (uint8_t) data
;
2387 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2389 target_buffer_set_u32(target
, buffer
, data
);
2399 static int cortex_a_read_cpu_memory_fast(struct target
*target
,
2400 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2402 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2403 * *dscr; updated to new value. This is fast but only works for word-sized
2404 * objects at aligned addresses.
2406 * - Address is in R0 and must be a multiple of 4.
2407 * - R0 is marked dirty.
2409 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2413 /* Switch to non-blocking mode if not already in that mode. */
2414 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2415 if (retval
!= ERROR_OK
)
2418 /* Issue the LDC instruction via a write to ITR. */
2419 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2420 if (retval
!= ERROR_OK
)
2426 /* Switch to fast mode if not already in that mode. */
2427 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2428 if (retval
!= ERROR_OK
)
2431 /* Latch LDC instruction. */
2432 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2433 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2434 if (retval
!= ERROR_OK
)
2437 /* Read the value transferred to DTRTX into the buffer. Due to fast
2438 * mode rules, this blocks until the instruction finishes executing and
2439 * then reissues the read instruction to read the next word from
2440 * memory. The last read of DTRTX in this call reads the second-to-last
2441 * word from memory and issues the read instruction for the last word.
2443 retval
= mem_ap_read_buf_noincr(armv7a
->debug_ap
, buffer
,
2444 4, count
, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2445 if (retval
!= ERROR_OK
)
2449 buffer
+= count
* 4;
2452 /* Wait for last issued instruction to complete. */
2453 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2454 if (retval
!= ERROR_OK
)
2457 /* Switch to non-blocking mode if not already in that mode. */
2458 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2459 if (retval
!= ERROR_OK
)
2462 /* Check for faults and return early. */
2463 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2464 return ERROR_OK
; /* A data fault is not considered a system failure. */
2466 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2467 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2468 * check TXfull_l). Most of the time this will be free because TXfull_l
2469 * will be set immediately and cached in dscr. */
2470 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2471 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2472 if (retval
!= ERROR_OK
)
2475 /* Read the value transferred to DTRTX into the buffer. This is the last
2477 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2478 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2479 if (retval
!= ERROR_OK
)
2481 target_buffer_set_u32(target
, buffer
, u32
);
2486 static int cortex_a_read_cpu_memory(struct target
*target
,
2487 uint32_t address
, uint32_t size
,
2488 uint32_t count
, uint8_t *buffer
)
2490 /* Read memory through the CPU. */
2491 int retval
, final_retval
;
2492 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2493 struct arm
*arm
= &armv7a
->arm
;
2494 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2496 LOG_DEBUG("Reading CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2497 address
, size
, count
);
2498 if (target
->state
!= TARGET_HALTED
) {
2499 LOG_WARNING("target not halted");
2500 return ERROR_TARGET_NOT_HALTED
;
2506 /* Clear any abort. */
2507 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2508 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2509 if (retval
!= ERROR_OK
)
2513 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2514 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2515 if (retval
!= ERROR_OK
)
2518 /* Switch to non-blocking mode if not already in that mode. */
2519 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2520 if (retval
!= ERROR_OK
)
2523 /* Mark R0 as dirty. */
2524 arm_reg_current(arm
, 0)->dirty
= true;
2526 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2527 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2528 if (retval
!= ERROR_OK
)
2531 /* Get the memory address into R0. */
2532 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2533 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2534 if (retval
!= ERROR_OK
)
2536 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2537 if (retval
!= ERROR_OK
)
2540 if (size
== 4 && (address
% 4) == 0) {
2541 /* We are doing a word-aligned transfer, so use fast mode. */
2542 retval
= cortex_a_read_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2544 /* Use slow path. */
2545 retval
= cortex_a_read_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2549 final_retval
= retval
;
2551 /* Switch to non-blocking mode if not already in that mode. */
2552 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2553 if (final_retval
== ERROR_OK
)
2554 final_retval
= retval
;
2556 /* Wait for last issued instruction to complete. */
2557 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2558 if (final_retval
== ERROR_OK
)
2559 final_retval
= retval
;
2561 /* If there were any sticky abort flags, clear them. */
2562 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2564 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2565 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2566 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2571 /* Handle synchronous data faults. */
2572 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2573 if (final_retval
== ERROR_OK
) {
2574 /* Final return value will reflect cause of fault. */
2575 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2576 if (retval
== ERROR_OK
) {
2577 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2578 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2580 final_retval
= retval
;
2582 /* Fault destroyed DFAR/DFSR; restore them. */
2583 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2584 if (retval
!= ERROR_OK
)
2585 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2588 /* Handle asynchronous data faults. */
2589 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2590 if (final_retval
== ERROR_OK
)
2591 /* No other error has been recorded so far, so keep this one. */
2592 final_retval
= ERROR_TARGET_DATA_ABORT
;
2595 /* If the DCC is nonempty, clear it. */
2596 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2598 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2599 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2600 if (final_retval
== ERROR_OK
)
2601 final_retval
= retval
;
2603 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2604 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2605 if (final_retval
== ERROR_OK
)
2606 final_retval
= retval
;
2610 return final_retval
;
2615 * Cortex-A Memory access
2617 * This is same Cortex-M3 but we must also use the correct
2618 * ap number for every access.
2621 static int cortex_a_read_phys_memory(struct target
*target
,
2622 target_addr_t address
, uint32_t size
,
2623 uint32_t count
, uint8_t *buffer
)
2627 if (!count
|| !buffer
)
2628 return ERROR_COMMAND_SYNTAX_ERROR
;
2630 LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2631 address
, size
, count
);
2633 /* read memory through the CPU */
2634 cortex_a_prep_memaccess(target
, 1);
2635 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2636 cortex_a_post_memaccess(target
, 1);
2641 static int cortex_a_read_memory(struct target
*target
, target_addr_t address
,
2642 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2646 /* cortex_a handles unaligned memory access */
2647 LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2648 address
, size
, count
);
2650 cortex_a_prep_memaccess(target
, 0);
2651 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2652 cortex_a_post_memaccess(target
, 0);
2657 static int cortex_a_write_phys_memory(struct target
*target
,
2658 target_addr_t address
, uint32_t size
,
2659 uint32_t count
, const uint8_t *buffer
)
2663 if (!count
|| !buffer
)
2664 return ERROR_COMMAND_SYNTAX_ERROR
;
2666 LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2667 address
, size
, count
);
2669 /* write memory through the CPU */
2670 cortex_a_prep_memaccess(target
, 1);
2671 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2672 cortex_a_post_memaccess(target
, 1);
2677 static int cortex_a_write_memory(struct target
*target
, target_addr_t address
,
2678 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2682 /* cortex_a handles unaligned memory access */
2683 LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2684 address
, size
, count
);
2686 /* memory writes bypass the caches, must flush before writing */
2687 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2689 cortex_a_prep_memaccess(target
, 0);
2690 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2691 cortex_a_post_memaccess(target
, 0);
2695 static int cortex_a_read_buffer(struct target
*target
, target_addr_t address
,
2696 uint32_t count
, uint8_t *buffer
)
2700 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2701 * will have something to do with the size we leave to it. */
2702 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2703 if (address
& size
) {
2704 int retval
= target_read_memory(target
, address
, size
, 1, buffer
);
2705 if (retval
!= ERROR_OK
)
2713 /* Read the data with as large access size as possible. */
2714 for (; size
> 0; size
/= 2) {
2715 uint32_t aligned
= count
- count
% size
;
2717 int retval
= target_read_memory(target
, address
, size
, aligned
/ size
, buffer
);
2718 if (retval
!= ERROR_OK
)
2729 static int cortex_a_write_buffer(struct target
*target
, target_addr_t address
,
2730 uint32_t count
, const uint8_t *buffer
)
2734 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2735 * will have something to do with the size we leave to it. */
2736 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2737 if (address
& size
) {
2738 int retval
= target_write_memory(target
, address
, size
, 1, buffer
);
2739 if (retval
!= ERROR_OK
)
2747 /* Write the data with as large access size as possible. */
2748 for (; size
> 0; size
/= 2) {
2749 uint32_t aligned
= count
- count
% size
;
2751 int retval
= target_write_memory(target
, address
, size
, aligned
/ size
, buffer
);
2752 if (retval
!= ERROR_OK
)
2763 static int cortex_a_handle_target_request(void *priv
)
2765 struct target
*target
= priv
;
2766 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2769 if (!target_was_examined(target
))
2771 if (!target
->dbg_msg_enabled
)
2774 if (target
->state
== TARGET_RUNNING
) {
2777 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2778 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2780 /* check if we have data */
2781 int64_t then
= timeval_ms();
2782 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2783 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2784 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2785 if (retval
== ERROR_OK
) {
2786 target_request(target
, request
);
2787 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2788 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2790 if (timeval_ms() > then
+ 1000) {
2791 LOG_ERROR("Timeout waiting for dtr tx full");
2801 * Cortex-A target information and configuration
2804 static int cortex_a_examine_first(struct target
*target
)
2806 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2807 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2808 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2811 int retval
= ERROR_OK
;
2812 uint32_t didr
, cpuid
, dbg_osreg
;
2814 /* Search for the APB-AP - it is needed for access to debug registers */
2815 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2816 if (retval
!= ERROR_OK
) {
2817 LOG_ERROR("Could not find APB-AP for debug access");
2821 retval
= mem_ap_init(armv7a
->debug_ap
);
2822 if (retval
!= ERROR_OK
) {
2823 LOG_ERROR("Could not initialize the APB-AP");
2827 armv7a
->debug_ap
->memaccess_tck
= 80;
2829 if (!target
->dbgbase_set
) {
2831 /* Get ROM Table base */
2833 int32_t coreidx
= target
->coreid
;
2834 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2836 retval
= dap_get_debugbase(armv7a
->debug_ap
, &dbgbase
, &apid
);
2837 if (retval
!= ERROR_OK
)
2839 /* Lookup 0x15 -- Processor DAP */
2840 retval
= dap_lookup_cs_component(armv7a
->debug_ap
, dbgbase
, 0x15,
2841 &armv7a
->debug_base
, &coreidx
);
2842 if (retval
!= ERROR_OK
) {
2843 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2847 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2848 target
->coreid
, armv7a
->debug_base
);
2850 armv7a
->debug_base
= target
->dbgbase
;
2852 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2853 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2854 if (retval
!= ERROR_OK
) {
2855 LOG_DEBUG("Examine %s failed", "DIDR");
2859 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2860 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2861 if (retval
!= ERROR_OK
) {
2862 LOG_DEBUG("Examine %s failed", "CPUID");
2866 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
2867 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
2869 cortex_a
->didr
= didr
;
2870 cortex_a
->cpuid
= cpuid
;
2872 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2873 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
2874 if (retval
!= ERROR_OK
)
2876 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
2878 if ((dbg_osreg
& PRSR_POWERUP_STATUS
) == 0) {
2879 LOG_ERROR("target->coreid %" PRId32
" powered down!", target
->coreid
);
2880 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
2881 return ERROR_TARGET_INIT_FAILED
;
2884 if (dbg_osreg
& PRSR_STICKY_RESET_STATUS
)
2885 LOG_DEBUG("target->coreid %" PRId32
" was reset!", target
->coreid
);
2887 /* Read DBGOSLSR and check if OSLK is implemented */
2888 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2889 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
2890 if (retval
!= ERROR_OK
)
2892 LOG_DEBUG("target->coreid %" PRId32
" DBGOSLSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
2894 /* check if OS Lock is implemented */
2895 if ((dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM0
|| (dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM1
) {
2896 /* check if OS Lock is set */
2897 if (dbg_osreg
& OSLSR_OSLK
) {
2898 LOG_DEBUG("target->coreid %" PRId32
" OSLock set! Trying to unlock", target
->coreid
);
2900 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2901 armv7a
->debug_base
+ CPUDBG_OSLAR
,
2903 if (retval
== ERROR_OK
)
2904 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2905 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
2907 /* if we fail to access the register or cannot reset the OSLK bit, bail out */
2908 if (retval
!= ERROR_OK
|| (dbg_osreg
& OSLSR_OSLK
) != 0) {
2909 LOG_ERROR("target->coreid %" PRId32
" OSLock sticky, core not powered?",
2911 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
2912 return ERROR_TARGET_INIT_FAILED
;
2917 armv7a
->arm
.core_type
= ARM_MODE_MON
;
2919 /* Avoid recreating the registers cache */
2920 if (!target_was_examined(target
)) {
2921 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
2922 if (retval
!= ERROR_OK
)
2926 /* Setup Breakpoint Register Pairs */
2927 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
2928 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
2929 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
2930 free(cortex_a
->brp_list
);
2931 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
2932 /* cortex_a->brb_enabled = ????; */
2933 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
2934 cortex_a
->brp_list
[i
].used
= 0;
2935 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
2936 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
2938 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
2939 cortex_a
->brp_list
[i
].value
= 0;
2940 cortex_a
->brp_list
[i
].control
= 0;
2941 cortex_a
->brp_list
[i
].BRPn
= i
;
2944 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
2946 /* select debug_ap as default */
2947 swjdp
->apsel
= armv7a
->debug_ap
->ap_num
;
2949 target_set_examined(target
);
2953 static int cortex_a_examine(struct target
*target
)
2955 int retval
= ERROR_OK
;
2957 /* Reestablish communication after target reset */
2958 retval
= cortex_a_examine_first(target
);
2960 /* Configure core debug access */
2961 if (retval
== ERROR_OK
)
2962 retval
= cortex_a_init_debug_access(target
);
2968 * Cortex-A target creation and initialization
2971 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
2972 struct target
*target
)
2974 /* examine_first() does a bunch of this */
2975 arm_semihosting_init(target
);
2979 static int cortex_a_init_arch_info(struct target
*target
,
2980 struct cortex_a_common
*cortex_a
, struct adiv5_dap
*dap
)
2982 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2984 /* Setup struct cortex_a_common */
2985 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
2986 armv7a
->arm
.dap
= dap
;
2988 /* register arch-specific functions */
2989 armv7a
->examine_debug_reason
= NULL
;
2991 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
2993 armv7a
->pre_restore_context
= NULL
;
2995 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
2998 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3000 /* REVISIT v7a setup should be in a v7a-specific routine */
3001 armv7a_init_arch_info(target
, armv7a
);
3002 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
3007 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
3009 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3010 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3011 struct adiv5_private_config
*pc
;
3013 if (target
->private_config
== NULL
)
3016 pc
= (struct adiv5_private_config
*)target
->private_config
;
3018 cortex_a
->armv7a_common
.is_armv7r
= false;
3020 cortex_a
->armv7a_common
.arm
.arm_vfp_version
= ARM_VFP_V3
;
3022 return cortex_a_init_arch_info(target
, cortex_a
, pc
->dap
);
3025 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
3027 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3028 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3029 struct adiv5_private_config
*pc
;
3031 pc
= (struct adiv5_private_config
*)target
->private_config
;
3032 if (adiv5_verify_config(pc
) != ERROR_OK
)
3035 cortex_a
->armv7a_common
.is_armv7r
= true;
3037 return cortex_a_init_arch_info(target
, cortex_a
, pc
->dap
);
3040 static void cortex_a_deinit_target(struct target
*target
)
3042 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3043 struct arm_dpm
*dpm
= &cortex_a
->armv7a_common
.dpm
;
3045 free(cortex_a
->brp_list
);
3048 free(target
->private_config
);
3052 static int cortex_a_mmu(struct target
*target
, int *enabled
)
3054 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3056 if (target
->state
!= TARGET_HALTED
) {
3057 LOG_ERROR("%s: target not halted", __func__
);
3058 return ERROR_TARGET_INVALID
;
3061 if (armv7a
->is_armv7r
)
3064 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
3069 static int cortex_a_virt2phys(struct target
*target
,
3070 target_addr_t virt
, target_addr_t
*phys
)
3073 int mmu_enabled
= 0;
3076 * If the MMU was not enabled at debug entry, there is no
3077 * way of knowing if there was ever a valid configuration
3078 * for it and thus it's not safe to enable it. In this case,
3079 * just return the virtual address as physical.
3081 cortex_a_mmu(target
, &mmu_enabled
);
3087 /* mmu must be enable in order to get a correct translation */
3088 retval
= cortex_a_mmu_modify(target
, 1);
3089 if (retval
!= ERROR_OK
)
3091 return armv7a_mmu_translate_va_pa(target
, (uint32_t)virt
,
3092 (uint32_t *)phys
, 1);
3095 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
3097 struct target
*target
= get_current_target(CMD_CTX
);
3098 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3100 return armv7a_handle_cache_info_command(CMD_CTX
,
3101 &armv7a
->armv7a_mmu
.armv7a_cache
);
3105 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
3107 struct target
*target
= get_current_target(CMD_CTX
);
3108 if (!target_was_examined(target
)) {
3109 LOG_ERROR("target not examined yet");
3113 return cortex_a_init_debug_access(target
);
3115 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
3117 struct target
*target
= get_current_target(CMD_CTX
);
3118 /* check target is an smp target */
3119 struct target_list
*head
;
3120 struct target
*curr
;
3121 head
= target
->head
;
3123 if (head
!= (struct target_list
*)NULL
) {
3124 while (head
!= (struct target_list
*)NULL
) {
3125 curr
= head
->target
;
3129 /* fixes the target display to the debugger */
3130 target
->gdb_service
->target
= target
;
3135 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
3137 struct target
*target
= get_current_target(CMD_CTX
);
3138 struct target_list
*head
;
3139 struct target
*curr
;
3140 head
= target
->head
;
3141 if (head
!= (struct target_list
*)NULL
) {
3143 while (head
!= (struct target_list
*)NULL
) {
3144 curr
= head
->target
;
3152 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
3154 struct target
*target
= get_current_target(CMD_CTX
);
3155 int retval
= ERROR_OK
;
3156 struct target_list
*head
;
3157 head
= target
->head
;
3158 if (head
!= (struct target_list
*)NULL
) {
3159 if (CMD_ARGC
== 1) {
3161 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
3162 if (ERROR_OK
!= retval
)
3164 target
->gdb_service
->core
[1] = coreid
;
3167 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
3168 , target
->gdb_service
->core
[1]);
3173 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
3175 struct target
*target
= get_current_target(CMD_CTX
);
3176 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3178 static const Jim_Nvp nvp_maskisr_modes
[] = {
3179 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
3180 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
3181 { .name
= NULL
, .value
= -1 },
3186 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
3187 if (n
->name
== NULL
) {
3188 LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV
[0]);
3189 return ERROR_COMMAND_SYNTAX_ERROR
;
3192 cortex_a
->isrmasking_mode
= n
->value
;
3195 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
3196 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
3201 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command
)
3203 struct target
*target
= get_current_target(CMD_CTX
);
3204 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3206 static const Jim_Nvp nvp_dacrfixup_modes
[] = {
3207 { .name
= "off", .value
= CORTEX_A_DACRFIXUP_OFF
},
3208 { .name
= "on", .value
= CORTEX_A_DACRFIXUP_ON
},
3209 { .name
= NULL
, .value
= -1 },
3214 n
= Jim_Nvp_name2value_simple(nvp_dacrfixup_modes
, CMD_ARGV
[0]);
3215 if (n
->name
== NULL
)
3216 return ERROR_COMMAND_SYNTAX_ERROR
;
3217 cortex_a
->dacrfixup_mode
= n
->value
;
3221 n
= Jim_Nvp_value2name_simple(nvp_dacrfixup_modes
, cortex_a
->dacrfixup_mode
);
3222 command_print(CMD_CTX
, "cortex_a domain access control fixup %s", n
->name
);
3227 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3229 .name
= "cache_info",
3230 .handler
= cortex_a_handle_cache_info_command
,
3231 .mode
= COMMAND_EXEC
,
3232 .help
= "display information about target caches",
3237 .handler
= cortex_a_handle_dbginit_command
,
3238 .mode
= COMMAND_EXEC
,
3239 .help
= "Initialize core debug",
3242 { .name
= "smp_off",
3243 .handler
= cortex_a_handle_smp_off_command
,
3244 .mode
= COMMAND_EXEC
,
3245 .help
= "Stop smp handling",
3249 .handler
= cortex_a_handle_smp_on_command
,
3250 .mode
= COMMAND_EXEC
,
3251 .help
= "Restart smp handling",
3256 .handler
= cortex_a_handle_smp_gdb_command
,
3257 .mode
= COMMAND_EXEC
,
3258 .help
= "display/fix current core played to gdb",
3263 .handler
= handle_cortex_a_mask_interrupts_command
,
3264 .mode
= COMMAND_ANY
,
3265 .help
= "mask cortex_a interrupts",
3266 .usage
= "['on'|'off']",
3269 .name
= "dacrfixup",
3270 .handler
= handle_cortex_a_dacrfixup_command
,
3271 .mode
= COMMAND_ANY
,
3272 .help
= "set domain access control (DACR) to all-manager "
3274 .usage
= "['on'|'off']",
3277 COMMAND_REGISTRATION_DONE
3279 static const struct command_registration cortex_a_command_handlers
[] = {
3281 .chain
= arm_command_handlers
,
3284 .chain
= armv7a_command_handlers
,
3288 .mode
= COMMAND_ANY
,
3289 .help
= "Cortex-A command group",
3291 .chain
= cortex_a_exec_command_handlers
,
3293 COMMAND_REGISTRATION_DONE
3296 struct target_type cortexa_target
= {
3298 .deprecated_name
= "cortex_a8",
3300 .poll
= cortex_a_poll
,
3301 .arch_state
= armv7a_arch_state
,
3303 .halt
= cortex_a_halt
,
3304 .resume
= cortex_a_resume
,
3305 .step
= cortex_a_step
,
3307 .assert_reset
= cortex_a_assert_reset
,
3308 .deassert_reset
= cortex_a_deassert_reset
,
3310 /* REVISIT allow exporting VFP3 registers ... */
3311 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3313 .read_memory
= cortex_a_read_memory
,
3314 .write_memory
= cortex_a_write_memory
,
3316 .read_buffer
= cortex_a_read_buffer
,
3317 .write_buffer
= cortex_a_write_buffer
,
3319 .checksum_memory
= arm_checksum_memory
,
3320 .blank_check_memory
= arm_blank_check_memory
,
3322 .run_algorithm
= armv4_5_run_algorithm
,
3324 .add_breakpoint
= cortex_a_add_breakpoint
,
3325 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3326 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3327 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3328 .add_watchpoint
= NULL
,
3329 .remove_watchpoint
= NULL
,
3331 .commands
= cortex_a_command_handlers
,
3332 .target_create
= cortex_a_target_create
,
3333 .target_jim_configure
= adiv5_jim_configure
,
3334 .init_target
= cortex_a_init_target
,
3335 .examine
= cortex_a_examine
,
3336 .deinit_target
= cortex_a_deinit_target
,
3338 .read_phys_memory
= cortex_a_read_phys_memory
,
3339 .write_phys_memory
= cortex_a_write_phys_memory
,
3340 .mmu
= cortex_a_mmu
,
3341 .virt2phys
= cortex_a_virt2phys
,
3344 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3347 .handler
= cortex_a_handle_dbginit_command
,
3348 .mode
= COMMAND_EXEC
,
3349 .help
= "Initialize core debug",
3354 .handler
= handle_cortex_a_mask_interrupts_command
,
3355 .mode
= COMMAND_EXEC
,
3356 .help
= "mask cortex_r4 interrupts",
3357 .usage
= "['on'|'off']",
3360 COMMAND_REGISTRATION_DONE
3362 static const struct command_registration cortex_r4_command_handlers
[] = {
3364 .chain
= arm_command_handlers
,
3367 .name
= "cortex_r4",
3368 .mode
= COMMAND_ANY
,
3369 .help
= "Cortex-R4 command group",
3371 .chain
= cortex_r4_exec_command_handlers
,
3373 COMMAND_REGISTRATION_DONE
3376 struct target_type cortexr4_target
= {
3377 .name
= "cortex_r4",
3379 .poll
= cortex_a_poll
,
3380 .arch_state
= armv7a_arch_state
,
3382 .halt
= cortex_a_halt
,
3383 .resume
= cortex_a_resume
,
3384 .step
= cortex_a_step
,
3386 .assert_reset
= cortex_a_assert_reset
,
3387 .deassert_reset
= cortex_a_deassert_reset
,
3389 /* REVISIT allow exporting VFP3 registers ... */
3390 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3392 .read_memory
= cortex_a_read_phys_memory
,
3393 .write_memory
= cortex_a_write_phys_memory
,
3395 .checksum_memory
= arm_checksum_memory
,
3396 .blank_check_memory
= arm_blank_check_memory
,
3398 .run_algorithm
= armv4_5_run_algorithm
,
3400 .add_breakpoint
= cortex_a_add_breakpoint
,
3401 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3402 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3403 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3404 .add_watchpoint
= NULL
,
3405 .remove_watchpoint
= NULL
,
3407 .commands
= cortex_r4_command_handlers
,
3408 .target_create
= cortex_r4_target_create
,
3409 .target_jim_configure
= adiv5_jim_configure
,
3410 .init_target
= cortex_a_init_target
,
3411 .examine
= cortex_a_examine
,
3412 .deinit_target
= cortex_a_deinit_target
,