1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex-R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
39 * Cortex-A8(tm) TRM, ARM DDI 0344H *
40 * Cortex-A9(tm) TRM, ARM DDI 0407F *
41 * Cortex-A4(tm) TRM, ARM DDI 0363E *
42 * Cortex-A15(tm)TRM, ARM DDI 0438C *
44 ***************************************************************************/
50 #include "breakpoints.h"
53 #include "target_request.h"
54 #include "target_type.h"
55 #include "arm_opcodes.h"
56 #include "arm_semihosting.h"
57 #include <helper/time_support.h>
59 static int cortex_a_poll(struct target
*target
);
60 static int cortex_a_debug_entry(struct target
*target
);
61 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
62 static int cortex_a_set_breakpoint(struct target
*target
,
63 struct breakpoint
*breakpoint
, uint8_t matchmode
);
64 static int cortex_a_set_context_breakpoint(struct target
*target
,
65 struct breakpoint
*breakpoint
, uint8_t matchmode
);
66 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
67 struct breakpoint
*breakpoint
);
68 static int cortex_a_unset_breakpoint(struct target
*target
,
69 struct breakpoint
*breakpoint
);
70 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
71 uint32_t *value
, int regnum
);
72 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
73 uint32_t value
, int regnum
);
74 static int cortex_a_mmu(struct target
*target
, int *enabled
);
75 static int cortex_a_mmu_modify(struct target
*target
, int enable
);
76 static int cortex_a_virt2phys(struct target
*target
,
77 uint32_t virt
, uint32_t *phys
);
78 static int cortex_a_read_cpu_memory(struct target
*target
,
79 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
82 /* restore cp15_control_reg at resume */
83 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
85 int retval
= ERROR_OK
;
86 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
87 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
89 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
90 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
91 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
92 retval
= armv7a
->arm
.mcr(target
, 15,
95 cortex_a
->cp15_control_reg
);
101 * Set up ARM core for memory access.
102 * If !phys_access, switch to SVC mode and make sure MMU is on
103 * If phys_access, switch off mmu
105 static int cortex_a_prep_memaccess(struct target
*target
, int phys_access
)
107 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
108 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
111 if (phys_access
== 0) {
112 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
113 cortex_a_mmu(target
, &mmu_enabled
);
115 cortex_a_mmu_modify(target
, 1);
116 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
117 /* overwrite DACR to all-manager */
118 armv7a
->arm
.mcr(target
, 15,
123 cortex_a_mmu(target
, &mmu_enabled
);
125 cortex_a_mmu_modify(target
, 0);
131 * Restore ARM core after memory access.
132 * If !phys_access, switch to previous mode
133 * If phys_access, restore MMU setting
135 static int cortex_a_post_memaccess(struct target
*target
, int phys_access
)
137 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
138 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
140 if (phys_access
== 0) {
141 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
143 armv7a
->arm
.mcr(target
, 15,
145 cortex_a
->cp15_dacr_reg
);
147 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
150 cortex_a_mmu(target
, &mmu_enabled
);
152 cortex_a_mmu_modify(target
, 1);
158 /* modify cp15_control_reg in order to enable or disable mmu for :
159 * - virt2phys address conversion
160 * - read or write memory in phys or virt address */
161 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
163 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
164 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
165 int retval
= ERROR_OK
;
169 /* if mmu enabled at target stop and mmu not enable */
170 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
171 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
174 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0) {
175 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
179 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0x1U
) {
180 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
186 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32
,
187 enable
? "enable mmu" : "disable mmu",
188 cortex_a
->cp15_control_reg_curr
);
190 retval
= armv7a
->arm
.mcr(target
, 15,
193 cortex_a
->cp15_control_reg_curr
);
199 * Cortex-A Basic debug access, very low level assumes state is saved
201 static int cortex_a_init_debug_access(struct target
*target
)
203 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
206 /* lock memory-mapped access to debug registers to prevent
207 * software interference */
208 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
209 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0);
210 if (retval
!= ERROR_OK
)
213 /* Disable cacheline fills and force cache write-through in debug state */
214 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
215 armv7a
->debug_base
+ CPUDBG_DSCCR
, 0);
216 if (retval
!= ERROR_OK
)
219 /* Disable TLB lookup and refill/eviction in debug state */
220 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
221 armv7a
->debug_base
+ CPUDBG_DSMCR
, 0);
222 if (retval
!= ERROR_OK
)
225 /* Enabling of instruction execution in debug mode is done in debug_entry code */
227 /* Resync breakpoint registers */
229 /* Since this is likely called from init or reset, update target state information*/
230 return cortex_a_poll(target
);
233 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
235 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
236 * Writes final value of DSCR into *dscr. Pass force to force always
237 * reading DSCR at least once. */
238 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
239 int64_t then
= timeval_ms();
240 while ((*dscr
& DSCR_INSTR_COMP
) == 0 || force
) {
242 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
243 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
244 if (retval
!= ERROR_OK
) {
245 LOG_ERROR("Could not read DSCR register");
248 if (timeval_ms() > then
+ 1000) {
249 LOG_ERROR("Timeout waiting for InstrCompl=1");
256 /* To reduce needless round-trips, pass in a pointer to the current
257 * DSCR value. Initialize it to zero if you just need to know the
258 * value on return from this function; or DSCR_INSTR_COMP if you
259 * happen to know that no instruction is pending.
261 static int cortex_a_exec_opcode(struct target
*target
,
262 uint32_t opcode
, uint32_t *dscr_p
)
266 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
268 dscr
= dscr_p
? *dscr_p
: 0;
270 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
272 /* Wait for InstrCompl bit to be set */
273 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
274 if (retval
!= ERROR_OK
)
277 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
278 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
279 if (retval
!= ERROR_OK
)
282 int64_t then
= timeval_ms();
284 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
285 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
286 if (retval
!= ERROR_OK
) {
287 LOG_ERROR("Could not read DSCR register");
290 if (timeval_ms() > then
+ 1000) {
291 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
294 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
302 /**************************************************************************
303 Read core register with very few exec_opcode, fast but needs work_area.
304 This can cause problems with MMU active.
305 **************************************************************************/
306 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
309 int retval
= ERROR_OK
;
310 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
312 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
313 if (retval
!= ERROR_OK
)
315 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
316 if (retval
!= ERROR_OK
)
318 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
319 if (retval
!= ERROR_OK
)
322 retval
= mem_ap_read_buf(armv7a
->memory_ap
,
323 (uint8_t *)(®file
[1]), 4, 15, address
);
328 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
329 uint32_t *value
, int regnum
)
331 int retval
= ERROR_OK
;
332 uint8_t reg
= regnum
&0xFF;
334 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
340 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
341 retval
= cortex_a_exec_opcode(target
,
342 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
344 if (retval
!= ERROR_OK
)
346 } else if (reg
== 15) {
347 /* "MOV r0, r15"; then move r0 to DCCTX */
348 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
349 if (retval
!= ERROR_OK
)
351 retval
= cortex_a_exec_opcode(target
,
352 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
354 if (retval
!= ERROR_OK
)
357 /* "MRS r0, CPSR" or "MRS r0, SPSR"
358 * then move r0 to DCCTX
360 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
361 if (retval
!= ERROR_OK
)
363 retval
= cortex_a_exec_opcode(target
,
364 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
366 if (retval
!= ERROR_OK
)
370 /* Wait for DTRRXfull then read DTRRTX */
371 int64_t then
= timeval_ms();
372 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
373 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
374 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
375 if (retval
!= ERROR_OK
)
377 if (timeval_ms() > then
+ 1000) {
378 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
383 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
384 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
385 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
390 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
391 uint32_t value
, int regnum
)
393 int retval
= ERROR_OK
;
394 uint8_t Rd
= regnum
&0xFF;
396 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
398 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
400 /* Check that DCCRX is not full */
401 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
402 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
403 if (retval
!= ERROR_OK
)
405 if (dscr
& DSCR_DTR_RX_FULL
) {
406 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
407 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
408 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
410 if (retval
!= ERROR_OK
)
417 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
418 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
419 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
420 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
421 if (retval
!= ERROR_OK
)
425 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
426 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
429 if (retval
!= ERROR_OK
)
431 } else if (Rd
== 15) {
432 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
435 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
437 if (retval
!= ERROR_OK
)
439 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
440 if (retval
!= ERROR_OK
)
443 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
444 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
446 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
448 if (retval
!= ERROR_OK
)
450 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
452 if (retval
!= ERROR_OK
)
455 /* "Prefetch flush" after modifying execution status in CPSR */
457 retval
= cortex_a_exec_opcode(target
,
458 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
460 if (retval
!= ERROR_OK
)
468 /* Write to memory mapped registers directly with no cache or mmu handling */
469 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
474 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
476 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
, address
, value
);
482 * Cortex-A implementation of Debug Programmer's Model
484 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
485 * so there's no need to poll for it before executing an instruction.
487 * NOTE that in several of these cases the "stall" mode might be useful.
488 * It'd let us queue a few operations together... prepare/finish might
489 * be the places to enable/disable that mode.
492 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
494 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
497 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
499 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
500 return mem_ap_write_u32(a
->armv7a_common
.debug_ap
,
501 a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
504 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
507 uint32_t dscr
= DSCR_INSTR_COMP
;
513 /* Wait for DTRRXfull */
514 int64_t then
= timeval_ms();
515 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
516 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
517 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
519 if (retval
!= ERROR_OK
)
521 if (timeval_ms() > then
+ 1000) {
522 LOG_ERROR("Timeout waiting for read dcc");
527 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
528 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
529 if (retval
!= ERROR_OK
)
531 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
539 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
541 struct cortex_a_common
*a
= dpm_to_a(dpm
);
545 /* set up invariant: INSTR_COMP is set after ever DPM operation */
546 int64_t then
= timeval_ms();
548 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
549 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
551 if (retval
!= ERROR_OK
)
553 if ((dscr
& DSCR_INSTR_COMP
) != 0)
555 if (timeval_ms() > then
+ 1000) {
556 LOG_ERROR("Timeout waiting for dpm prepare");
561 /* this "should never happen" ... */
562 if (dscr
& DSCR_DTR_RX_FULL
) {
563 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
565 retval
= cortex_a_exec_opcode(
566 a
->armv7a_common
.arm
.target
,
567 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
569 if (retval
!= ERROR_OK
)
576 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
578 /* REVISIT what could be done here? */
582 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
583 uint32_t opcode
, uint32_t data
)
585 struct cortex_a_common
*a
= dpm_to_a(dpm
);
587 uint32_t dscr
= DSCR_INSTR_COMP
;
589 retval
= cortex_a_write_dcc(a
, data
);
590 if (retval
!= ERROR_OK
)
593 return cortex_a_exec_opcode(
594 a
->armv7a_common
.arm
.target
,
599 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
600 uint32_t opcode
, uint32_t data
)
602 struct cortex_a_common
*a
= dpm_to_a(dpm
);
603 uint32_t dscr
= DSCR_INSTR_COMP
;
606 retval
= cortex_a_write_dcc(a
, data
);
607 if (retval
!= ERROR_OK
)
610 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
611 retval
= cortex_a_exec_opcode(
612 a
->armv7a_common
.arm
.target
,
613 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
615 if (retval
!= ERROR_OK
)
618 /* then the opcode, taking data from R0 */
619 retval
= cortex_a_exec_opcode(
620 a
->armv7a_common
.arm
.target
,
627 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
629 struct target
*target
= dpm
->arm
->target
;
630 uint32_t dscr
= DSCR_INSTR_COMP
;
632 /* "Prefetch flush" after modifying execution status in CPSR */
633 return cortex_a_exec_opcode(target
,
634 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
638 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
639 uint32_t opcode
, uint32_t *data
)
641 struct cortex_a_common
*a
= dpm_to_a(dpm
);
643 uint32_t dscr
= DSCR_INSTR_COMP
;
645 /* the opcode, writing data to DCC */
646 retval
= cortex_a_exec_opcode(
647 a
->armv7a_common
.arm
.target
,
650 if (retval
!= ERROR_OK
)
653 return cortex_a_read_dcc(a
, data
, &dscr
);
657 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
658 uint32_t opcode
, uint32_t *data
)
660 struct cortex_a_common
*a
= dpm_to_a(dpm
);
661 uint32_t dscr
= DSCR_INSTR_COMP
;
664 /* the opcode, writing data to R0 */
665 retval
= cortex_a_exec_opcode(
666 a
->armv7a_common
.arm
.target
,
669 if (retval
!= ERROR_OK
)
672 /* write R0 to DCC */
673 retval
= cortex_a_exec_opcode(
674 a
->armv7a_common
.arm
.target
,
675 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
677 if (retval
!= ERROR_OK
)
680 return cortex_a_read_dcc(a
, data
, &dscr
);
683 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
684 uint32_t addr
, uint32_t control
)
686 struct cortex_a_common
*a
= dpm_to_a(dpm
);
687 uint32_t vr
= a
->armv7a_common
.debug_base
;
688 uint32_t cr
= a
->armv7a_common
.debug_base
;
692 case 0 ... 15: /* breakpoints */
693 vr
+= CPUDBG_BVR_BASE
;
694 cr
+= CPUDBG_BCR_BASE
;
696 case 16 ... 31: /* watchpoints */
697 vr
+= CPUDBG_WVR_BASE
;
698 cr
+= CPUDBG_WCR_BASE
;
707 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
708 (unsigned) vr
, (unsigned) cr
);
710 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
712 if (retval
!= ERROR_OK
)
714 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
719 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
721 struct cortex_a_common
*a
= dpm_to_a(dpm
);
726 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
729 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
737 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
739 /* clear control register */
740 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
743 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
745 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
748 dpm
->arm
= &a
->armv7a_common
.arm
;
751 dpm
->prepare
= cortex_a_dpm_prepare
;
752 dpm
->finish
= cortex_a_dpm_finish
;
754 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
755 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
756 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
758 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
759 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
761 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
762 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
764 retval
= arm_dpm_setup(dpm
);
765 if (retval
== ERROR_OK
)
766 retval
= arm_dpm_initialize(dpm
);
770 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
772 struct target_list
*head
;
776 while (head
!= (struct target_list
*)NULL
) {
778 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
784 static int cortex_a_halt(struct target
*target
);
786 static int cortex_a_halt_smp(struct target
*target
)
789 struct target_list
*head
;
792 while (head
!= (struct target_list
*)NULL
) {
794 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
)
795 && target_was_examined(curr
))
796 retval
+= cortex_a_halt(curr
);
802 static int update_halt_gdb(struct target
*target
)
805 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
806 target
->gdb_service
->target
= target
;
807 target
->gdb_service
->core
[0] = target
->coreid
;
808 retval
+= cortex_a_halt_smp(target
);
814 * Cortex-A Run control
817 static int cortex_a_poll(struct target
*target
)
819 int retval
= ERROR_OK
;
821 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
822 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
823 enum target_state prev_target_state
= target
->state
;
824 /* toggle to another core is done by gdb as follow */
825 /* maint packet J core_id */
827 /* the next polling trigger an halt event sent to gdb */
828 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
829 (target
->gdb_service
) &&
830 (target
->gdb_service
->target
== NULL
)) {
831 target
->gdb_service
->target
=
832 get_cortex_a(target
, target
->gdb_service
->core
[1]);
833 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
836 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
837 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
838 if (retval
!= ERROR_OK
)
840 cortex_a
->cpudbg_dscr
= dscr
;
842 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
843 if (prev_target_state
!= TARGET_HALTED
) {
844 /* We have a halting debug event */
845 LOG_DEBUG("Target halted");
846 target
->state
= TARGET_HALTED
;
847 if ((prev_target_state
== TARGET_RUNNING
)
848 || (prev_target_state
== TARGET_UNKNOWN
)
849 || (prev_target_state
== TARGET_RESET
)) {
850 retval
= cortex_a_debug_entry(target
);
851 if (retval
!= ERROR_OK
)
854 retval
= update_halt_gdb(target
);
855 if (retval
!= ERROR_OK
)
859 if (arm_semihosting(target
, &retval
) != 0)
862 target_call_event_callbacks(target
,
863 TARGET_EVENT_HALTED
);
865 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
868 retval
= cortex_a_debug_entry(target
);
869 if (retval
!= ERROR_OK
)
872 retval
= update_halt_gdb(target
);
873 if (retval
!= ERROR_OK
)
877 target_call_event_callbacks(target
,
878 TARGET_EVENT_DEBUG_HALTED
);
881 } else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
882 target
->state
= TARGET_RUNNING
;
884 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
885 target
->state
= TARGET_UNKNOWN
;
891 static int cortex_a_halt(struct target
*target
)
893 int retval
= ERROR_OK
;
895 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
898 * Tell the core to be halted by writing DRCR with 0x1
899 * and then wait for the core to be halted.
901 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
902 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
903 if (retval
!= ERROR_OK
)
907 * enter halting debug mode
909 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
910 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
911 if (retval
!= ERROR_OK
)
914 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
915 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
916 if (retval
!= ERROR_OK
)
919 int64_t then
= timeval_ms();
921 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
922 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
923 if (retval
!= ERROR_OK
)
925 if ((dscr
& DSCR_CORE_HALTED
) != 0)
927 if (timeval_ms() > then
+ 1000) {
928 LOG_ERROR("Timeout waiting for halt");
933 target
->debug_reason
= DBG_REASON_DBGRQ
;
938 static int cortex_a_internal_restore(struct target
*target
, int current
,
939 uint32_t *address
, int handle_breakpoints
, int debug_execution
)
941 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
942 struct arm
*arm
= &armv7a
->arm
;
946 if (!debug_execution
)
947 target_free_all_working_areas(target
);
950 if (debug_execution
) {
951 /* Disable interrupts */
952 /* We disable interrupts in the PRIMASK register instead of
953 * masking with C_MASKINTS,
954 * This is probably the same issue as Cortex-M3 Errata 377493:
955 * C_MASKINTS in parallel with disabled interrupts can cause
956 * local faults to not be taken. */
957 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
958 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
959 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
961 /* Make sure we are in Thumb mode */
962 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
963 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
965 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
966 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
970 /* current = 1: continue on current pc, otherwise continue at <address> */
971 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
973 resume_pc
= *address
;
975 *address
= resume_pc
;
977 /* Make sure that the Armv7 gdb thumb fixups does not
978 * kill the return address
980 switch (arm
->core_state
) {
982 resume_pc
&= 0xFFFFFFFC;
984 case ARM_STATE_THUMB
:
985 case ARM_STATE_THUMB_EE
:
986 /* When the return address is loaded into PC
987 * bit 0 must be 1 to stay in Thumb state
991 case ARM_STATE_JAZELLE
:
992 LOG_ERROR("How do I resume into Jazelle state??");
995 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
996 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1000 /* restore dpm_mode at system halt */
1001 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1002 /* called it now before restoring context because it uses cpu
1003 * register r0 for restoring cp15 control register */
1004 retval
= cortex_a_restore_cp15_control_reg(target
);
1005 if (retval
!= ERROR_OK
)
1007 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1008 if (retval
!= ERROR_OK
)
1010 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1011 target
->state
= TARGET_RUNNING
;
1013 /* registers are now invalid */
1014 register_cache_invalidate(arm
->core_cache
);
1017 /* the front-end may request us not to handle breakpoints */
1018 if (handle_breakpoints
) {
1019 /* Single step past breakpoint at current address */
1020 breakpoint
= breakpoint_find(target
, resume_pc
);
1022 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1023 cortex_m3_unset_breakpoint(target
, breakpoint
);
1024 cortex_m3_single_step_core(target
);
1025 cortex_m3_set_breakpoint(target
, breakpoint
);
1033 static int cortex_a_internal_restart(struct target
*target
)
1035 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1036 struct arm
*arm
= &armv7a
->arm
;
1040 * * Restart core and wait for it to be started. Clear ITRen and sticky
1041 * * exception flags: see ARMv7 ARM, C5.9.
1043 * REVISIT: for single stepping, we probably want to
1044 * disable IRQs by default, with optional override...
1047 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1048 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1049 if (retval
!= ERROR_OK
)
1052 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1053 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1055 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1056 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1057 if (retval
!= ERROR_OK
)
1060 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1061 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1062 DRCR_CLEAR_EXCEPTIONS
);
1063 if (retval
!= ERROR_OK
)
1066 int64_t then
= timeval_ms();
1068 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1069 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1070 if (retval
!= ERROR_OK
)
1072 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1074 if (timeval_ms() > then
+ 1000) {
1075 LOG_ERROR("Timeout waiting for resume");
1080 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1081 target
->state
= TARGET_RUNNING
;
1083 /* registers are now invalid */
1084 register_cache_invalidate(arm
->core_cache
);
1089 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1092 struct target_list
*head
;
1093 struct target
*curr
;
1095 head
= target
->head
;
1096 while (head
!= (struct target_list
*)NULL
) {
1097 curr
= head
->target
;
1098 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)
1099 && target_was_examined(curr
)) {
1100 /* resume current address , not in step mode */
1101 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1102 handle_breakpoints
, 0);
1103 retval
+= cortex_a_internal_restart(curr
);
1111 static int cortex_a_resume(struct target
*target
, int current
,
1112 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1115 /* dummy resume for smp toggle in order to reduce gdb impact */
1116 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1117 /* simulate a start and halt of target */
1118 target
->gdb_service
->target
= NULL
;
1119 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1120 /* fake resume at next poll we play the target core[1], see poll*/
1121 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1124 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1126 target
->gdb_service
->core
[0] = -1;
1127 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1128 if (retval
!= ERROR_OK
)
1131 cortex_a_internal_restart(target
);
1133 if (!debug_execution
) {
1134 target
->state
= TARGET_RUNNING
;
1135 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1136 LOG_DEBUG("target resumed at 0x%" PRIx32
, address
);
1138 target
->state
= TARGET_DEBUG_RUNNING
;
1139 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1140 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, address
);
1146 static int cortex_a_debug_entry(struct target
*target
)
1149 uint32_t regfile
[16], cpsr
, spsr
, dscr
;
1150 int retval
= ERROR_OK
;
1151 struct working_area
*regfile_working_area
= NULL
;
1152 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1153 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1154 struct arm
*arm
= &armv7a
->arm
;
1157 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1159 /* REVISIT surely we should not re-read DSCR !! */
1160 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1161 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1162 if (retval
!= ERROR_OK
)
1165 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1166 * imprecise data aborts get discarded by issuing a Data
1167 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1170 /* Enable the ITR execution once we are in debug mode */
1171 dscr
|= DSCR_ITR_EN
;
1172 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1173 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1174 if (retval
!= ERROR_OK
)
1177 /* Examine debug reason */
1178 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1180 /* save address of instruction that triggered the watchpoint? */
1181 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1184 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1185 armv7a
->debug_base
+ CPUDBG_WFAR
,
1187 if (retval
!= ERROR_OK
)
1189 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1192 /* REVISIT fast_reg_read is never set ... */
1194 /* Examine target state and mode */
1195 if (cortex_a
->fast_reg_read
)
1196 target_alloc_working_area(target
, 64, ®file_working_area
);
1199 /* First load register acessible through core debug port*/
1200 if (!regfile_working_area
)
1201 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1203 retval
= cortex_a_read_regs_through_mem(target
,
1204 regfile_working_area
->address
, regfile
);
1206 target_free_working_area(target
, regfile_working_area
);
1207 if (retval
!= ERROR_OK
)
1210 /* read Current PSR */
1211 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1212 /* store current cpsr */
1213 if (retval
!= ERROR_OK
)
1216 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1218 arm_set_cpsr(arm
, cpsr
);
1221 for (i
= 0; i
<= ARM_PC
; i
++) {
1222 reg
= arm_reg_current(arm
, i
);
1224 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1229 /* Fixup PC Resume Address */
1230 if (cpsr
& (1 << 5)) {
1231 /* T bit set for Thumb or ThumbEE state */
1232 regfile
[ARM_PC
] -= 4;
1235 regfile
[ARM_PC
] -= 8;
1239 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1240 reg
->dirty
= reg
->valid
;
1243 /* read Saved PSR */
1244 retval
= cortex_a_dap_read_coreregister_u32(target
, &spsr
, 17);
1245 /* store current spsr */
1246 if (retval
!= ERROR_OK
)
1250 buf_set_u32(reg
->value
, 0, 32, spsr
);
1255 /* TODO, Move this */
1256 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1257 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1258 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1260 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1261 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1263 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1264 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1267 /* Are we in an exception handler */
1268 /* armv4_5->exception_number = 0; */
1269 if (armv7a
->post_debug_entry
) {
1270 retval
= armv7a
->post_debug_entry(target
);
1271 if (retval
!= ERROR_OK
)
1278 static int cortex_a_post_debug_entry(struct target
*target
)
1280 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1281 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1284 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1285 retval
= armv7a
->arm
.mrc(target
, 15,
1286 0, 0, /* op1, op2 */
1287 1, 0, /* CRn, CRm */
1288 &cortex_a
->cp15_control_reg
);
1289 if (retval
!= ERROR_OK
)
1291 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1292 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1294 if (armv7a
->armv7a_mmu
.armv7a_cache
.info
== -1)
1295 armv7a_identify_cache(target
);
1297 if (armv7a
->is_armv7r
) {
1298 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1300 armv7a
->armv7a_mmu
.mmu_enabled
=
1301 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1303 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1304 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1305 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1306 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1307 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1309 /* switch to SVC mode to read DACR */
1310 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
1311 armv7a
->arm
.mrc(target
, 15,
1313 &cortex_a
->cp15_dacr_reg
);
1315 LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32
,
1316 cortex_a
->cp15_dacr_reg
);
1318 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1322 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1324 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1328 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1329 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1330 if (ERROR_OK
!= retval
)
1333 /* clear bitfield */
1336 dscr
|= value
& bit_mask
;
1338 /* write new DSCR */
1339 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1340 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1344 static int cortex_a_step(struct target
*target
, int current
, uint32_t address
,
1345 int handle_breakpoints
)
1347 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1348 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1349 struct arm
*arm
= &armv7a
->arm
;
1350 struct breakpoint
*breakpoint
= NULL
;
1351 struct breakpoint stepbreakpoint
;
1355 if (target
->state
!= TARGET_HALTED
) {
1356 LOG_WARNING("target not halted");
1357 return ERROR_TARGET_NOT_HALTED
;
1360 /* current = 1: continue on current pc, otherwise continue at <address> */
1363 buf_set_u32(r
->value
, 0, 32, address
);
1365 address
= buf_get_u32(r
->value
, 0, 32);
1367 /* The front-end may request us not to handle breakpoints.
1368 * But since Cortex-A uses breakpoint for single step,
1369 * we MUST handle breakpoints.
1371 handle_breakpoints
= 1;
1372 if (handle_breakpoints
) {
1373 breakpoint
= breakpoint_find(target
, address
);
1375 cortex_a_unset_breakpoint(target
, breakpoint
);
1378 /* Setup single step breakpoint */
1379 stepbreakpoint
.address
= address
;
1380 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1382 stepbreakpoint
.type
= BKPT_HARD
;
1383 stepbreakpoint
.set
= 0;
1385 /* Disable interrupts during single step if requested */
1386 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1387 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1388 if (ERROR_OK
!= retval
)
1392 /* Break on IVA mismatch */
1393 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1395 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1397 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1398 if (retval
!= ERROR_OK
)
1401 int64_t then
= timeval_ms();
1402 while (target
->state
!= TARGET_HALTED
) {
1403 retval
= cortex_a_poll(target
);
1404 if (retval
!= ERROR_OK
)
1406 if (timeval_ms() > then
+ 1000) {
1407 LOG_ERROR("timeout waiting for target halt");
1412 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1414 /* Re-enable interrupts if they were disabled */
1415 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1416 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1417 if (ERROR_OK
!= retval
)
1422 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1425 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1427 if (target
->state
!= TARGET_HALTED
)
1428 LOG_DEBUG("target stepped");
1433 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1435 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1439 if (armv7a
->pre_restore_context
)
1440 armv7a
->pre_restore_context(target
);
1442 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1446 * Cortex-A Breakpoint and watchpoint functions
1449 /* Setup hardware Breakpoint Register Pair */
1450 static int cortex_a_set_breakpoint(struct target
*target
,
1451 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1456 uint8_t byte_addr_select
= 0x0F;
1457 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1458 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1459 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1461 if (breakpoint
->set
) {
1462 LOG_WARNING("breakpoint already set");
1466 if (breakpoint
->type
== BKPT_HARD
) {
1467 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1469 if (brp_i
>= cortex_a
->brp_num
) {
1470 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1473 breakpoint
->set
= brp_i
+ 1;
1474 if (breakpoint
->length
== 2)
1475 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1476 control
= ((matchmode
& 0x7) << 20)
1477 | (byte_addr_select
<< 5)
1479 brp_list
[brp_i
].used
= 1;
1480 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1481 brp_list
[brp_i
].control
= control
;
1482 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1483 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1484 brp_list
[brp_i
].value
);
1485 if (retval
!= ERROR_OK
)
1487 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1488 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1489 brp_list
[brp_i
].control
);
1490 if (retval
!= ERROR_OK
)
1492 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1493 brp_list
[brp_i
].control
,
1494 brp_list
[brp_i
].value
);
1495 } else if (breakpoint
->type
== BKPT_SOFT
) {
1497 if (breakpoint
->length
== 2)
1498 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1500 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1501 retval
= target_read_memory(target
,
1502 breakpoint
->address
& 0xFFFFFFFE,
1503 breakpoint
->length
, 1,
1504 breakpoint
->orig_instr
);
1505 if (retval
!= ERROR_OK
)
1508 /* make sure data cache is cleaned & invalidated down to PoC */
1509 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1510 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1511 breakpoint
->length
);
1514 retval
= target_write_memory(target
,
1515 breakpoint
->address
& 0xFFFFFFFE,
1516 breakpoint
->length
, 1, code
);
1517 if (retval
!= ERROR_OK
)
1520 /* update i-cache at breakpoint location */
1521 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1522 breakpoint
->length
);
1523 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1524 breakpoint
->length
);
1526 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1532 static int cortex_a_set_context_breakpoint(struct target
*target
,
1533 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1535 int retval
= ERROR_FAIL
;
1538 uint8_t byte_addr_select
= 0x0F;
1539 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1540 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1541 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1543 if (breakpoint
->set
) {
1544 LOG_WARNING("breakpoint already set");
1547 /*check available context BRPs*/
1548 while ((brp_list
[brp_i
].used
||
1549 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1552 if (brp_i
>= cortex_a
->brp_num
) {
1553 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1557 breakpoint
->set
= brp_i
+ 1;
1558 control
= ((matchmode
& 0x7) << 20)
1559 | (byte_addr_select
<< 5)
1561 brp_list
[brp_i
].used
= 1;
1562 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1563 brp_list
[brp_i
].control
= control
;
1564 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1565 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1566 brp_list
[brp_i
].value
);
1567 if (retval
!= ERROR_OK
)
1569 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1570 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1571 brp_list
[brp_i
].control
);
1572 if (retval
!= ERROR_OK
)
1574 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1575 brp_list
[brp_i
].control
,
1576 brp_list
[brp_i
].value
);
1581 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1583 int retval
= ERROR_FAIL
;
1584 int brp_1
= 0; /* holds the contextID pair */
1585 int brp_2
= 0; /* holds the IVA pair */
1586 uint32_t control_CTX
, control_IVA
;
1587 uint8_t CTX_byte_addr_select
= 0x0F;
1588 uint8_t IVA_byte_addr_select
= 0x0F;
1589 uint8_t CTX_machmode
= 0x03;
1590 uint8_t IVA_machmode
= 0x01;
1591 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1592 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1593 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1595 if (breakpoint
->set
) {
1596 LOG_WARNING("breakpoint already set");
1599 /*check available context BRPs*/
1600 while ((brp_list
[brp_1
].used
||
1601 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1604 printf("brp(CTX) found num: %d\n", brp_1
);
1605 if (brp_1
>= cortex_a
->brp_num
) {
1606 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1610 while ((brp_list
[brp_2
].used
||
1611 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1614 printf("brp(IVA) found num: %d\n", brp_2
);
1615 if (brp_2
>= cortex_a
->brp_num
) {
1616 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1620 breakpoint
->set
= brp_1
+ 1;
1621 breakpoint
->linked_BRP
= brp_2
;
1622 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1625 | (CTX_byte_addr_select
<< 5)
1627 brp_list
[brp_1
].used
= 1;
1628 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1629 brp_list
[brp_1
].control
= control_CTX
;
1630 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1631 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1632 brp_list
[brp_1
].value
);
1633 if (retval
!= ERROR_OK
)
1635 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1636 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1637 brp_list
[brp_1
].control
);
1638 if (retval
!= ERROR_OK
)
1641 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1643 | (IVA_byte_addr_select
<< 5)
1645 brp_list
[brp_2
].used
= 1;
1646 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1647 brp_list
[brp_2
].control
= control_IVA
;
1648 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1649 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1650 brp_list
[brp_2
].value
);
1651 if (retval
!= ERROR_OK
)
1653 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1654 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1655 brp_list
[brp_2
].control
);
1656 if (retval
!= ERROR_OK
)
1662 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1665 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1666 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1667 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1669 if (!breakpoint
->set
) {
1670 LOG_WARNING("breakpoint not set");
1674 if (breakpoint
->type
== BKPT_HARD
) {
1675 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1676 int brp_i
= breakpoint
->set
- 1;
1677 int brp_j
= breakpoint
->linked_BRP
;
1678 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1679 LOG_DEBUG("Invalid BRP number in breakpoint");
1682 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1683 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1684 brp_list
[brp_i
].used
= 0;
1685 brp_list
[brp_i
].value
= 0;
1686 brp_list
[brp_i
].control
= 0;
1687 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1688 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1689 brp_list
[brp_i
].control
);
1690 if (retval
!= ERROR_OK
)
1692 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1693 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1694 brp_list
[brp_i
].value
);
1695 if (retval
!= ERROR_OK
)
1697 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1698 LOG_DEBUG("Invalid BRP number in breakpoint");
1701 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1702 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1703 brp_list
[brp_j
].used
= 0;
1704 brp_list
[brp_j
].value
= 0;
1705 brp_list
[brp_j
].control
= 0;
1706 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1707 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1708 brp_list
[brp_j
].control
);
1709 if (retval
!= ERROR_OK
)
1711 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1712 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1713 brp_list
[brp_j
].value
);
1714 if (retval
!= ERROR_OK
)
1716 breakpoint
->linked_BRP
= 0;
1717 breakpoint
->set
= 0;
1721 int brp_i
= breakpoint
->set
- 1;
1722 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1723 LOG_DEBUG("Invalid BRP number in breakpoint");
1726 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1727 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1728 brp_list
[brp_i
].used
= 0;
1729 brp_list
[brp_i
].value
= 0;
1730 brp_list
[brp_i
].control
= 0;
1731 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1732 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1733 brp_list
[brp_i
].control
);
1734 if (retval
!= ERROR_OK
)
1736 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1737 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1738 brp_list
[brp_i
].value
);
1739 if (retval
!= ERROR_OK
)
1741 breakpoint
->set
= 0;
1746 /* make sure data cache is cleaned & invalidated down to PoC */
1747 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1748 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1749 breakpoint
->length
);
1752 /* restore original instruction (kept in target endianness) */
1753 if (breakpoint
->length
== 4) {
1754 retval
= target_write_memory(target
,
1755 breakpoint
->address
& 0xFFFFFFFE,
1756 4, 1, breakpoint
->orig_instr
);
1757 if (retval
!= ERROR_OK
)
1760 retval
= target_write_memory(target
,
1761 breakpoint
->address
& 0xFFFFFFFE,
1762 2, 1, breakpoint
->orig_instr
);
1763 if (retval
!= ERROR_OK
)
1767 /* update i-cache at breakpoint location */
1768 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1769 breakpoint
->length
);
1770 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1771 breakpoint
->length
);
1773 breakpoint
->set
= 0;
1778 static int cortex_a_add_breakpoint(struct target
*target
,
1779 struct breakpoint
*breakpoint
)
1781 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1783 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1784 LOG_INFO("no hardware breakpoint available");
1785 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1788 if (breakpoint
->type
== BKPT_HARD
)
1789 cortex_a
->brp_num_available
--;
1791 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1794 static int cortex_a_add_context_breakpoint(struct target
*target
,
1795 struct breakpoint
*breakpoint
)
1797 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1799 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1800 LOG_INFO("no hardware breakpoint available");
1801 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1804 if (breakpoint
->type
== BKPT_HARD
)
1805 cortex_a
->brp_num_available
--;
1807 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1810 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1811 struct breakpoint
*breakpoint
)
1813 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1815 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1816 LOG_INFO("no hardware breakpoint available");
1817 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1820 if (breakpoint
->type
== BKPT_HARD
)
1821 cortex_a
->brp_num_available
--;
1823 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1827 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1829 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1832 /* It is perfectly possible to remove breakpoints while the target is running */
1833 if (target
->state
!= TARGET_HALTED
) {
1834 LOG_WARNING("target not halted");
1835 return ERROR_TARGET_NOT_HALTED
;
1839 if (breakpoint
->set
) {
1840 cortex_a_unset_breakpoint(target
, breakpoint
);
1841 if (breakpoint
->type
== BKPT_HARD
)
1842 cortex_a
->brp_num_available
++;
1850 * Cortex-A Reset functions
1853 static int cortex_a_assert_reset(struct target
*target
)
1855 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1859 /* FIXME when halt is requested, make it work somehow... */
1861 /* This function can be called in "target not examined" state */
1863 /* Issue some kind of warm reset. */
1864 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1865 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1866 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1867 /* REVISIT handle "pulls" cases, if there's
1868 * hardware that needs them to work.
1870 if (target
->reset_halt
)
1871 if (jtag_get_reset_config() & RESET_SRST_NO_GATING
)
1872 jtag_add_reset(0, 1);
1874 LOG_ERROR("%s: how to reset?", target_name(target
));
1878 /* registers are now invalid */
1879 if (target_was_examined(target
))
1880 register_cache_invalidate(armv7a
->arm
.core_cache
);
1882 target
->state
= TARGET_RESET
;
1887 static int cortex_a_deassert_reset(struct target
*target
)
1893 /* be certain SRST is off */
1894 jtag_add_reset(0, 0);
1896 if (target_was_examined(target
)) {
1897 retval
= cortex_a_poll(target
);
1898 if (retval
!= ERROR_OK
)
1902 if (target
->reset_halt
) {
1903 if (target
->state
!= TARGET_HALTED
) {
1904 LOG_WARNING("%s: ran after reset and before halt ...",
1905 target_name(target
));
1906 if (target_was_examined(target
)) {
1907 retval
= target_halt(target
);
1908 if (retval
!= ERROR_OK
)
1911 target
->state
= TARGET_UNKNOWN
;
1918 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1920 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1921 * New desired mode must be in mode. Current value of DSCR must be in
1922 * *dscr, which is updated with new value.
1924 * This function elides actually sending the mode-change over the debug
1925 * interface if the mode is already set as desired.
1927 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1928 if (new_dscr
!= *dscr
) {
1929 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1930 int retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1931 armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1932 if (retval
== ERROR_OK
)
1940 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
1941 uint32_t value
, uint32_t *dscr
)
1943 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1944 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1945 int64_t then
= timeval_ms();
1948 while ((*dscr
& mask
) != value
) {
1949 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1950 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1951 if (retval
!= ERROR_OK
)
1953 if (timeval_ms() > then
+ 1000) {
1954 LOG_ERROR("timeout waiting for DSCR bit change");
1961 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
1962 uint32_t *data
, uint32_t *dscr
)
1965 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1967 /* Move from coprocessor to R0. */
1968 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1969 if (retval
!= ERROR_OK
)
1972 /* Move from R0 to DTRTX. */
1973 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
1974 if (retval
!= ERROR_OK
)
1977 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
1978 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1979 * must also check TXfull_l). Most of the time this will be free
1980 * because TXfull_l will be set immediately and cached in dscr. */
1981 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
1982 DSCR_DTRTX_FULL_LATCHED
, dscr
);
1983 if (retval
!= ERROR_OK
)
1986 /* Read the value transferred to DTRTX. */
1987 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1988 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
1989 if (retval
!= ERROR_OK
)
1995 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
1996 uint32_t *dfsr
, uint32_t *dscr
)
2001 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2002 if (retval
!= ERROR_OK
)
2007 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2008 if (retval
!= ERROR_OK
)
2015 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
2016 uint32_t data
, uint32_t *dscr
)
2019 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2021 /* Write the value into DTRRX. */
2022 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2023 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2024 if (retval
!= ERROR_OK
)
2027 /* Move from DTRRX to R0. */
2028 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
2029 if (retval
!= ERROR_OK
)
2032 /* Move from R0 to coprocessor. */
2033 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2034 if (retval
!= ERROR_OK
)
2037 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2038 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2039 * check RXfull_l). Most of the time this will be free because RXfull_l
2040 * will be cleared immediately and cached in dscr. */
2041 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2042 if (retval
!= ERROR_OK
)
2048 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
2049 uint32_t dfsr
, uint32_t *dscr
)
2053 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2054 if (retval
!= ERROR_OK
)
2057 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2058 if (retval
!= ERROR_OK
)
2064 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
2066 uint32_t status
, upper4
;
2068 if (dfsr
& (1 << 9)) {
2070 status
= dfsr
& 0x3f;
2071 upper4
= status
>> 2;
2072 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
2073 return ERROR_TARGET_TRANSLATION_FAULT
;
2074 else if (status
== 33)
2075 return ERROR_TARGET_UNALIGNED_ACCESS
;
2077 return ERROR_TARGET_DATA_ABORT
;
2079 /* Normal format. */
2080 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
2082 return ERROR_TARGET_UNALIGNED_ACCESS
;
2083 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
2084 status
== 9 || status
== 11 || status
== 13 || status
== 15)
2085 return ERROR_TARGET_TRANSLATION_FAULT
;
2087 return ERROR_TARGET_DATA_ABORT
;
2091 static int cortex_a_write_cpu_memory_slow(struct target
*target
,
2092 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2094 /* Writes count objects of size size from *buffer. Old value of DSCR must
2095 * be in *dscr; updated to new value. This is slow because it works for
2096 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2097 * the address is aligned, cortex_a_write_cpu_memory_fast should be
2100 * - Address is in R0.
2101 * - R0 is marked dirty.
2103 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2104 struct arm
*arm
= &armv7a
->arm
;
2107 /* Mark register R1 as dirty, to use for transferring data. */
2108 arm_reg_current(arm
, 1)->dirty
= true;
2110 /* Switch to non-blocking mode if not already in that mode. */
2111 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2112 if (retval
!= ERROR_OK
)
2115 /* Go through the objects. */
2117 /* Write the value to store into DTRRX. */
2118 uint32_t data
, opcode
;
2122 data
= target_buffer_get_u16(target
, buffer
);
2124 data
= target_buffer_get_u32(target
, buffer
);
2125 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2126 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2127 if (retval
!= ERROR_OK
)
2130 /* Transfer the value from DTRRX to R1. */
2131 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
2132 if (retval
!= ERROR_OK
)
2135 /* Write the value transferred to R1 into memory. */
2137 opcode
= ARMV4_5_STRB_IP(1, 0);
2139 opcode
= ARMV4_5_STRH_IP(1, 0);
2141 opcode
= ARMV4_5_STRW_IP(1, 0);
2142 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2143 if (retval
!= ERROR_OK
)
2146 /* Check for faults and return early. */
2147 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2148 return ERROR_OK
; /* A data fault is not considered a system failure. */
2150 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2151 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2152 * must also check RXfull_l). Most of the time this will be free
2153 * because RXfull_l will be cleared immediately and cached in dscr. */
2154 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2155 if (retval
!= ERROR_OK
)
2166 static int cortex_a_write_cpu_memory_fast(struct target
*target
,
2167 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2169 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2170 * in *dscr; updated to new value. This is fast but only works for
2171 * word-sized objects at aligned addresses.
2173 * - Address is in R0 and must be a multiple of 4.
2174 * - R0 is marked dirty.
2176 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2179 /* Switch to fast mode if not already in that mode. */
2180 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2181 if (retval
!= ERROR_OK
)
2184 /* Latch STC instruction. */
2185 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2186 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2187 if (retval
!= ERROR_OK
)
2190 /* Transfer all the data and issue all the instructions. */
2191 return mem_ap_write_buf_noincr(armv7a
->debug_ap
, buffer
,
2192 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
2195 static int cortex_a_write_cpu_memory(struct target
*target
,
2196 uint32_t address
, uint32_t size
,
2197 uint32_t count
, const uint8_t *buffer
)
2199 /* Write memory through the CPU. */
2200 int retval
, final_retval
;
2201 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2202 struct arm
*arm
= &armv7a
->arm
;
2203 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2205 LOG_DEBUG("Writing CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2206 address
, size
, count
);
2207 if (target
->state
!= TARGET_HALTED
) {
2208 LOG_WARNING("target not halted");
2209 return ERROR_TARGET_NOT_HALTED
;
2215 /* Clear any abort. */
2216 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2217 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2218 if (retval
!= ERROR_OK
)
2222 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2223 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2224 if (retval
!= ERROR_OK
)
2227 /* Switch to non-blocking mode if not already in that mode. */
2228 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2229 if (retval
!= ERROR_OK
)
2232 /* Mark R0 as dirty. */
2233 arm_reg_current(arm
, 0)->dirty
= true;
2235 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2236 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2237 if (retval
!= ERROR_OK
)
2240 /* Get the memory address into R0. */
2241 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2242 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2243 if (retval
!= ERROR_OK
)
2245 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2246 if (retval
!= ERROR_OK
)
2249 if (size
== 4 && (address
% 4) == 0) {
2250 /* We are doing a word-aligned transfer, so use fast mode. */
2251 retval
= cortex_a_write_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2253 /* Use slow path. */
2254 retval
= cortex_a_write_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2258 final_retval
= retval
;
2260 /* Switch to non-blocking mode if not already in that mode. */
2261 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2262 if (final_retval
== ERROR_OK
)
2263 final_retval
= retval
;
2265 /* Wait for last issued instruction to complete. */
2266 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2267 if (final_retval
== ERROR_OK
)
2268 final_retval
= retval
;
2270 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2271 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2272 * check RXfull_l). Most of the time this will be free because RXfull_l
2273 * will be cleared immediately and cached in dscr. However, don't do this
2274 * if there is fault, because then the instruction might not have completed
2276 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2277 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2278 if (retval
!= ERROR_OK
)
2282 /* If there were any sticky abort flags, clear them. */
2283 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2285 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2286 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2287 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2292 /* Handle synchronous data faults. */
2293 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2294 if (final_retval
== ERROR_OK
) {
2295 /* Final return value will reflect cause of fault. */
2296 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2297 if (retval
== ERROR_OK
) {
2298 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2299 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2301 final_retval
= retval
;
2303 /* Fault destroyed DFAR/DFSR; restore them. */
2304 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2305 if (retval
!= ERROR_OK
)
2306 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2309 /* Handle asynchronous data faults. */
2310 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2311 if (final_retval
== ERROR_OK
)
2312 /* No other error has been recorded so far, so keep this one. */
2313 final_retval
= ERROR_TARGET_DATA_ABORT
;
2316 /* If the DCC is nonempty, clear it. */
2317 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2319 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2320 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2321 if (final_retval
== ERROR_OK
)
2322 final_retval
= retval
;
2324 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2325 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2326 if (final_retval
== ERROR_OK
)
2327 final_retval
= retval
;
2331 return final_retval
;
2334 static int cortex_a_read_cpu_memory_slow(struct target
*target
,
2335 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2337 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2338 * in *dscr; updated to new value. This is slow because it works for
2339 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2340 * the address is aligned, cortex_a_read_cpu_memory_fast should be
2343 * - Address is in R0.
2344 * - R0 is marked dirty.
2346 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2347 struct arm
*arm
= &armv7a
->arm
;
2350 /* Mark register R1 as dirty, to use for transferring data. */
2351 arm_reg_current(arm
, 1)->dirty
= true;
2353 /* Switch to non-blocking mode if not already in that mode. */
2354 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2355 if (retval
!= ERROR_OK
)
2358 /* Go through the objects. */
2360 /* Issue a load of the appropriate size to R1. */
2361 uint32_t opcode
, data
;
2363 opcode
= ARMV4_5_LDRB_IP(1, 0);
2365 opcode
= ARMV4_5_LDRH_IP(1, 0);
2367 opcode
= ARMV4_5_LDRW_IP(1, 0);
2368 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2369 if (retval
!= ERROR_OK
)
2372 /* Issue a write of R1 to DTRTX. */
2373 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2374 if (retval
!= ERROR_OK
)
2377 /* Check for faults and return early. */
2378 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2379 return ERROR_OK
; /* A data fault is not considered a system failure. */
2381 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2382 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2383 * must also check TXfull_l). Most of the time this will be free
2384 * because TXfull_l will be set immediately and cached in dscr. */
2385 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2386 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2387 if (retval
!= ERROR_OK
)
2390 /* Read the value transferred to DTRTX into the buffer. */
2391 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2392 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2393 if (retval
!= ERROR_OK
)
2396 *buffer
= (uint8_t) data
;
2398 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2400 target_buffer_set_u32(target
, buffer
, data
);
2410 static int cortex_a_read_cpu_memory_fast(struct target
*target
,
2411 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2413 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2414 * *dscr; updated to new value. This is fast but only works for word-sized
2415 * objects at aligned addresses.
2417 * - Address is in R0 and must be a multiple of 4.
2418 * - R0 is marked dirty.
2420 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2424 /* Switch to non-blocking mode if not already in that mode. */
2425 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2426 if (retval
!= ERROR_OK
)
2429 /* Issue the LDC instruction via a write to ITR. */
2430 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2431 if (retval
!= ERROR_OK
)
2437 /* Switch to fast mode if not already in that mode. */
2438 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2439 if (retval
!= ERROR_OK
)
2442 /* Latch LDC instruction. */
2443 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2444 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2445 if (retval
!= ERROR_OK
)
2448 /* Read the value transferred to DTRTX into the buffer. Due to fast
2449 * mode rules, this blocks until the instruction finishes executing and
2450 * then reissues the read instruction to read the next word from
2451 * memory. The last read of DTRTX in this call reads the second-to-last
2452 * word from memory and issues the read instruction for the last word.
2454 retval
= mem_ap_read_buf_noincr(armv7a
->debug_ap
, buffer
,
2455 4, count
, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2456 if (retval
!= ERROR_OK
)
2460 buffer
+= count
* 4;
2463 /* Wait for last issued instruction to complete. */
2464 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2465 if (retval
!= ERROR_OK
)
2468 /* Switch to non-blocking mode if not already in that mode. */
2469 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2470 if (retval
!= ERROR_OK
)
2473 /* Check for faults and return early. */
2474 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2475 return ERROR_OK
; /* A data fault is not considered a system failure. */
2477 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2478 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2479 * check TXfull_l). Most of the time this will be free because TXfull_l
2480 * will be set immediately and cached in dscr. */
2481 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2482 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2483 if (retval
!= ERROR_OK
)
2486 /* Read the value transferred to DTRTX into the buffer. This is the last
2488 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2489 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2490 if (retval
!= ERROR_OK
)
2492 target_buffer_set_u32(target
, buffer
, u32
);
2497 static int cortex_a_read_cpu_memory(struct target
*target
,
2498 uint32_t address
, uint32_t size
,
2499 uint32_t count
, uint8_t *buffer
)
2501 /* Read memory through the CPU. */
2502 int retval
, final_retval
;
2503 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2504 struct arm
*arm
= &armv7a
->arm
;
2505 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2507 LOG_DEBUG("Reading CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2508 address
, size
, count
);
2509 if (target
->state
!= TARGET_HALTED
) {
2510 LOG_WARNING("target not halted");
2511 return ERROR_TARGET_NOT_HALTED
;
2517 /* Clear any abort. */
2518 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2519 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2520 if (retval
!= ERROR_OK
)
2524 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2525 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2526 if (retval
!= ERROR_OK
)
2529 /* Switch to non-blocking mode if not already in that mode. */
2530 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2531 if (retval
!= ERROR_OK
)
2534 /* Mark R0 as dirty. */
2535 arm_reg_current(arm
, 0)->dirty
= true;
2537 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2538 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2539 if (retval
!= ERROR_OK
)
2542 /* Get the memory address into R0. */
2543 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2544 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2545 if (retval
!= ERROR_OK
)
2547 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2548 if (retval
!= ERROR_OK
)
2551 if (size
== 4 && (address
% 4) == 0) {
2552 /* We are doing a word-aligned transfer, so use fast mode. */
2553 retval
= cortex_a_read_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2555 /* Use slow path. */
2556 retval
= cortex_a_read_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2560 final_retval
= retval
;
2562 /* Switch to non-blocking mode if not already in that mode. */
2563 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2564 if (final_retval
== ERROR_OK
)
2565 final_retval
= retval
;
2567 /* Wait for last issued instruction to complete. */
2568 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2569 if (final_retval
== ERROR_OK
)
2570 final_retval
= retval
;
2572 /* If there were any sticky abort flags, clear them. */
2573 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2575 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2576 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2577 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2582 /* Handle synchronous data faults. */
2583 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2584 if (final_retval
== ERROR_OK
) {
2585 /* Final return value will reflect cause of fault. */
2586 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2587 if (retval
== ERROR_OK
) {
2588 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2589 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2591 final_retval
= retval
;
2593 /* Fault destroyed DFAR/DFSR; restore them. */
2594 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2595 if (retval
!= ERROR_OK
)
2596 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2599 /* Handle asynchronous data faults. */
2600 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2601 if (final_retval
== ERROR_OK
)
2602 /* No other error has been recorded so far, so keep this one. */
2603 final_retval
= ERROR_TARGET_DATA_ABORT
;
2606 /* If the DCC is nonempty, clear it. */
2607 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2609 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2610 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2611 if (final_retval
== ERROR_OK
)
2612 final_retval
= retval
;
2614 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2615 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2616 if (final_retval
== ERROR_OK
)
2617 final_retval
= retval
;
2621 return final_retval
;
2626 * Cortex-A Memory access
2628 * This is same Cortex-M3 but we must also use the correct
2629 * ap number for every access.
2632 static int cortex_a_read_phys_memory(struct target
*target
,
2633 uint32_t address
, uint32_t size
,
2634 uint32_t count
, uint8_t *buffer
)
2636 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2637 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2638 uint8_t apsel
= swjdp
->apsel
;
2641 if (!count
|| !buffer
)
2642 return ERROR_COMMAND_SYNTAX_ERROR
;
2644 LOG_DEBUG("Reading memory at real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
,
2645 address
, size
, count
);
2647 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2648 return mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2650 /* read memory through the CPU */
2651 cortex_a_prep_memaccess(target
, 1);
2652 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2653 cortex_a_post_memaccess(target
, 1);
2658 static int cortex_a_read_memory(struct target
*target
, uint32_t address
,
2659 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2663 /* cortex_a handles unaligned memory access */
2664 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2667 cortex_a_prep_memaccess(target
, 0);
2668 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2669 cortex_a_post_memaccess(target
, 0);
2674 static int cortex_a_read_memory_ahb(struct target
*target
, uint32_t address
,
2675 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2677 int mmu_enabled
= 0;
2678 uint32_t virt
, phys
;
2680 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2681 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2682 uint8_t apsel
= swjdp
->apsel
;
2684 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2685 return target_read_memory(target
, address
, size
, count
, buffer
);
2687 /* cortex_a handles unaligned memory access */
2688 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2691 /* determine if MMU was enabled on target stop */
2692 if (!armv7a
->is_armv7r
) {
2693 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2694 if (retval
!= ERROR_OK
)
2700 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2701 if (retval
!= ERROR_OK
)
2704 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2709 if (!count
|| !buffer
)
2710 return ERROR_COMMAND_SYNTAX_ERROR
;
2712 retval
= mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2717 static int cortex_a_write_phys_memory(struct target
*target
,
2718 uint32_t address
, uint32_t size
,
2719 uint32_t count
, const uint8_t *buffer
)
2721 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2722 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2723 uint8_t apsel
= swjdp
->apsel
;
2726 if (!count
|| !buffer
)
2727 return ERROR_COMMAND_SYNTAX_ERROR
;
2729 LOG_DEBUG("Writing memory to real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2732 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2733 return mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2735 /* write memory through the CPU */
2736 cortex_a_prep_memaccess(target
, 1);
2737 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2738 cortex_a_post_memaccess(target
, 1);
2743 static int cortex_a_write_memory(struct target
*target
, uint32_t address
,
2744 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2748 /* cortex_a handles unaligned memory access */
2749 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2752 /* memory writes bypass the caches, must flush before writing */
2753 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2755 cortex_a_prep_memaccess(target
, 0);
2756 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2757 cortex_a_post_memaccess(target
, 0);
2761 static int cortex_a_write_memory_ahb(struct target
*target
, uint32_t address
,
2762 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2764 int mmu_enabled
= 0;
2765 uint32_t virt
, phys
;
2767 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2768 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2769 uint8_t apsel
= swjdp
->apsel
;
2771 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2772 return target_write_memory(target
, address
, size
, count
, buffer
);
2774 /* cortex_a handles unaligned memory access */
2775 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2778 /* determine if MMU was enabled on target stop */
2779 if (!armv7a
->is_armv7r
) {
2780 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2781 if (retval
!= ERROR_OK
)
2787 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2788 if (retval
!= ERROR_OK
)
2791 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2797 if (!count
|| !buffer
)
2798 return ERROR_COMMAND_SYNTAX_ERROR
;
2800 retval
= mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2805 static int cortex_a_read_buffer(struct target
*target
, uint32_t address
,
2806 uint32_t count
, uint8_t *buffer
)
2810 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2811 * will have something to do with the size we leave to it. */
2812 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2813 if (address
& size
) {
2814 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, 1, buffer
);
2815 if (retval
!= ERROR_OK
)
2823 /* Read the data with as large access size as possible. */
2824 for (; size
> 0; size
/= 2) {
2825 uint32_t aligned
= count
- count
% size
;
2827 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2828 if (retval
!= ERROR_OK
)
2839 static int cortex_a_write_buffer(struct target
*target
, uint32_t address
,
2840 uint32_t count
, const uint8_t *buffer
)
2844 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2845 * will have something to do with the size we leave to it. */
2846 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2847 if (address
& size
) {
2848 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, 1, buffer
);
2849 if (retval
!= ERROR_OK
)
2857 /* Write the data with as large access size as possible. */
2858 for (; size
> 0; size
/= 2) {
2859 uint32_t aligned
= count
- count
% size
;
2861 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2862 if (retval
!= ERROR_OK
)
2873 static int cortex_a_handle_target_request(void *priv
)
2875 struct target
*target
= priv
;
2876 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2879 if (!target_was_examined(target
))
2881 if (!target
->dbg_msg_enabled
)
2884 if (target
->state
== TARGET_RUNNING
) {
2887 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2888 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2890 /* check if we have data */
2891 int64_t then
= timeval_ms();
2892 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2893 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2894 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2895 if (retval
== ERROR_OK
) {
2896 target_request(target
, request
);
2897 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2898 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2900 if (timeval_ms() > then
+ 1000) {
2901 LOG_ERROR("Timeout waiting for dtr tx full");
2911 * Cortex-A target information and configuration
2914 static int cortex_a_examine_first(struct target
*target
)
2916 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2917 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2918 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2921 int retval
= ERROR_OK
;
2922 uint32_t didr
, cpuid
, dbg_osreg
;
2924 retval
= dap_dp_init(swjdp
);
2925 if (retval
!= ERROR_OK
) {
2926 LOG_ERROR("Could not initialize the debug port");
2930 /* Search for the APB-AP - it is needed for access to debug registers */
2931 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2932 if (retval
!= ERROR_OK
) {
2933 LOG_ERROR("Could not find APB-AP for debug access");
2937 retval
= mem_ap_init(armv7a
->debug_ap
);
2938 if (retval
!= ERROR_OK
) {
2939 LOG_ERROR("Could not initialize the APB-AP");
2943 armv7a
->debug_ap
->memaccess_tck
= 80;
2945 /* Search for the AHB-AB.
2946 * REVISIT: We should search for AXI-AP as well and make sure the AP's MEMTYPE says it
2947 * can access system memory. */
2948 armv7a
->memory_ap_available
= false;
2949 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
2950 if (retval
== ERROR_OK
) {
2951 retval
= mem_ap_init(armv7a
->memory_ap
);
2952 if (retval
== ERROR_OK
)
2953 armv7a
->memory_ap_available
= true;
2955 if (retval
!= ERROR_OK
) {
2956 /* AHB-AP not found or unavailable - use the CPU */
2957 LOG_DEBUG("No AHB-AP available for memory access");
2960 if (!target
->dbgbase_set
) {
2962 /* Get ROM Table base */
2964 int32_t coreidx
= target
->coreid
;
2965 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2967 retval
= dap_get_debugbase(armv7a
->debug_ap
, &dbgbase
, &apid
);
2968 if (retval
!= ERROR_OK
)
2970 /* Lookup 0x15 -- Processor DAP */
2971 retval
= dap_lookup_cs_component(armv7a
->debug_ap
, dbgbase
, 0x15,
2972 &armv7a
->debug_base
, &coreidx
);
2973 if (retval
!= ERROR_OK
) {
2974 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2978 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2979 target
->coreid
, armv7a
->debug_base
);
2981 armv7a
->debug_base
= target
->dbgbase
;
2983 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2984 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2985 if (retval
!= ERROR_OK
) {
2986 LOG_DEBUG("Examine %s failed", "DIDR");
2990 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2991 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2992 if (retval
!= ERROR_OK
) {
2993 LOG_DEBUG("Examine %s failed", "CPUID");
2997 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
2998 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
3000 cortex_a
->didr
= didr
;
3001 cortex_a
->cpuid
= cpuid
;
3003 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3004 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
3005 if (retval
!= ERROR_OK
)
3007 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3009 if ((dbg_osreg
& PRSR_POWERUP_STATUS
) == 0) {
3010 LOG_ERROR("target->coreid %" PRId32
" powered down!", target
->coreid
);
3011 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
3012 return ERROR_TARGET_INIT_FAILED
;
3015 if (dbg_osreg
& PRSR_STICKY_RESET_STATUS
)
3016 LOG_DEBUG("target->coreid %" PRId32
" was reset!", target
->coreid
);
3018 /* Read DBGOSLSR and check if OSLK is implemented */
3019 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3020 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
3021 if (retval
!= ERROR_OK
)
3023 LOG_DEBUG("target->coreid %" PRId32
" DBGOSLSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3025 /* check if OS Lock is implemented */
3026 if ((dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM0
|| (dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM1
) {
3027 /* check if OS Lock is set */
3028 if (dbg_osreg
& OSLSR_OSLK
) {
3029 LOG_DEBUG("target->coreid %" PRId32
" OSLock set! Trying to unlock", target
->coreid
);
3031 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
3032 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3034 if (retval
== ERROR_OK
)
3035 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3036 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
3038 /* if we fail to access the register or cannot reset the OSLK bit, bail out */
3039 if (retval
!= ERROR_OK
|| (dbg_osreg
& OSLSR_OSLK
) != 0) {
3040 LOG_ERROR("target->coreid %" PRId32
" OSLock sticky, core not powered?",
3042 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
3043 return ERROR_TARGET_INIT_FAILED
;
3048 armv7a
->arm
.core_type
= ARM_MODE_MON
;
3050 /* Avoid recreating the registers cache */
3051 if (!target_was_examined(target
)) {
3052 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
3053 if (retval
!= ERROR_OK
)
3057 /* Setup Breakpoint Register Pairs */
3058 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
3059 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
3060 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
3061 free(cortex_a
->brp_list
);
3062 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
3063 /* cortex_a->brb_enabled = ????; */
3064 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
3065 cortex_a
->brp_list
[i
].used
= 0;
3066 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
3067 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
3069 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
3070 cortex_a
->brp_list
[i
].value
= 0;
3071 cortex_a
->brp_list
[i
].control
= 0;
3072 cortex_a
->brp_list
[i
].BRPn
= i
;
3075 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
3077 /* select debug_ap as default */
3078 swjdp
->apsel
= armv7a
->debug_ap
->ap_num
;
3080 target_set_examined(target
);
3084 static int cortex_a_examine(struct target
*target
)
3086 int retval
= ERROR_OK
;
3088 /* Reestablish communication after target reset */
3089 retval
= cortex_a_examine_first(target
);
3091 /* Configure core debug access */
3092 if (retval
== ERROR_OK
)
3093 retval
= cortex_a_init_debug_access(target
);
3099 * Cortex-A target creation and initialization
3102 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
3103 struct target
*target
)
3105 /* examine_first() does a bunch of this */
3106 arm_semihosting_init(target
);
3110 static int cortex_a_init_arch_info(struct target
*target
,
3111 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
3113 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
3115 /* Setup struct cortex_a_common */
3116 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3118 /* tap has no dap initialized */
3120 tap
->dap
= dap_init();
3122 /* Leave (only) generic DAP stuff for debugport_init() */
3123 tap
->dap
->tap
= tap
;
3126 armv7a
->arm
.dap
= tap
->dap
;
3128 cortex_a
->fast_reg_read
= 0;
3130 /* register arch-specific functions */
3131 armv7a
->examine_debug_reason
= NULL
;
3133 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
3135 armv7a
->pre_restore_context
= NULL
;
3137 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
3140 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3142 /* REVISIT v7a setup should be in a v7a-specific routine */
3143 armv7a_init_arch_info(target
, armv7a
);
3144 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
3149 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
3151 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3153 cortex_a
->armv7a_common
.is_armv7r
= false;
3155 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3158 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
3160 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3162 cortex_a
->armv7a_common
.is_armv7r
= true;
3164 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3167 static void cortex_a_deinit_target(struct target
*target
)
3169 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3170 struct arm_dpm
*dpm
= &cortex_a
->armv7a_common
.dpm
;
3172 free(cortex_a
->brp_list
);
3178 static int cortex_a_mmu(struct target
*target
, int *enabled
)
3180 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3182 if (target
->state
!= TARGET_HALTED
) {
3183 LOG_ERROR("%s: target not halted", __func__
);
3184 return ERROR_TARGET_INVALID
;
3187 if (armv7a
->is_armv7r
)
3190 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
3195 static int cortex_a_virt2phys(struct target
*target
,
3196 uint32_t virt
, uint32_t *phys
)
3198 int retval
= ERROR_FAIL
;
3199 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3200 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
3201 uint8_t apsel
= swjdp
->apsel
;
3202 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
)) {
3204 retval
= armv7a_mmu_translate_va(target
,
3206 if (retval
!= ERROR_OK
)
3209 } else {/* use this method if armv7a->memory_ap not selected
3210 * mmu must be enable in order to get a correct translation */
3211 retval
= cortex_a_mmu_modify(target
, 1);
3212 if (retval
!= ERROR_OK
)
3214 retval
= armv7a_mmu_translate_va_pa(target
, virt
, phys
, 1);
3220 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
3222 struct target
*target
= get_current_target(CMD_CTX
);
3223 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3225 return armv7a_handle_cache_info_command(CMD_CTX
,
3226 &armv7a
->armv7a_mmu
.armv7a_cache
);
3230 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
3232 struct target
*target
= get_current_target(CMD_CTX
);
3233 if (!target_was_examined(target
)) {
3234 LOG_ERROR("target not examined yet");
3238 return cortex_a_init_debug_access(target
);
3240 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
3242 struct target
*target
= get_current_target(CMD_CTX
);
3243 /* check target is an smp target */
3244 struct target_list
*head
;
3245 struct target
*curr
;
3246 head
= target
->head
;
3248 if (head
!= (struct target_list
*)NULL
) {
3249 while (head
!= (struct target_list
*)NULL
) {
3250 curr
= head
->target
;
3254 /* fixes the target display to the debugger */
3255 target
->gdb_service
->target
= target
;
3260 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
3262 struct target
*target
= get_current_target(CMD_CTX
);
3263 struct target_list
*head
;
3264 struct target
*curr
;
3265 head
= target
->head
;
3266 if (head
!= (struct target_list
*)NULL
) {
3268 while (head
!= (struct target_list
*)NULL
) {
3269 curr
= head
->target
;
3277 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
3279 struct target
*target
= get_current_target(CMD_CTX
);
3280 int retval
= ERROR_OK
;
3281 struct target_list
*head
;
3282 head
= target
->head
;
3283 if (head
!= (struct target_list
*)NULL
) {
3284 if (CMD_ARGC
== 1) {
3286 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
3287 if (ERROR_OK
!= retval
)
3289 target
->gdb_service
->core
[1] = coreid
;
3292 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
3293 , target
->gdb_service
->core
[1]);
3298 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
3300 struct target
*target
= get_current_target(CMD_CTX
);
3301 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3303 static const Jim_Nvp nvp_maskisr_modes
[] = {
3304 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
3305 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
3306 { .name
= NULL
, .value
= -1 },
3311 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
3312 if (n
->name
== NULL
) {
3313 LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV
[0]);
3314 return ERROR_COMMAND_SYNTAX_ERROR
;
3317 cortex_a
->isrmasking_mode
= n
->value
;
3320 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
3321 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
3326 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command
)
3328 struct target
*target
= get_current_target(CMD_CTX
);
3329 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3331 static const Jim_Nvp nvp_dacrfixup_modes
[] = {
3332 { .name
= "off", .value
= CORTEX_A_DACRFIXUP_OFF
},
3333 { .name
= "on", .value
= CORTEX_A_DACRFIXUP_ON
},
3334 { .name
= NULL
, .value
= -1 },
3339 n
= Jim_Nvp_name2value_simple(nvp_dacrfixup_modes
, CMD_ARGV
[0]);
3340 if (n
->name
== NULL
)
3341 return ERROR_COMMAND_SYNTAX_ERROR
;
3342 cortex_a
->dacrfixup_mode
= n
->value
;
3346 n
= Jim_Nvp_value2name_simple(nvp_dacrfixup_modes
, cortex_a
->dacrfixup_mode
);
3347 command_print(CMD_CTX
, "cortex_a domain access control fixup %s", n
->name
);
3352 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3354 .name
= "cache_info",
3355 .handler
= cortex_a_handle_cache_info_command
,
3356 .mode
= COMMAND_EXEC
,
3357 .help
= "display information about target caches",
3362 .handler
= cortex_a_handle_dbginit_command
,
3363 .mode
= COMMAND_EXEC
,
3364 .help
= "Initialize core debug",
3367 { .name
= "smp_off",
3368 .handler
= cortex_a_handle_smp_off_command
,
3369 .mode
= COMMAND_EXEC
,
3370 .help
= "Stop smp handling",
3374 .handler
= cortex_a_handle_smp_on_command
,
3375 .mode
= COMMAND_EXEC
,
3376 .help
= "Restart smp handling",
3381 .handler
= cortex_a_handle_smp_gdb_command
,
3382 .mode
= COMMAND_EXEC
,
3383 .help
= "display/fix current core played to gdb",
3388 .handler
= handle_cortex_a_mask_interrupts_command
,
3389 .mode
= COMMAND_ANY
,
3390 .help
= "mask cortex_a interrupts",
3391 .usage
= "['on'|'off']",
3394 .name
= "dacrfixup",
3395 .handler
= handle_cortex_a_dacrfixup_command
,
3396 .mode
= COMMAND_EXEC
,
3397 .help
= "set domain access control (DACR) to all-manager "
3399 .usage
= "['on'|'off']",
3402 COMMAND_REGISTRATION_DONE
3404 static const struct command_registration cortex_a_command_handlers
[] = {
3406 .chain
= arm_command_handlers
,
3409 .chain
= armv7a_command_handlers
,
3413 .mode
= COMMAND_ANY
,
3414 .help
= "Cortex-A command group",
3416 .chain
= cortex_a_exec_command_handlers
,
3418 COMMAND_REGISTRATION_DONE
3421 struct target_type cortexa_target
= {
3423 .deprecated_name
= "cortex_a8",
3425 .poll
= cortex_a_poll
,
3426 .arch_state
= armv7a_arch_state
,
3428 .halt
= cortex_a_halt
,
3429 .resume
= cortex_a_resume
,
3430 .step
= cortex_a_step
,
3432 .assert_reset
= cortex_a_assert_reset
,
3433 .deassert_reset
= cortex_a_deassert_reset
,
3435 /* REVISIT allow exporting VFP3 registers ... */
3436 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3438 .read_memory
= cortex_a_read_memory
,
3439 .write_memory
= cortex_a_write_memory
,
3441 .read_buffer
= cortex_a_read_buffer
,
3442 .write_buffer
= cortex_a_write_buffer
,
3444 .checksum_memory
= arm_checksum_memory
,
3445 .blank_check_memory
= arm_blank_check_memory
,
3447 .run_algorithm
= armv4_5_run_algorithm
,
3449 .add_breakpoint
= cortex_a_add_breakpoint
,
3450 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3451 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3452 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3453 .add_watchpoint
= NULL
,
3454 .remove_watchpoint
= NULL
,
3456 .commands
= cortex_a_command_handlers
,
3457 .target_create
= cortex_a_target_create
,
3458 .init_target
= cortex_a_init_target
,
3459 .examine
= cortex_a_examine
,
3460 .deinit_target
= cortex_a_deinit_target
,
3462 .read_phys_memory
= cortex_a_read_phys_memory
,
3463 .write_phys_memory
= cortex_a_write_phys_memory
,
3464 .mmu
= cortex_a_mmu
,
3465 .virt2phys
= cortex_a_virt2phys
,
3468 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3470 .name
= "cache_info",
3471 .handler
= cortex_a_handle_cache_info_command
,
3472 .mode
= COMMAND_EXEC
,
3473 .help
= "display information about target caches",
3478 .handler
= cortex_a_handle_dbginit_command
,
3479 .mode
= COMMAND_EXEC
,
3480 .help
= "Initialize core debug",
3485 .handler
= handle_cortex_a_mask_interrupts_command
,
3486 .mode
= COMMAND_EXEC
,
3487 .help
= "mask cortex_r4 interrupts",
3488 .usage
= "['on'|'off']",
3491 COMMAND_REGISTRATION_DONE
3493 static const struct command_registration cortex_r4_command_handlers
[] = {
3495 .chain
= arm_command_handlers
,
3498 .chain
= armv7a_command_handlers
,
3501 .name
= "cortex_r4",
3502 .mode
= COMMAND_ANY
,
3503 .help
= "Cortex-R4 command group",
3505 .chain
= cortex_r4_exec_command_handlers
,
3507 COMMAND_REGISTRATION_DONE
3510 struct target_type cortexr4_target
= {
3511 .name
= "cortex_r4",
3513 .poll
= cortex_a_poll
,
3514 .arch_state
= armv7a_arch_state
,
3516 .halt
= cortex_a_halt
,
3517 .resume
= cortex_a_resume
,
3518 .step
= cortex_a_step
,
3520 .assert_reset
= cortex_a_assert_reset
,
3521 .deassert_reset
= cortex_a_deassert_reset
,
3523 /* REVISIT allow exporting VFP3 registers ... */
3524 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3526 .read_memory
= cortex_a_read_phys_memory
,
3527 .write_memory
= cortex_a_write_phys_memory
,
3529 .checksum_memory
= arm_checksum_memory
,
3530 .blank_check_memory
= arm_blank_check_memory
,
3532 .run_algorithm
= armv4_5_run_algorithm
,
3534 .add_breakpoint
= cortex_a_add_breakpoint
,
3535 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3536 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3537 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3538 .add_watchpoint
= NULL
,
3539 .remove_watchpoint
= NULL
,
3541 .commands
= cortex_r4_command_handlers
,
3542 .target_create
= cortex_r4_target_create
,
3543 .init_target
= cortex_a_init_target
,
3544 .examine
= cortex_a_examine
,
3545 .deinit_target
= cortex_a_deinit_target
,