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[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_clear_halt(struct target *target)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 struct armv7m_common *armv7m = &cortex_m->armv7m;
143 int retval;
144
145 /* clear step if any */
146 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
147
148 /* Read Debug Fault Status Register */
149 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
150 if (retval != ERROR_OK)
151 return retval;
152
153 /* Clear Debug Fault Status */
154 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
155 if (retval != ERROR_OK)
156 return retval;
157 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
158
159 return ERROR_OK;
160 }
161
162 static int cortex_m_single_step_core(struct target *target)
163 {
164 struct cortex_m_common *cortex_m = target_to_cm(target);
165 struct armv7m_common *armv7m = &cortex_m->armv7m;
166 int retval;
167
168 /* Mask interrupts before clearing halt, if not done already. This avoids
169 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
170 * HALT can put the core into an unknown state.
171 */
172 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
174 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
175 if (retval != ERROR_OK)
176 return retval;
177 }
178 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
179 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
180 if (retval != ERROR_OK)
181 return retval;
182 LOG_DEBUG(" ");
183
184 /* restore dhcsr reg */
185 cortex_m_clear_halt(target);
186
187 return ERROR_OK;
188 }
189
190 static int cortex_m_enable_fpb(struct target *target)
191 {
192 int retval = target_write_u32(target, FP_CTRL, 3);
193 if (retval != ERROR_OK)
194 return retval;
195
196 /* check the fpb is actually enabled */
197 uint32_t fpctrl;
198 retval = target_read_u32(target, FP_CTRL, &fpctrl);
199 if (retval != ERROR_OK)
200 return retval;
201
202 if (fpctrl & 1)
203 return ERROR_OK;
204
205 return ERROR_FAIL;
206 }
207
208 static int cortex_m_endreset_event(struct target *target)
209 {
210 int i;
211 int retval;
212 uint32_t dcb_demcr;
213 struct cortex_m_common *cortex_m = target_to_cm(target);
214 struct armv7m_common *armv7m = &cortex_m->armv7m;
215 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
216 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
217 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
218
219 /* REVISIT The four debug monitor bits are currently ignored... */
220 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
221 if (retval != ERROR_OK)
222 return retval;
223 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
224
225 /* this register is used for emulated dcc channel */
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enable debug requests */
231 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
232 if (retval != ERROR_OK)
233 return retval;
234 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
235 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 /* Restore proper interrupt masking setting. */
241 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
242 cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
243 else
244 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
245
246 /* Enable features controlled by ITM and DWT blocks, and catch only
247 * the vectors we were told to pay attention to.
248 *
249 * Target firmware is responsible for all fault handling policy
250 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
251 * or manual updates to the NVIC SHCSR and CCR registers.
252 */
253 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
254 if (retval != ERROR_OK)
255 return retval;
256
257 /* Paranoia: evidently some (early?) chips don't preserve all the
258 * debug state (including FPB, DWT, etc) across reset...
259 */
260
261 /* Enable FPB */
262 retval = cortex_m_enable_fpb(target);
263 if (retval != ERROR_OK) {
264 LOG_ERROR("Failed to enable the FPB");
265 return retval;
266 }
267
268 cortex_m->fpb_enabled = 1;
269
270 /* Restore FPB registers */
271 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
272 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
273 if (retval != ERROR_OK)
274 return retval;
275 }
276
277 /* Restore DWT registers */
278 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
279 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
280 dwt_list[i].comp);
281 if (retval != ERROR_OK)
282 return retval;
283 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
284 dwt_list[i].mask);
285 if (retval != ERROR_OK)
286 return retval;
287 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
288 dwt_list[i].function);
289 if (retval != ERROR_OK)
290 return retval;
291 }
292 retval = dap_run(swjdp);
293 if (retval != ERROR_OK)
294 return retval;
295
296 register_cache_invalidate(armv7m->arm.core_cache);
297
298 /* make sure we have latest dhcsr flags */
299 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
300
301 return retval;
302 }
303
304 static int cortex_m_examine_debug_reason(struct target *target)
305 {
306 struct cortex_m_common *cortex_m = target_to_cm(target);
307
308 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
309 * only check the debug reason if we don't know it already */
310
311 if ((target->debug_reason != DBG_REASON_DBGRQ)
312 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
313 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
314 target->debug_reason = DBG_REASON_BREAKPOINT;
315 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
316 target->debug_reason = DBG_REASON_WPTANDBKPT;
317 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
318 target->debug_reason = DBG_REASON_WATCHPOINT;
319 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
320 target->debug_reason = DBG_REASON_BREAKPOINT;
321 else /* EXTERNAL, HALTED */
322 target->debug_reason = DBG_REASON_UNDEFINED;
323 }
324
325 return ERROR_OK;
326 }
327
328 static int cortex_m_examine_exception_reason(struct target *target)
329 {
330 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
331 struct armv7m_common *armv7m = target_to_armv7m(target);
332 struct adiv5_dap *swjdp = armv7m->arm.dap;
333 int retval;
334
335 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
336 if (retval != ERROR_OK)
337 return retval;
338 switch (armv7m->exception_number) {
339 case 2: /* NMI */
340 break;
341 case 3: /* Hard Fault */
342 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
343 if (retval != ERROR_OK)
344 return retval;
345 if (except_sr & 0x40000000) {
346 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350 break;
351 case 4: /* Memory Management */
352 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
353 if (retval != ERROR_OK)
354 return retval;
355 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
356 if (retval != ERROR_OK)
357 return retval;
358 break;
359 case 5: /* Bus Fault */
360 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
361 if (retval != ERROR_OK)
362 return retval;
363 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
364 if (retval != ERROR_OK)
365 return retval;
366 break;
367 case 6: /* Usage Fault */
368 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
369 if (retval != ERROR_OK)
370 return retval;
371 break;
372 case 11: /* SVCall */
373 break;
374 case 12: /* Debug Monitor */
375 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
376 if (retval != ERROR_OK)
377 return retval;
378 break;
379 case 14: /* PendSV */
380 break;
381 case 15: /* SysTick */
382 break;
383 default:
384 except_sr = 0;
385 break;
386 }
387 retval = dap_run(swjdp);
388 if (retval == ERROR_OK)
389 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
390 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
391 armv7m_exception_string(armv7m->exception_number),
392 shcsr, except_sr, cfsr, except_ar);
393 return retval;
394 }
395
396 static int cortex_m_debug_entry(struct target *target)
397 {
398 int i;
399 uint32_t xPSR;
400 int retval;
401 struct cortex_m_common *cortex_m = target_to_cm(target);
402 struct armv7m_common *armv7m = &cortex_m->armv7m;
403 struct arm *arm = &armv7m->arm;
404 struct reg *r;
405
406 LOG_DEBUG(" ");
407
408 cortex_m_clear_halt(target);
409 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
410 if (retval != ERROR_OK)
411 return retval;
412
413 retval = armv7m->examine_debug_reason(target);
414 if (retval != ERROR_OK)
415 return retval;
416
417 /* Examine target state and mode
418 * First load register accessible through core debug port */
419 int num_regs = arm->core_cache->num_regs;
420
421 for (i = 0; i < num_regs; i++) {
422 r = &armv7m->arm.core_cache->reg_list[i];
423 if (!r->valid)
424 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
425 }
426
427 r = arm->cpsr;
428 xPSR = buf_get_u32(r->value, 0, 32);
429
430 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
431 if (xPSR & 0xf00) {
432 r->dirty = r->valid;
433 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
434 }
435
436 /* Are we in an exception handler */
437 if (xPSR & 0x1FF) {
438 armv7m->exception_number = (xPSR & 0x1FF);
439
440 arm->core_mode = ARM_MODE_HANDLER;
441 arm->map = armv7m_msp_reg_map;
442 } else {
443 unsigned control = buf_get_u32(arm->core_cache
444 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
445
446 /* is this thread privileged? */
447 arm->core_mode = control & 1
448 ? ARM_MODE_USER_THREAD
449 : ARM_MODE_THREAD;
450
451 /* which stack is it using? */
452 if (control & 2)
453 arm->map = armv7m_psp_reg_map;
454 else
455 arm->map = armv7m_msp_reg_map;
456
457 armv7m->exception_number = 0;
458 }
459
460 if (armv7m->exception_number)
461 cortex_m_examine_exception_reason(target);
462
463 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
464 arm_mode_name(arm->core_mode),
465 buf_get_u32(arm->pc->value, 0, 32),
466 target_state_name(target));
467
468 if (armv7m->post_debug_entry) {
469 retval = armv7m->post_debug_entry(target);
470 if (retval != ERROR_OK)
471 return retval;
472 }
473
474 return ERROR_OK;
475 }
476
477 static int cortex_m_poll(struct target *target)
478 {
479 int detected_failure = ERROR_OK;
480 int retval = ERROR_OK;
481 enum target_state prev_target_state = target->state;
482 struct cortex_m_common *cortex_m = target_to_cm(target);
483 struct armv7m_common *armv7m = &cortex_m->armv7m;
484
485 /* Read from Debug Halting Control and Status Register */
486 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
487 if (retval != ERROR_OK) {
488 target->state = TARGET_UNKNOWN;
489 return retval;
490 }
491
492 /* Recover from lockup. See ARMv7-M architecture spec,
493 * section B1.5.15 "Unrecoverable exception cases".
494 */
495 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
496 LOG_ERROR("%s -- clearing lockup after double fault",
497 target_name(target));
498 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
499 target->debug_reason = DBG_REASON_DBGRQ;
500
501 /* We have to execute the rest (the "finally" equivalent, but
502 * still throw this exception again).
503 */
504 detected_failure = ERROR_FAIL;
505
506 /* refresh status bits */
507 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
508 if (retval != ERROR_OK)
509 return retval;
510 }
511
512 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
513 if (target->state != TARGET_RESET) {
514 target->state = TARGET_RESET;
515 LOG_INFO("%s: external reset detected", target_name(target));
516 }
517 return ERROR_OK;
518 }
519
520 if (target->state == TARGET_RESET) {
521 /* Cannot switch context while running so endreset is
522 * called with target->state == TARGET_RESET
523 */
524 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
525 cortex_m->dcb_dhcsr);
526 retval = cortex_m_endreset_event(target);
527 if (retval != ERROR_OK) {
528 target->state = TARGET_UNKNOWN;
529 return retval;
530 }
531 target->state = TARGET_RUNNING;
532 prev_target_state = TARGET_RUNNING;
533 }
534
535 if (cortex_m->dcb_dhcsr & S_HALT) {
536 target->state = TARGET_HALTED;
537
538 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
539 retval = cortex_m_debug_entry(target);
540 if (retval != ERROR_OK)
541 return retval;
542
543 if (arm_semihosting(target, &retval) != 0)
544 return retval;
545
546 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
547 }
548 if (prev_target_state == TARGET_DEBUG_RUNNING) {
549 LOG_DEBUG(" ");
550 retval = cortex_m_debug_entry(target);
551 if (retval != ERROR_OK)
552 return retval;
553
554 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
555 }
556 }
557
558 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
559 * How best to model low power modes?
560 */
561
562 if (target->state == TARGET_UNKNOWN) {
563 /* check if processor is retiring instructions */
564 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
565 target->state = TARGET_RUNNING;
566 retval = ERROR_OK;
567 }
568 }
569
570 /* Check that target is truly halted, since the target could be resumed externally */
571 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
572 /* registers are now invalid */
573 register_cache_invalidate(armv7m->arm.core_cache);
574
575 target->state = TARGET_RUNNING;
576 LOG_WARNING("%s: external resume detected", target_name(target));
577 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
578 retval = ERROR_OK;
579 }
580
581 /* Did we detect a failure condition that we cleared? */
582 if (detected_failure != ERROR_OK)
583 retval = detected_failure;
584 return retval;
585 }
586
587 static int cortex_m_halt(struct target *target)
588 {
589 LOG_DEBUG("target->state: %s",
590 target_state_name(target));
591
592 if (target->state == TARGET_HALTED) {
593 LOG_DEBUG("target was already halted");
594 return ERROR_OK;
595 }
596
597 if (target->state == TARGET_UNKNOWN)
598 LOG_WARNING("target was in unknown state when halt was requested");
599
600 if (target->state == TARGET_RESET) {
601 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
602 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
603 return ERROR_TARGET_FAILURE;
604 } else {
605 /* we came here in a reset_halt or reset_init sequence
606 * debug entry was already prepared in cortex_m3_assert_reset()
607 */
608 target->debug_reason = DBG_REASON_DBGRQ;
609
610 return ERROR_OK;
611 }
612 }
613
614 /* Write to Debug Halting Control and Status Register */
615 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
616
617 target->debug_reason = DBG_REASON_DBGRQ;
618
619 return ERROR_OK;
620 }
621
622 static int cortex_m_soft_reset_halt(struct target *target)
623 {
624 struct cortex_m_common *cortex_m = target_to_cm(target);
625 struct armv7m_common *armv7m = &cortex_m->armv7m;
626 uint32_t dcb_dhcsr = 0;
627 int retval, timeout = 0;
628
629 /* soft_reset_halt is deprecated on cortex_m as the same functionality
630 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
631 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
632 * core, not the peripherals */
633 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
634
635 /* Enter debug state on reset; restore DEMCR in endreset_event() */
636 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
637 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
638 if (retval != ERROR_OK)
639 return retval;
640
641 /* Request a core-only reset */
642 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
643 AIRCR_VECTKEY | AIRCR_VECTRESET);
644 if (retval != ERROR_OK)
645 return retval;
646 target->state = TARGET_RESET;
647
648 /* registers are now invalid */
649 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
650
651 while (timeout < 100) {
652 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
653 if (retval == ERROR_OK) {
654 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
655 &cortex_m->nvic_dfsr);
656 if (retval != ERROR_OK)
657 return retval;
658 if ((dcb_dhcsr & S_HALT)
659 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
660 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
661 "DFSR 0x%08x",
662 (unsigned) dcb_dhcsr,
663 (unsigned) cortex_m->nvic_dfsr);
664 cortex_m_poll(target);
665 /* FIXME restore user's vector catch config */
666 return ERROR_OK;
667 } else
668 LOG_DEBUG("waiting for system reset-halt, "
669 "DHCSR 0x%08x, %d ms",
670 (unsigned) dcb_dhcsr, timeout);
671 }
672 timeout++;
673 alive_sleep(1);
674 }
675
676 return ERROR_OK;
677 }
678
679 void cortex_m_enable_breakpoints(struct target *target)
680 {
681 struct breakpoint *breakpoint = target->breakpoints;
682
683 /* set any pending breakpoints */
684 while (breakpoint) {
685 if (!breakpoint->set)
686 cortex_m_set_breakpoint(target, breakpoint);
687 breakpoint = breakpoint->next;
688 }
689 }
690
691 static int cortex_m_resume(struct target *target, int current,
692 target_addr_t address, int handle_breakpoints, int debug_execution)
693 {
694 struct armv7m_common *armv7m = target_to_armv7m(target);
695 struct breakpoint *breakpoint = NULL;
696 uint32_t resume_pc;
697 struct reg *r;
698
699 if (target->state != TARGET_HALTED) {
700 LOG_WARNING("target not halted");
701 return ERROR_TARGET_NOT_HALTED;
702 }
703
704 if (!debug_execution) {
705 target_free_all_working_areas(target);
706 cortex_m_enable_breakpoints(target);
707 cortex_m_enable_watchpoints(target);
708 }
709
710 if (debug_execution) {
711 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
712
713 /* Disable interrupts */
714 /* We disable interrupts in the PRIMASK register instead of
715 * masking with C_MASKINTS. This is probably the same issue
716 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
717 * in parallel with disabled interrupts can cause local faults
718 * to not be taken.
719 *
720 * REVISIT this clearly breaks non-debug execution, since the
721 * PRIMASK register state isn't saved/restored... workaround
722 * by never resuming app code after debug execution.
723 */
724 buf_set_u32(r->value, 0, 1, 1);
725 r->dirty = true;
726 r->valid = true;
727
728 /* Make sure we are in Thumb mode */
729 r = armv7m->arm.cpsr;
730 buf_set_u32(r->value, 24, 1, 1);
731 r->dirty = true;
732 r->valid = true;
733 }
734
735 /* current = 1: continue on current pc, otherwise continue at <address> */
736 r = armv7m->arm.pc;
737 if (!current) {
738 buf_set_u32(r->value, 0, 32, address);
739 r->dirty = true;
740 r->valid = true;
741 }
742
743 /* if we halted last time due to a bkpt instruction
744 * then we have to manually step over it, otherwise
745 * the core will break again */
746
747 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
748 && !debug_execution)
749 armv7m_maybe_skip_bkpt_inst(target, NULL);
750
751 resume_pc = buf_get_u32(r->value, 0, 32);
752
753 armv7m_restore_context(target);
754
755 /* the front-end may request us not to handle breakpoints */
756 if (handle_breakpoints) {
757 /* Single step past breakpoint at current address */
758 breakpoint = breakpoint_find(target, resume_pc);
759 if (breakpoint) {
760 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
761 breakpoint->address,
762 breakpoint->unique_id);
763 cortex_m_unset_breakpoint(target, breakpoint);
764 cortex_m_single_step_core(target);
765 cortex_m_set_breakpoint(target, breakpoint);
766 }
767 }
768
769 /* Restart core */
770 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
771
772 target->debug_reason = DBG_REASON_NOTHALTED;
773
774 /* registers are now invalid */
775 register_cache_invalidate(armv7m->arm.core_cache);
776
777 if (!debug_execution) {
778 target->state = TARGET_RUNNING;
779 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
780 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
781 } else {
782 target->state = TARGET_DEBUG_RUNNING;
783 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
784 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
785 }
786
787 return ERROR_OK;
788 }
789
790 /* int irqstepcount = 0; */
791 static int cortex_m_step(struct target *target, int current,
792 target_addr_t address, int handle_breakpoints)
793 {
794 struct cortex_m_common *cortex_m = target_to_cm(target);
795 struct armv7m_common *armv7m = &cortex_m->armv7m;
796 struct breakpoint *breakpoint = NULL;
797 struct reg *pc = armv7m->arm.pc;
798 bool bkpt_inst_found = false;
799 int retval;
800 bool isr_timed_out = false;
801
802 if (target->state != TARGET_HALTED) {
803 LOG_WARNING("target not halted");
804 return ERROR_TARGET_NOT_HALTED;
805 }
806
807 /* current = 1: continue on current pc, otherwise continue at <address> */
808 if (!current)
809 buf_set_u32(pc->value, 0, 32, address);
810
811 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
812
813 /* the front-end may request us not to handle breakpoints */
814 if (handle_breakpoints) {
815 breakpoint = breakpoint_find(target, pc_value);
816 if (breakpoint)
817 cortex_m_unset_breakpoint(target, breakpoint);
818 }
819
820 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
821
822 target->debug_reason = DBG_REASON_SINGLESTEP;
823
824 armv7m_restore_context(target);
825
826 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
827
828 /* if no bkpt instruction is found at pc then we can perform
829 * a normal step, otherwise we have to manually step over the bkpt
830 * instruction - as such simulate a step */
831 if (bkpt_inst_found == false) {
832 /* Automatic ISR masking mode off: Just step over the next instruction */
833 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
834 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
835 else {
836 /* Process interrupts during stepping in a way they don't interfere
837 * debugging.
838 *
839 * Principle:
840 *
841 * Set a temporary break point at the current pc and let the core run
842 * with interrupts enabled. Pending interrupts get served and we run
843 * into the breakpoint again afterwards. Then we step over the next
844 * instruction with interrupts disabled.
845 *
846 * If the pending interrupts don't complete within time, we leave the
847 * core running. This may happen if the interrupts trigger faster
848 * than the core can process them or the handler doesn't return.
849 *
850 * If no more breakpoints are available we simply do a step with
851 * interrupts enabled.
852 *
853 */
854
855 /* 2012-09-29 ph
856 *
857 * If a break point is already set on the lower half word then a break point on
858 * the upper half word will not break again when the core is restarted. So we
859 * just step over the instruction with interrupts disabled.
860 *
861 * The documentation has no information about this, it was found by observation
862 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
863 * suffer from this problem.
864 *
865 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
866 * address has it always cleared. The former is done to indicate thumb mode
867 * to gdb.
868 *
869 */
870 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
871 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
872 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
873 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
874 /* Re-enable interrupts */
875 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
876 }
877 else {
878
879 /* Set a temporary break point */
880 if (breakpoint)
881 retval = cortex_m_set_breakpoint(target, breakpoint);
882 else
883 retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
884 bool tmp_bp_set = (retval == ERROR_OK);
885
886 /* No more breakpoints left, just do a step */
887 if (!tmp_bp_set)
888 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
889 else {
890 /* Start the core */
891 LOG_DEBUG("Starting core to serve pending interrupts");
892 int64_t t_start = timeval_ms();
893 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
894
895 /* Wait for pending handlers to complete or timeout */
896 do {
897 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
898 DCB_DHCSR,
899 &cortex_m->dcb_dhcsr);
900 if (retval != ERROR_OK) {
901 target->state = TARGET_UNKNOWN;
902 return retval;
903 }
904 isr_timed_out = ((timeval_ms() - t_start) > 500);
905 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
906
907 /* only remove breakpoint if we created it */
908 if (breakpoint)
909 cortex_m_unset_breakpoint(target, breakpoint);
910 else {
911 /* Remove the temporary breakpoint */
912 breakpoint_remove(target, pc_value);
913 }
914
915 if (isr_timed_out) {
916 LOG_DEBUG("Interrupt handlers didn't complete within time, "
917 "leaving target running");
918 } else {
919 /* Step over next instruction with interrupts disabled */
920 cortex_m_write_debug_halt_mask(target,
921 C_HALT | C_MASKINTS,
922 0);
923 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
924 /* Re-enable interrupts */
925 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
926 }
927 }
928 }
929 }
930 }
931
932 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
933 if (retval != ERROR_OK)
934 return retval;
935
936 /* registers are now invalid */
937 register_cache_invalidate(armv7m->arm.core_cache);
938
939 if (breakpoint)
940 cortex_m_set_breakpoint(target, breakpoint);
941
942 if (isr_timed_out) {
943 /* Leave the core running. The user has to stop execution manually. */
944 target->debug_reason = DBG_REASON_NOTHALTED;
945 target->state = TARGET_RUNNING;
946 return ERROR_OK;
947 }
948
949 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
950 " nvic_icsr = 0x%" PRIx32,
951 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
952
953 retval = cortex_m_debug_entry(target);
954 if (retval != ERROR_OK)
955 return retval;
956 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
957
958 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
959 " nvic_icsr = 0x%" PRIx32,
960 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
961
962 return ERROR_OK;
963 }
964
965 static int cortex_m_assert_reset(struct target *target)
966 {
967 struct cortex_m_common *cortex_m = target_to_cm(target);
968 struct armv7m_common *armv7m = &cortex_m->armv7m;
969 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
970
971 LOG_DEBUG("target->state: %s",
972 target_state_name(target));
973
974 enum reset_types jtag_reset_config = jtag_get_reset_config();
975
976 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
977 /* allow scripts to override the reset event */
978
979 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
980 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
981 target->state = TARGET_RESET;
982
983 return ERROR_OK;
984 }
985
986 /* some cores support connecting while srst is asserted
987 * use that mode is it has been configured */
988
989 bool srst_asserted = false;
990
991 if (!target_was_examined(target)) {
992 if (jtag_reset_config & RESET_HAS_SRST) {
993 adapter_assert_reset();
994 if (target->reset_halt)
995 LOG_ERROR("Target not examined, will not halt after reset!");
996 return ERROR_OK;
997 } else {
998 LOG_ERROR("Target not examined, reset NOT asserted!");
999 return ERROR_FAIL;
1000 }
1001 }
1002
1003 if ((jtag_reset_config & RESET_HAS_SRST) &&
1004 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1005 adapter_assert_reset();
1006 srst_asserted = true;
1007 }
1008
1009 /* Enable debug requests */
1010 int retval;
1011 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1012 /* Store important errors instead of failing and proceed to reset assert */
1013
1014 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1015 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1016
1017 /* If the processor is sleeping in a WFI or WFE instruction, the
1018 * C_HALT bit must be asserted to regain control */
1019 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1020 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1021
1022 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1023 /* Ignore less important errors */
1024
1025 if (!target->reset_halt) {
1026 /* Set/Clear C_MASKINTS in a separate operation */
1027 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1028 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1029
1030 /* clear any debug flags before resuming */
1031 cortex_m_clear_halt(target);
1032
1033 /* clear C_HALT in dhcsr reg */
1034 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1035 } else {
1036 /* Halt in debug on reset; endreset_event() restores DEMCR.
1037 *
1038 * REVISIT catching BUSERR presumably helps to defend against
1039 * bad vector table entries. Should this include MMERR or
1040 * other flags too?
1041 */
1042 int retval2;
1043 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1044 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1045 if (retval != ERROR_OK || retval2 != ERROR_OK)
1046 LOG_INFO("AP write error, reset will not halt");
1047 }
1048
1049 if (jtag_reset_config & RESET_HAS_SRST) {
1050 /* default to asserting srst */
1051 if (!srst_asserted)
1052 adapter_assert_reset();
1053
1054 /* srst is asserted, ignore AP access errors */
1055 retval = ERROR_OK;
1056 } else {
1057 /* Use a standard Cortex-M3 software reset mechanism.
1058 * We default to using VECRESET as it is supported on all current cores
1059 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1060 * This has the disadvantage of not resetting the peripherals, so a
1061 * reset-init event handler is needed to perform any peripheral resets.
1062 */
1063 if (!cortex_m->vectreset_supported
1064 && reset_config == CORTEX_M_RESET_VECTRESET) {
1065 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1066 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1067 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1068 }
1069
1070 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1071 ? "SYSRESETREQ" : "VECTRESET");
1072
1073 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1074 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1075 "handler to reset any peripherals or configure hardware srst support.");
1076 }
1077
1078 int retval3;
1079 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1080 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1081 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1082 if (retval3 != ERROR_OK)
1083 LOG_DEBUG("Ignoring AP write error right after reset");
1084
1085 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1086 if (retval3 != ERROR_OK)
1087 LOG_ERROR("DP initialisation failed");
1088
1089 else {
1090 /* I do not know why this is necessary, but it
1091 * fixes strange effects (step/resume cause NMI
1092 * after reset) on LM3S6918 -- Michael Schwingen
1093 */
1094 uint32_t tmp;
1095 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1096 }
1097 }
1098
1099 target->state = TARGET_RESET;
1100 jtag_add_sleep(50000);
1101
1102 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1103
1104 /* now return stored error code if any */
1105 if (retval != ERROR_OK)
1106 return retval;
1107
1108 if (target->reset_halt) {
1109 retval = target_halt(target);
1110 if (retval != ERROR_OK)
1111 return retval;
1112 }
1113
1114 return ERROR_OK;
1115 }
1116
1117 static int cortex_m_deassert_reset(struct target *target)
1118 {
1119 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1120
1121 LOG_DEBUG("target->state: %s",
1122 target_state_name(target));
1123
1124 /* deassert reset lines */
1125 adapter_deassert_reset();
1126
1127 enum reset_types jtag_reset_config = jtag_get_reset_config();
1128
1129 if ((jtag_reset_config & RESET_HAS_SRST) &&
1130 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1131 target_was_examined(target)) {
1132 int retval = dap_dp_init(armv7m->debug_ap->dap);
1133 if (retval != ERROR_OK) {
1134 LOG_ERROR("DP initialisation failed");
1135 return retval;
1136 }
1137 }
1138
1139 return ERROR_OK;
1140 }
1141
1142 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1143 {
1144 int retval;
1145 int fp_num = 0;
1146 struct cortex_m_common *cortex_m = target_to_cm(target);
1147 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1148
1149 if (breakpoint->set) {
1150 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1151 return ERROR_OK;
1152 }
1153
1154 if (breakpoint->type == BKPT_HARD) {
1155 uint32_t fpcr_value;
1156 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1157 fp_num++;
1158 if (fp_num >= cortex_m->fp_num_code) {
1159 LOG_ERROR("Can not find free FPB Comparator!");
1160 return ERROR_FAIL;
1161 }
1162 breakpoint->set = fp_num + 1;
1163 fpcr_value = breakpoint->address | 1;
1164 if (cortex_m->fp_rev == 0) {
1165 if (breakpoint->address > 0x1FFFFFFF) {
1166 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1167 return ERROR_FAIL;
1168 }
1169 uint32_t hilo;
1170 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1171 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1172 } else if (cortex_m->fp_rev > 1) {
1173 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1174 return ERROR_FAIL;
1175 }
1176 comparator_list[fp_num].used = 1;
1177 comparator_list[fp_num].fpcr_value = fpcr_value;
1178 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1179 comparator_list[fp_num].fpcr_value);
1180 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1181 fp_num,
1182 comparator_list[fp_num].fpcr_value);
1183 if (!cortex_m->fpb_enabled) {
1184 LOG_DEBUG("FPB wasn't enabled, do it now");
1185 retval = cortex_m_enable_fpb(target);
1186 if (retval != ERROR_OK) {
1187 LOG_ERROR("Failed to enable the FPB");
1188 return retval;
1189 }
1190
1191 cortex_m->fpb_enabled = 1;
1192 }
1193 } else if (breakpoint->type == BKPT_SOFT) {
1194 uint8_t code[4];
1195
1196 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1197 * semihosting; don't use that. Otherwise the BKPT
1198 * parameter is arbitrary.
1199 */
1200 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1201 retval = target_read_memory(target,
1202 breakpoint->address & 0xFFFFFFFE,
1203 breakpoint->length, 1,
1204 breakpoint->orig_instr);
1205 if (retval != ERROR_OK)
1206 return retval;
1207 retval = target_write_memory(target,
1208 breakpoint->address & 0xFFFFFFFE,
1209 breakpoint->length, 1,
1210 code);
1211 if (retval != ERROR_OK)
1212 return retval;
1213 breakpoint->set = true;
1214 }
1215
1216 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1217 breakpoint->unique_id,
1218 (int)(breakpoint->type),
1219 breakpoint->address,
1220 breakpoint->length,
1221 breakpoint->set);
1222
1223 return ERROR_OK;
1224 }
1225
1226 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1227 {
1228 int retval;
1229 struct cortex_m_common *cortex_m = target_to_cm(target);
1230 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1231
1232 if (!breakpoint->set) {
1233 LOG_WARNING("breakpoint not set");
1234 return ERROR_OK;
1235 }
1236
1237 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1238 breakpoint->unique_id,
1239 (int)(breakpoint->type),
1240 breakpoint->address,
1241 breakpoint->length,
1242 breakpoint->set);
1243
1244 if (breakpoint->type == BKPT_HARD) {
1245 int fp_num = breakpoint->set - 1;
1246 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1247 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1248 return ERROR_OK;
1249 }
1250 comparator_list[fp_num].used = 0;
1251 comparator_list[fp_num].fpcr_value = 0;
1252 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1253 comparator_list[fp_num].fpcr_value);
1254 } else {
1255 /* restore original instruction (kept in target endianness) */
1256 if (breakpoint->length == 4) {
1257 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1258 breakpoint->orig_instr);
1259 if (retval != ERROR_OK)
1260 return retval;
1261 } else {
1262 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1263 breakpoint->orig_instr);
1264 if (retval != ERROR_OK)
1265 return retval;
1266 }
1267 }
1268 breakpoint->set = false;
1269
1270 return ERROR_OK;
1271 }
1272
1273 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1274 {
1275 struct cortex_m_common *cortex_m = target_to_cm(target);
1276
1277 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1278 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1279 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1280 }
1281
1282 if (breakpoint->length == 3) {
1283 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1284 breakpoint->length = 2;
1285 }
1286
1287 if ((breakpoint->length != 2)) {
1288 LOG_INFO("only breakpoints of two bytes length supported");
1289 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1290 }
1291
1292 if (breakpoint->type == BKPT_HARD)
1293 cortex_m->fp_code_available--;
1294
1295 return cortex_m_set_breakpoint(target, breakpoint);
1296 }
1297
1298 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1299 {
1300 struct cortex_m_common *cortex_m = target_to_cm(target);
1301
1302 /* REVISIT why check? FPB can be updated with core running ... */
1303 if (target->state != TARGET_HALTED) {
1304 LOG_WARNING("target not halted");
1305 return ERROR_TARGET_NOT_HALTED;
1306 }
1307
1308 if (breakpoint->set)
1309 cortex_m_unset_breakpoint(target, breakpoint);
1310
1311 if (breakpoint->type == BKPT_HARD)
1312 cortex_m->fp_code_available++;
1313
1314 return ERROR_OK;
1315 }
1316
1317 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1318 {
1319 int dwt_num = 0;
1320 uint32_t mask, temp;
1321 struct cortex_m_common *cortex_m = target_to_cm(target);
1322
1323 /* watchpoint params were validated earlier */
1324 mask = 0;
1325 temp = watchpoint->length;
1326 while (temp) {
1327 temp >>= 1;
1328 mask++;
1329 }
1330 mask--;
1331
1332 /* REVISIT Don't fully trust these "not used" records ... users
1333 * may set up breakpoints by hand, e.g. dual-address data value
1334 * watchpoint using comparator #1; comparator #0 matching cycle
1335 * count; send data trace info through ITM and TPIU; etc
1336 */
1337 struct cortex_m_dwt_comparator *comparator;
1338
1339 for (comparator = cortex_m->dwt_comparator_list;
1340 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1341 comparator++, dwt_num++)
1342 continue;
1343 if (dwt_num >= cortex_m->dwt_num_comp) {
1344 LOG_ERROR("Can not find free DWT Comparator");
1345 return ERROR_FAIL;
1346 }
1347 comparator->used = 1;
1348 watchpoint->set = dwt_num + 1;
1349
1350 comparator->comp = watchpoint->address;
1351 target_write_u32(target, comparator->dwt_comparator_address + 0,
1352 comparator->comp);
1353
1354 comparator->mask = mask;
1355 target_write_u32(target, comparator->dwt_comparator_address + 4,
1356 comparator->mask);
1357
1358 switch (watchpoint->rw) {
1359 case WPT_READ:
1360 comparator->function = 5;
1361 break;
1362 case WPT_WRITE:
1363 comparator->function = 6;
1364 break;
1365 case WPT_ACCESS:
1366 comparator->function = 7;
1367 break;
1368 }
1369 target_write_u32(target, comparator->dwt_comparator_address + 8,
1370 comparator->function);
1371
1372 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1373 watchpoint->unique_id, dwt_num,
1374 (unsigned) comparator->comp,
1375 (unsigned) comparator->mask,
1376 (unsigned) comparator->function);
1377 return ERROR_OK;
1378 }
1379
1380 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1381 {
1382 struct cortex_m_common *cortex_m = target_to_cm(target);
1383 struct cortex_m_dwt_comparator *comparator;
1384 int dwt_num;
1385
1386 if (!watchpoint->set) {
1387 LOG_WARNING("watchpoint (wpid: %d) not set",
1388 watchpoint->unique_id);
1389 return ERROR_OK;
1390 }
1391
1392 dwt_num = watchpoint->set - 1;
1393
1394 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1395 watchpoint->unique_id, dwt_num,
1396 (unsigned) watchpoint->address);
1397
1398 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1399 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1400 return ERROR_OK;
1401 }
1402
1403 comparator = cortex_m->dwt_comparator_list + dwt_num;
1404 comparator->used = 0;
1405 comparator->function = 0;
1406 target_write_u32(target, comparator->dwt_comparator_address + 8,
1407 comparator->function);
1408
1409 watchpoint->set = false;
1410
1411 return ERROR_OK;
1412 }
1413
1414 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1415 {
1416 struct cortex_m_common *cortex_m = target_to_cm(target);
1417
1418 if (cortex_m->dwt_comp_available < 1) {
1419 LOG_DEBUG("no comparators?");
1420 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1421 }
1422
1423 /* hardware doesn't support data value masking */
1424 if (watchpoint->mask != ~(uint32_t)0) {
1425 LOG_DEBUG("watchpoint value masks not supported");
1426 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1427 }
1428
1429 /* hardware allows address masks of up to 32K */
1430 unsigned mask;
1431
1432 for (mask = 0; mask < 16; mask++) {
1433 if ((1u << mask) == watchpoint->length)
1434 break;
1435 }
1436 if (mask == 16) {
1437 LOG_DEBUG("unsupported watchpoint length");
1438 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1439 }
1440 if (watchpoint->address & ((1 << mask) - 1)) {
1441 LOG_DEBUG("watchpoint address is unaligned");
1442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1443 }
1444
1445 /* Caller doesn't seem to be able to describe watching for data
1446 * values of zero; that flags "no value".
1447 *
1448 * REVISIT This DWT may well be able to watch for specific data
1449 * values. Requires comparator #1 to set DATAVMATCH and match
1450 * the data, and another comparator (DATAVADDR0) matching addr.
1451 */
1452 if (watchpoint->value) {
1453 LOG_DEBUG("data value watchpoint not YET supported");
1454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1455 }
1456
1457 cortex_m->dwt_comp_available--;
1458 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1459
1460 return ERROR_OK;
1461 }
1462
1463 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1464 {
1465 struct cortex_m_common *cortex_m = target_to_cm(target);
1466
1467 /* REVISIT why check? DWT can be updated with core running ... */
1468 if (target->state != TARGET_HALTED) {
1469 LOG_WARNING("target not halted");
1470 return ERROR_TARGET_NOT_HALTED;
1471 }
1472
1473 if (watchpoint->set)
1474 cortex_m_unset_watchpoint(target, watchpoint);
1475
1476 cortex_m->dwt_comp_available++;
1477 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1478
1479 return ERROR_OK;
1480 }
1481
1482 void cortex_m_enable_watchpoints(struct target *target)
1483 {
1484 struct watchpoint *watchpoint = target->watchpoints;
1485
1486 /* set any pending watchpoints */
1487 while (watchpoint) {
1488 if (!watchpoint->set)
1489 cortex_m_set_watchpoint(target, watchpoint);
1490 watchpoint = watchpoint->next;
1491 }
1492 }
1493
1494 static int cortex_m_load_core_reg_u32(struct target *target,
1495 uint32_t num, uint32_t *value)
1496 {
1497 int retval;
1498
1499 /* NOTE: we "know" here that the register identifiers used
1500 * in the v7m header match the Cortex-M3 Debug Core Register
1501 * Selector values for R0..R15, xPSR, MSP, and PSP.
1502 */
1503 switch (num) {
1504 case 0 ... 18:
1505 /* read a normal core register */
1506 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1507
1508 if (retval != ERROR_OK) {
1509 LOG_ERROR("JTAG failure %i", retval);
1510 return ERROR_JTAG_DEVICE_ERROR;
1511 }
1512 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1513 break;
1514
1515 case ARMV7M_FPSCR:
1516 /* Floating-point Status and Registers */
1517 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1518 if (retval != ERROR_OK)
1519 return retval;
1520 retval = target_read_u32(target, DCB_DCRDR, value);
1521 if (retval != ERROR_OK)
1522 return retval;
1523 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1524 break;
1525
1526 case ARMV7M_S0 ... ARMV7M_S31:
1527 /* Floating-point Status and Registers */
1528 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1529 if (retval != ERROR_OK)
1530 return retval;
1531 retval = target_read_u32(target, DCB_DCRDR, value);
1532 if (retval != ERROR_OK)
1533 return retval;
1534 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1535 (int)(num - ARMV7M_S0), *value);
1536 break;
1537
1538 case ARMV7M_PRIMASK:
1539 case ARMV7M_BASEPRI:
1540 case ARMV7M_FAULTMASK:
1541 case ARMV7M_CONTROL:
1542 /* Cortex-M3 packages these four registers as bitfields
1543 * in one Debug Core register. So say r0 and r2 docs;
1544 * it was removed from r1 docs, but still works.
1545 */
1546 cortexm_dap_read_coreregister_u32(target, value, 20);
1547
1548 switch (num) {
1549 case ARMV7M_PRIMASK:
1550 *value = buf_get_u32((uint8_t *)value, 0, 1);
1551 break;
1552
1553 case ARMV7M_BASEPRI:
1554 *value = buf_get_u32((uint8_t *)value, 8, 8);
1555 break;
1556
1557 case ARMV7M_FAULTMASK:
1558 *value = buf_get_u32((uint8_t *)value, 16, 1);
1559 break;
1560
1561 case ARMV7M_CONTROL:
1562 *value = buf_get_u32((uint8_t *)value, 24, 2);
1563 break;
1564 }
1565
1566 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1567 break;
1568
1569 default:
1570 return ERROR_COMMAND_SYNTAX_ERROR;
1571 }
1572
1573 return ERROR_OK;
1574 }
1575
1576 static int cortex_m_store_core_reg_u32(struct target *target,
1577 uint32_t num, uint32_t value)
1578 {
1579 int retval;
1580 uint32_t reg;
1581 struct armv7m_common *armv7m = target_to_armv7m(target);
1582
1583 /* NOTE: we "know" here that the register identifiers used
1584 * in the v7m header match the Cortex-M3 Debug Core Register
1585 * Selector values for R0..R15, xPSR, MSP, and PSP.
1586 */
1587 switch (num) {
1588 case 0 ... 18:
1589 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1590 if (retval != ERROR_OK) {
1591 struct reg *r;
1592
1593 LOG_ERROR("JTAG failure");
1594 r = armv7m->arm.core_cache->reg_list + num;
1595 r->dirty = r->valid;
1596 return ERROR_JTAG_DEVICE_ERROR;
1597 }
1598 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1599 break;
1600
1601 case ARMV7M_FPSCR:
1602 /* Floating-point Status and Registers */
1603 retval = target_write_u32(target, DCB_DCRDR, value);
1604 if (retval != ERROR_OK)
1605 return retval;
1606 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1607 if (retval != ERROR_OK)
1608 return retval;
1609 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1610 break;
1611
1612 case ARMV7M_S0 ... ARMV7M_S31:
1613 /* Floating-point Status and Registers */
1614 retval = target_write_u32(target, DCB_DCRDR, value);
1615 if (retval != ERROR_OK)
1616 return retval;
1617 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1618 if (retval != ERROR_OK)
1619 return retval;
1620 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1621 (int)(num - ARMV7M_S0), value);
1622 break;
1623
1624 case ARMV7M_PRIMASK:
1625 case ARMV7M_BASEPRI:
1626 case ARMV7M_FAULTMASK:
1627 case ARMV7M_CONTROL:
1628 /* Cortex-M3 packages these four registers as bitfields
1629 * in one Debug Core register. So say r0 and r2 docs;
1630 * it was removed from r1 docs, but still works.
1631 */
1632 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1633
1634 switch (num) {
1635 case ARMV7M_PRIMASK:
1636 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1637 break;
1638
1639 case ARMV7M_BASEPRI:
1640 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1641 break;
1642
1643 case ARMV7M_FAULTMASK:
1644 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1645 break;
1646
1647 case ARMV7M_CONTROL:
1648 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1649 break;
1650 }
1651
1652 cortexm_dap_write_coreregister_u32(target, reg, 20);
1653
1654 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1655 break;
1656
1657 default:
1658 return ERROR_COMMAND_SYNTAX_ERROR;
1659 }
1660
1661 return ERROR_OK;
1662 }
1663
1664 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1665 uint32_t size, uint32_t count, uint8_t *buffer)
1666 {
1667 struct armv7m_common *armv7m = target_to_armv7m(target);
1668
1669 if (armv7m->arm.is_armv6m) {
1670 /* armv6m does not handle unaligned memory access */
1671 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1672 return ERROR_TARGET_UNALIGNED_ACCESS;
1673 }
1674
1675 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1676 }
1677
1678 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1679 uint32_t size, uint32_t count, const uint8_t *buffer)
1680 {
1681 struct armv7m_common *armv7m = target_to_armv7m(target);
1682
1683 if (armv7m->arm.is_armv6m) {
1684 /* armv6m does not handle unaligned memory access */
1685 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1686 return ERROR_TARGET_UNALIGNED_ACCESS;
1687 }
1688
1689 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1690 }
1691
1692 static int cortex_m_init_target(struct command_context *cmd_ctx,
1693 struct target *target)
1694 {
1695 armv7m_build_reg_cache(target);
1696 arm_semihosting_init(target);
1697 return ERROR_OK;
1698 }
1699
1700 void cortex_m_deinit_target(struct target *target)
1701 {
1702 struct cortex_m_common *cortex_m = target_to_cm(target);
1703
1704 free(cortex_m->fp_comparator_list);
1705
1706 cortex_m_dwt_free(target);
1707 armv7m_free_reg_cache(target);
1708
1709 free(target->private_config);
1710 free(cortex_m);
1711 }
1712
1713 int cortex_m_profiling(struct target *target, uint32_t *samples,
1714 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1715 {
1716 struct timeval timeout, now;
1717 struct armv7m_common *armv7m = target_to_armv7m(target);
1718 uint32_t reg_value;
1719 bool use_pcsr = false;
1720 int retval = ERROR_OK;
1721 struct reg *reg;
1722
1723 gettimeofday(&timeout, NULL);
1724 timeval_add_time(&timeout, seconds, 0);
1725
1726 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1727 if (retval != ERROR_OK) {
1728 LOG_ERROR("Error while reading PCSR");
1729 return retval;
1730 }
1731
1732 if (reg_value != 0) {
1733 use_pcsr = true;
1734 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1735 } else {
1736 LOG_INFO("Starting profiling. Halting and resuming the"
1737 " target as often as we can...");
1738 reg = register_get_by_name(target->reg_cache, "pc", 1);
1739 }
1740
1741 /* Make sure the target is running */
1742 target_poll(target);
1743 if (target->state == TARGET_HALTED)
1744 retval = target_resume(target, 1, 0, 0, 0);
1745
1746 if (retval != ERROR_OK) {
1747 LOG_ERROR("Error while resuming target");
1748 return retval;
1749 }
1750
1751 uint32_t sample_count = 0;
1752
1753 for (;;) {
1754 if (use_pcsr) {
1755 if (armv7m && armv7m->debug_ap) {
1756 uint32_t read_count = max_num_samples - sample_count;
1757 if (read_count > 1024)
1758 read_count = 1024;
1759
1760 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1761 (void *)&samples[sample_count],
1762 4, read_count, DWT_PCSR);
1763 sample_count += read_count;
1764 } else {
1765 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1766 }
1767 } else {
1768 target_poll(target);
1769 if (target->state == TARGET_HALTED) {
1770 reg_value = buf_get_u32(reg->value, 0, 32);
1771 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1772 retval = target_resume(target, 1, 0, 0, 0);
1773 samples[sample_count++] = reg_value;
1774 target_poll(target);
1775 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1776 } else if (target->state == TARGET_RUNNING) {
1777 /* We want to quickly sample the PC. */
1778 retval = target_halt(target);
1779 } else {
1780 LOG_INFO("Target not halted or running");
1781 retval = ERROR_OK;
1782 break;
1783 }
1784 }
1785
1786 if (retval != ERROR_OK) {
1787 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1788 return retval;
1789 }
1790
1791
1792 gettimeofday(&now, NULL);
1793 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1794 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1795 break;
1796 }
1797 }
1798
1799 *num_samples = sample_count;
1800 return retval;
1801 }
1802
1803
1804 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1805 * on r/w if the core is not running, and clear on resume or reset ... or
1806 * at least, in a post_restore_context() method.
1807 */
1808
1809 struct dwt_reg_state {
1810 struct target *target;
1811 uint32_t addr;
1812 uint8_t value[4]; /* scratch/cache */
1813 };
1814
1815 static int cortex_m_dwt_get_reg(struct reg *reg)
1816 {
1817 struct dwt_reg_state *state = reg->arch_info;
1818
1819 uint32_t tmp;
1820 int retval = target_read_u32(state->target, state->addr, &tmp);
1821 if (retval != ERROR_OK)
1822 return retval;
1823
1824 buf_set_u32(state->value, 0, 32, tmp);
1825 return ERROR_OK;
1826 }
1827
1828 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1829 {
1830 struct dwt_reg_state *state = reg->arch_info;
1831
1832 return target_write_u32(state->target, state->addr,
1833 buf_get_u32(buf, 0, reg->size));
1834 }
1835
1836 struct dwt_reg {
1837 uint32_t addr;
1838 const char *name;
1839 unsigned size;
1840 };
1841
1842 static const struct dwt_reg dwt_base_regs[] = {
1843 { DWT_CTRL, "dwt_ctrl", 32, },
1844 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1845 * increments while the core is asleep.
1846 */
1847 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1848 /* plus some 8 bit counters, useful for profiling with TPIU */
1849 };
1850
1851 static const struct dwt_reg dwt_comp[] = {
1852 #define DWT_COMPARATOR(i) \
1853 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1854 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1855 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1856 DWT_COMPARATOR(0),
1857 DWT_COMPARATOR(1),
1858 DWT_COMPARATOR(2),
1859 DWT_COMPARATOR(3),
1860 DWT_COMPARATOR(4),
1861 DWT_COMPARATOR(5),
1862 DWT_COMPARATOR(6),
1863 DWT_COMPARATOR(7),
1864 DWT_COMPARATOR(8),
1865 DWT_COMPARATOR(9),
1866 DWT_COMPARATOR(10),
1867 DWT_COMPARATOR(11),
1868 DWT_COMPARATOR(12),
1869 DWT_COMPARATOR(13),
1870 DWT_COMPARATOR(14),
1871 DWT_COMPARATOR(15),
1872 #undef DWT_COMPARATOR
1873 };
1874
1875 static const struct reg_arch_type dwt_reg_type = {
1876 .get = cortex_m_dwt_get_reg,
1877 .set = cortex_m_dwt_set_reg,
1878 };
1879
1880 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1881 {
1882 struct dwt_reg_state *state;
1883
1884 state = calloc(1, sizeof *state);
1885 if (!state)
1886 return;
1887 state->addr = d->addr;
1888 state->target = t;
1889
1890 r->name = d->name;
1891 r->size = d->size;
1892 r->value = state->value;
1893 r->arch_info = state;
1894 r->type = &dwt_reg_type;
1895 }
1896
1897 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1898 {
1899 uint32_t dwtcr;
1900 struct reg_cache *cache;
1901 struct cortex_m_dwt_comparator *comparator;
1902 int reg, i;
1903
1904 target_read_u32(target, DWT_CTRL, &dwtcr);
1905 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1906 if (!dwtcr) {
1907 LOG_DEBUG("no DWT");
1908 return;
1909 }
1910
1911 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1912 cm->dwt_comp_available = cm->dwt_num_comp;
1913 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1914 sizeof(struct cortex_m_dwt_comparator));
1915 if (!cm->dwt_comparator_list) {
1916 fail0:
1917 cm->dwt_num_comp = 0;
1918 LOG_ERROR("out of mem");
1919 return;
1920 }
1921
1922 cache = calloc(1, sizeof *cache);
1923 if (!cache) {
1924 fail1:
1925 free(cm->dwt_comparator_list);
1926 goto fail0;
1927 }
1928 cache->name = "Cortex-M DWT registers";
1929 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1930 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1931 if (!cache->reg_list) {
1932 free(cache);
1933 goto fail1;
1934 }
1935
1936 for (reg = 0; reg < 2; reg++)
1937 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1938 dwt_base_regs + reg);
1939
1940 comparator = cm->dwt_comparator_list;
1941 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1942 int j;
1943
1944 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1945 for (j = 0; j < 3; j++, reg++)
1946 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1947 dwt_comp + 3 * i + j);
1948
1949 /* make sure we clear any watchpoints enabled on the target */
1950 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1951 }
1952
1953 *register_get_last_cache_p(&target->reg_cache) = cache;
1954 cm->dwt_cache = cache;
1955
1956 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1957 dwtcr, cm->dwt_num_comp,
1958 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1959
1960 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1961 * implement single-address data value watchpoints ... so we
1962 * won't need to check it later, when asked to set one up.
1963 */
1964 }
1965
1966 static void cortex_m_dwt_free(struct target *target)
1967 {
1968 struct cortex_m_common *cm = target_to_cm(target);
1969 struct reg_cache *cache = cm->dwt_cache;
1970
1971 free(cm->dwt_comparator_list);
1972 cm->dwt_comparator_list = NULL;
1973 cm->dwt_num_comp = 0;
1974
1975 if (cache) {
1976 register_unlink_cache(&target->reg_cache, cache);
1977
1978 if (cache->reg_list) {
1979 for (size_t i = 0; i < cache->num_regs; i++)
1980 free(cache->reg_list[i].arch_info);
1981 free(cache->reg_list);
1982 }
1983 free(cache);
1984 }
1985 cm->dwt_cache = NULL;
1986 }
1987
1988 #define MVFR0 0xe000ef40
1989 #define MVFR1 0xe000ef44
1990
1991 #define MVFR0_DEFAULT_M4 0x10110021
1992 #define MVFR1_DEFAULT_M4 0x11000011
1993
1994 #define MVFR0_DEFAULT_M7_SP 0x10110021
1995 #define MVFR0_DEFAULT_M7_DP 0x10110221
1996 #define MVFR1_DEFAULT_M7_SP 0x11000011
1997 #define MVFR1_DEFAULT_M7_DP 0x12000011
1998
1999 int cortex_m_examine(struct target *target)
2000 {
2001 int retval;
2002 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2003 int i;
2004 struct cortex_m_common *cortex_m = target_to_cm(target);
2005 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2006 struct armv7m_common *armv7m = target_to_armv7m(target);
2007
2008 /* stlink shares the examine handler but does not support
2009 * all its calls */
2010 if (!armv7m->stlink) {
2011 if (cortex_m->apsel == DP_APSEL_INVALID) {
2012 /* Search for the MEM-AP */
2013 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
2014 if (retval != ERROR_OK) {
2015 LOG_ERROR("Could not find MEM-AP to control the core");
2016 return retval;
2017 }
2018 } else {
2019 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2020 }
2021
2022 /* Leave (only) generic DAP stuff for debugport_init(); */
2023 armv7m->debug_ap->memaccess_tck = 8;
2024
2025 retval = mem_ap_init(armv7m->debug_ap);
2026 if (retval != ERROR_OK)
2027 return retval;
2028 }
2029
2030 if (!target_was_examined(target)) {
2031 target_set_examined(target);
2032
2033 /* Read from Device Identification Registers */
2034 retval = target_read_u32(target, CPUID, &cpuid);
2035 if (retval != ERROR_OK)
2036 return retval;
2037
2038 /* Get CPU Type */
2039 i = (cpuid >> 4) & 0xf;
2040
2041 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2042 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2043 if (i == 7) {
2044 uint8_t rev, patch;
2045 rev = (cpuid >> 20) & 0xf;
2046 patch = (cpuid >> 0) & 0xf;
2047 if ((rev == 0) && (patch < 2))
2048 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2049 }
2050 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2051
2052 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2053 cortex_m->vectreset_supported = i > 1;
2054
2055 if (i == 4) {
2056 target_read_u32(target, MVFR0, &mvfr0);
2057 target_read_u32(target, MVFR1, &mvfr1);
2058
2059 /* test for floating point feature on Cortex-M4 */
2060 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2061 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2062 armv7m->fp_feature = FPv4_SP;
2063 }
2064 } else if (i == 7) {
2065 target_read_u32(target, MVFR0, &mvfr0);
2066 target_read_u32(target, MVFR1, &mvfr1);
2067
2068 /* test for floating point features on Cortex-M7 */
2069 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2070 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2071 armv7m->fp_feature = FPv5_SP;
2072 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2073 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2074 armv7m->fp_feature = FPv5_DP;
2075 }
2076 } else if (i == 0) {
2077 /* Cortex-M0 does not support unaligned memory access */
2078 armv7m->arm.is_armv6m = true;
2079 }
2080
2081 if (armv7m->fp_feature == FP_NONE &&
2082 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2083 /* free unavailable FPU registers */
2084 size_t idx;
2085
2086 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2087 idx < armv7m->arm.core_cache->num_regs;
2088 idx++) {
2089 free(armv7m->arm.core_cache->reg_list[idx].value);
2090 free(armv7m->arm.core_cache->reg_list[idx].feature);
2091 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2092 }
2093 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2094 }
2095
2096 if (!armv7m->stlink) {
2097 if (i == 3 || i == 4)
2098 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2099 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2100 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2101 else if (i == 7)
2102 /* Cortex-M7 has only 1024 bytes autoincrement range */
2103 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2104 }
2105
2106 /* Configure trace modules */
2107 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2108 if (retval != ERROR_OK)
2109 return retval;
2110
2111 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2112 armv7m_trace_tpiu_config(target);
2113 armv7m_trace_itm_config(target);
2114 }
2115
2116 /* NOTE: FPB and DWT are both optional. */
2117
2118 /* Setup FPB */
2119 target_read_u32(target, FP_CTRL, &fpcr);
2120 /* bits [14:12] and [7:4] */
2121 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2122 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2123 cortex_m->fp_code_available = cortex_m->fp_num_code;
2124 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2125 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2126 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2127 free(cortex_m->fp_comparator_list);
2128 cortex_m->fp_comparator_list = calloc(
2129 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2130 sizeof(struct cortex_m_fp_comparator));
2131 cortex_m->fpb_enabled = fpcr & 1;
2132 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2133 cortex_m->fp_comparator_list[i].type =
2134 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2135 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2136
2137 /* make sure we clear any breakpoints enabled on the target */
2138 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2139 }
2140 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2141 fpcr,
2142 cortex_m->fp_num_code,
2143 cortex_m->fp_num_lit);
2144
2145 /* Setup DWT */
2146 cortex_m_dwt_free(target);
2147 cortex_m_dwt_setup(cortex_m, target);
2148
2149 /* These hardware breakpoints only work for code in flash! */
2150 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2151 target_name(target),
2152 cortex_m->fp_num_code,
2153 cortex_m->dwt_num_comp);
2154 }
2155
2156 return ERROR_OK;
2157 }
2158
2159 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2160 {
2161 struct armv7m_common *armv7m = target_to_armv7m(target);
2162 uint16_t dcrdr;
2163 uint8_t buf[2];
2164 int retval;
2165
2166 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2167 if (retval != ERROR_OK)
2168 return retval;
2169
2170 dcrdr = target_buffer_get_u16(target, buf);
2171 *ctrl = (uint8_t)dcrdr;
2172 *value = (uint8_t)(dcrdr >> 8);
2173
2174 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2175
2176 /* write ack back to software dcc register
2177 * signify we have read data */
2178 if (dcrdr & (1 << 0)) {
2179 target_buffer_set_u16(target, buf, 0);
2180 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2181 if (retval != ERROR_OK)
2182 return retval;
2183 }
2184
2185 return ERROR_OK;
2186 }
2187
2188 static int cortex_m_target_request_data(struct target *target,
2189 uint32_t size, uint8_t *buffer)
2190 {
2191 uint8_t data;
2192 uint8_t ctrl;
2193 uint32_t i;
2194
2195 for (i = 0; i < (size * 4); i++) {
2196 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2197 if (retval != ERROR_OK)
2198 return retval;
2199 buffer[i] = data;
2200 }
2201
2202 return ERROR_OK;
2203 }
2204
2205 static int cortex_m_handle_target_request(void *priv)
2206 {
2207 struct target *target = priv;
2208 if (!target_was_examined(target))
2209 return ERROR_OK;
2210
2211 if (!target->dbg_msg_enabled)
2212 return ERROR_OK;
2213
2214 if (target->state == TARGET_RUNNING) {
2215 uint8_t data;
2216 uint8_t ctrl;
2217 int retval;
2218
2219 retval = cortex_m_dcc_read(target, &data, &ctrl);
2220 if (retval != ERROR_OK)
2221 return retval;
2222
2223 /* check if we have data */
2224 if (ctrl & (1 << 0)) {
2225 uint32_t request;
2226
2227 /* we assume target is quick enough */
2228 request = data;
2229 for (int i = 1; i <= 3; i++) {
2230 retval = cortex_m_dcc_read(target, &data, &ctrl);
2231 if (retval != ERROR_OK)
2232 return retval;
2233 request |= ((uint32_t)data << (i * 8));
2234 }
2235 target_request(target, request);
2236 }
2237 }
2238
2239 return ERROR_OK;
2240 }
2241
2242 static int cortex_m_init_arch_info(struct target *target,
2243 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2244 {
2245 struct armv7m_common *armv7m = &cortex_m->armv7m;
2246
2247 armv7m_init_arch_info(target, armv7m);
2248
2249 /* default reset mode is to use srst if fitted
2250 * if not it will use CORTEX_M3_RESET_VECTRESET */
2251 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2252
2253 armv7m->arm.dap = dap;
2254
2255 /* register arch-specific functions */
2256 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2257
2258 armv7m->post_debug_entry = NULL;
2259
2260 armv7m->pre_restore_context = NULL;
2261
2262 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2263 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2264
2265 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2266
2267 return ERROR_OK;
2268 }
2269
2270 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2271 {
2272 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2273 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2274 struct adiv5_private_config *pc;
2275
2276 pc = (struct adiv5_private_config *)target->private_config;
2277 if (adiv5_verify_config(pc) != ERROR_OK)
2278 return ERROR_FAIL;
2279
2280 cortex_m->apsel = pc->ap_num;
2281
2282 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2283
2284 return ERROR_OK;
2285 }
2286
2287 /*--------------------------------------------------------------------------*/
2288
2289 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2290 struct cortex_m_common *cm)
2291 {
2292 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2293 command_print(cmd_ctx, "target is not a Cortex-M");
2294 return ERROR_TARGET_INVALID;
2295 }
2296 return ERROR_OK;
2297 }
2298
2299 /*
2300 * Only stuff below this line should need to verify that its target
2301 * is a Cortex-M3. Everything else should have indirected through the
2302 * cortexm3_target structure, which is only used with CM3 targets.
2303 */
2304
2305 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2306 {
2307 struct target *target = get_current_target(CMD_CTX);
2308 struct cortex_m_common *cortex_m = target_to_cm(target);
2309 struct armv7m_common *armv7m = &cortex_m->armv7m;
2310 uint32_t demcr = 0;
2311 int retval;
2312
2313 static const struct {
2314 char name[10];
2315 unsigned mask;
2316 } vec_ids[] = {
2317 { "hard_err", VC_HARDERR, },
2318 { "int_err", VC_INTERR, },
2319 { "bus_err", VC_BUSERR, },
2320 { "state_err", VC_STATERR, },
2321 { "chk_err", VC_CHKERR, },
2322 { "nocp_err", VC_NOCPERR, },
2323 { "mm_err", VC_MMERR, },
2324 { "reset", VC_CORERESET, },
2325 };
2326
2327 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2328 if (retval != ERROR_OK)
2329 return retval;
2330
2331 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2332 if (retval != ERROR_OK)
2333 return retval;
2334
2335 if (CMD_ARGC > 0) {
2336 unsigned catch = 0;
2337
2338 if (CMD_ARGC == 1) {
2339 if (strcmp(CMD_ARGV[0], "all") == 0) {
2340 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2341 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2342 | VC_MMERR | VC_CORERESET;
2343 goto write;
2344 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2345 goto write;
2346 }
2347 while (CMD_ARGC-- > 0) {
2348 unsigned i;
2349 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2350 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2351 continue;
2352 catch |= vec_ids[i].mask;
2353 break;
2354 }
2355 if (i == ARRAY_SIZE(vec_ids)) {
2356 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2357 return ERROR_COMMAND_SYNTAX_ERROR;
2358 }
2359 }
2360 write:
2361 /* For now, armv7m->demcr only stores vector catch flags. */
2362 armv7m->demcr = catch;
2363
2364 demcr &= ~0xffff;
2365 demcr |= catch;
2366
2367 /* write, but don't assume it stuck (why not??) */
2368 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2369 if (retval != ERROR_OK)
2370 return retval;
2371 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2372 if (retval != ERROR_OK)
2373 return retval;
2374
2375 /* FIXME be sure to clear DEMCR on clean server shutdown.
2376 * Otherwise the vector catch hardware could fire when there's
2377 * no debugger hooked up, causing much confusion...
2378 */
2379 }
2380
2381 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2382 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2383 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2384 }
2385
2386 return ERROR_OK;
2387 }
2388
2389 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2390 {
2391 struct target *target = get_current_target(CMD_CTX);
2392 struct cortex_m_common *cortex_m = target_to_cm(target);
2393 int retval;
2394
2395 static const Jim_Nvp nvp_maskisr_modes[] = {
2396 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2397 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2398 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2399 { .name = NULL, .value = -1 },
2400 };
2401 const Jim_Nvp *n;
2402
2403
2404 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2405 if (retval != ERROR_OK)
2406 return retval;
2407
2408 if (target->state != TARGET_HALTED) {
2409 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2410 return ERROR_OK;
2411 }
2412
2413 if (CMD_ARGC > 0) {
2414 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2415 if (n->name == NULL)
2416 return ERROR_COMMAND_SYNTAX_ERROR;
2417 cortex_m->isrmasking_mode = n->value;
2418
2419
2420 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2421 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2422 else
2423 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2424 }
2425
2426 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2427 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2428
2429 return ERROR_OK;
2430 }
2431
2432 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2433 {
2434 struct target *target = get_current_target(CMD_CTX);
2435 struct cortex_m_common *cortex_m = target_to_cm(target);
2436 int retval;
2437 char *reset_config;
2438
2439 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2440 if (retval != ERROR_OK)
2441 return retval;
2442
2443 if (CMD_ARGC > 0) {
2444 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2445 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2446
2447 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2448 if (target_was_examined(target)
2449 && !cortex_m->vectreset_supported)
2450 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2451 else
2452 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2453
2454 } else
2455 return ERROR_COMMAND_SYNTAX_ERROR;
2456 }
2457
2458 switch (cortex_m->soft_reset_config) {
2459 case CORTEX_M_RESET_SYSRESETREQ:
2460 reset_config = "sysresetreq";
2461 break;
2462
2463 case CORTEX_M_RESET_VECTRESET:
2464 reset_config = "vectreset";
2465 break;
2466
2467 default:
2468 reset_config = "unknown";
2469 break;
2470 }
2471
2472 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2473
2474 return ERROR_OK;
2475 }
2476
2477 static const struct command_registration cortex_m_exec_command_handlers[] = {
2478 {
2479 .name = "maskisr",
2480 .handler = handle_cortex_m_mask_interrupts_command,
2481 .mode = COMMAND_EXEC,
2482 .help = "mask cortex_m interrupts",
2483 .usage = "['auto'|'on'|'off']",
2484 },
2485 {
2486 .name = "vector_catch",
2487 .handler = handle_cortex_m_vector_catch_command,
2488 .mode = COMMAND_EXEC,
2489 .help = "configure hardware vectors to trigger debug entry",
2490 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2491 },
2492 {
2493 .name = "reset_config",
2494 .handler = handle_cortex_m_reset_config_command,
2495 .mode = COMMAND_ANY,
2496 .help = "configure software reset handling",
2497 .usage = "['sysresetreq'|'vectreset']",
2498 },
2499 COMMAND_REGISTRATION_DONE
2500 };
2501 static const struct command_registration cortex_m_command_handlers[] = {
2502 {
2503 .chain = armv7m_command_handlers,
2504 },
2505 {
2506 .chain = armv7m_trace_command_handlers,
2507 },
2508 {
2509 .name = "cortex_m",
2510 .mode = COMMAND_EXEC,
2511 .help = "Cortex-M command group",
2512 .usage = "",
2513 .chain = cortex_m_exec_command_handlers,
2514 },
2515 COMMAND_REGISTRATION_DONE
2516 };
2517
2518 struct target_type cortexm_target = {
2519 .name = "cortex_m",
2520 .deprecated_name = "cortex_m3",
2521
2522 .poll = cortex_m_poll,
2523 .arch_state = armv7m_arch_state,
2524
2525 .target_request_data = cortex_m_target_request_data,
2526
2527 .halt = cortex_m_halt,
2528 .resume = cortex_m_resume,
2529 .step = cortex_m_step,
2530
2531 .assert_reset = cortex_m_assert_reset,
2532 .deassert_reset = cortex_m_deassert_reset,
2533 .soft_reset_halt = cortex_m_soft_reset_halt,
2534
2535 .get_gdb_arch = arm_get_gdb_arch,
2536 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2537
2538 .read_memory = cortex_m_read_memory,
2539 .write_memory = cortex_m_write_memory,
2540 .checksum_memory = armv7m_checksum_memory,
2541 .blank_check_memory = armv7m_blank_check_memory,
2542
2543 .run_algorithm = armv7m_run_algorithm,
2544 .start_algorithm = armv7m_start_algorithm,
2545 .wait_algorithm = armv7m_wait_algorithm,
2546
2547 .add_breakpoint = cortex_m_add_breakpoint,
2548 .remove_breakpoint = cortex_m_remove_breakpoint,
2549 .add_watchpoint = cortex_m_add_watchpoint,
2550 .remove_watchpoint = cortex_m_remove_watchpoint,
2551
2552 .commands = cortex_m_command_handlers,
2553 .target_create = cortex_m_target_create,
2554 .target_jim_configure = adiv5_jim_configure,
2555 .init_target = cortex_m_init_target,
2556 .examine = cortex_m_examine,
2557 .deinit_target = cortex_m_deinit_target,
2558
2559 .profiling = cortex_m_profiling,
2560 };
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