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[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_clear_halt(struct target *target)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 struct armv7m_common *armv7m = &cortex_m->armv7m;
143 int retval;
144
145 /* clear step if any */
146 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
147
148 /* Read Debug Fault Status Register */
149 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
150 if (retval != ERROR_OK)
151 return retval;
152
153 /* Clear Debug Fault Status */
154 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
155 if (retval != ERROR_OK)
156 return retval;
157 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
158
159 return ERROR_OK;
160 }
161
162 static int cortex_m_single_step_core(struct target *target)
163 {
164 struct cortex_m_common *cortex_m = target_to_cm(target);
165 struct armv7m_common *armv7m = &cortex_m->armv7m;
166 int retval;
167
168 /* Mask interrupts before clearing halt, if not done already. This avoids
169 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
170 * HALT can put the core into an unknown state.
171 */
172 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
174 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
175 if (retval != ERROR_OK)
176 return retval;
177 }
178 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
179 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
180 if (retval != ERROR_OK)
181 return retval;
182 LOG_DEBUG(" ");
183
184 /* restore dhcsr reg */
185 cortex_m_clear_halt(target);
186
187 return ERROR_OK;
188 }
189
190 static int cortex_m_enable_fpb(struct target *target)
191 {
192 int retval = target_write_u32(target, FP_CTRL, 3);
193 if (retval != ERROR_OK)
194 return retval;
195
196 /* check the fpb is actually enabled */
197 uint32_t fpctrl;
198 retval = target_read_u32(target, FP_CTRL, &fpctrl);
199 if (retval != ERROR_OK)
200 return retval;
201
202 if (fpctrl & 1)
203 return ERROR_OK;
204
205 return ERROR_FAIL;
206 }
207
208 static int cortex_m_endreset_event(struct target *target)
209 {
210 int i;
211 int retval;
212 uint32_t dcb_demcr;
213 struct cortex_m_common *cortex_m = target_to_cm(target);
214 struct armv7m_common *armv7m = &cortex_m->armv7m;
215 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
216 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
217 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
218
219 /* REVISIT The four debug monitor bits are currently ignored... */
220 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
221 if (retval != ERROR_OK)
222 return retval;
223 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
224
225 /* this register is used for emulated dcc channel */
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enable debug requests */
231 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
232 if (retval != ERROR_OK)
233 return retval;
234 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
235 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 /* Restore proper interrupt masking setting. */
241 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
242 cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
243 else
244 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
245
246 /* Enable features controlled by ITM and DWT blocks, and catch only
247 * the vectors we were told to pay attention to.
248 *
249 * Target firmware is responsible for all fault handling policy
250 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
251 * or manual updates to the NVIC SHCSR and CCR registers.
252 */
253 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
254 if (retval != ERROR_OK)
255 return retval;
256
257 /* Paranoia: evidently some (early?) chips don't preserve all the
258 * debug state (including FPB, DWT, etc) across reset...
259 */
260
261 /* Enable FPB */
262 retval = cortex_m_enable_fpb(target);
263 if (retval != ERROR_OK) {
264 LOG_ERROR("Failed to enable the FPB");
265 return retval;
266 }
267
268 cortex_m->fpb_enabled = 1;
269
270 /* Restore FPB registers */
271 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
272 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
273 if (retval != ERROR_OK)
274 return retval;
275 }
276
277 /* Restore DWT registers */
278 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
279 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
280 dwt_list[i].comp);
281 if (retval != ERROR_OK)
282 return retval;
283 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
284 dwt_list[i].mask);
285 if (retval != ERROR_OK)
286 return retval;
287 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
288 dwt_list[i].function);
289 if (retval != ERROR_OK)
290 return retval;
291 }
292 retval = dap_run(swjdp);
293 if (retval != ERROR_OK)
294 return retval;
295
296 register_cache_invalidate(armv7m->arm.core_cache);
297
298 /* make sure we have latest dhcsr flags */
299 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
300
301 return retval;
302 }
303
304 static int cortex_m_examine_debug_reason(struct target *target)
305 {
306 struct cortex_m_common *cortex_m = target_to_cm(target);
307
308 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
309 * only check the debug reason if we don't know it already */
310
311 if ((target->debug_reason != DBG_REASON_DBGRQ)
312 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
313 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
314 target->debug_reason = DBG_REASON_BREAKPOINT;
315 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
316 target->debug_reason = DBG_REASON_WPTANDBKPT;
317 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
318 target->debug_reason = DBG_REASON_WATCHPOINT;
319 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
320 target->debug_reason = DBG_REASON_BREAKPOINT;
321 else /* EXTERNAL, HALTED */
322 target->debug_reason = DBG_REASON_UNDEFINED;
323 }
324
325 return ERROR_OK;
326 }
327
328 static int cortex_m_examine_exception_reason(struct target *target)
329 {
330 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
331 struct armv7m_common *armv7m = target_to_armv7m(target);
332 struct adiv5_dap *swjdp = armv7m->arm.dap;
333 int retval;
334
335 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
336 if (retval != ERROR_OK)
337 return retval;
338 switch (armv7m->exception_number) {
339 case 2: /* NMI */
340 break;
341 case 3: /* Hard Fault */
342 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
343 if (retval != ERROR_OK)
344 return retval;
345 if (except_sr & 0x40000000) {
346 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350 break;
351 case 4: /* Memory Management */
352 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
353 if (retval != ERROR_OK)
354 return retval;
355 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
356 if (retval != ERROR_OK)
357 return retval;
358 break;
359 case 5: /* Bus Fault */
360 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
361 if (retval != ERROR_OK)
362 return retval;
363 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
364 if (retval != ERROR_OK)
365 return retval;
366 break;
367 case 6: /* Usage Fault */
368 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
369 if (retval != ERROR_OK)
370 return retval;
371 break;
372 case 11: /* SVCall */
373 break;
374 case 12: /* Debug Monitor */
375 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
376 if (retval != ERROR_OK)
377 return retval;
378 break;
379 case 14: /* PendSV */
380 break;
381 case 15: /* SysTick */
382 break;
383 default:
384 except_sr = 0;
385 break;
386 }
387 retval = dap_run(swjdp);
388 if (retval == ERROR_OK)
389 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
390 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
391 armv7m_exception_string(armv7m->exception_number),
392 shcsr, except_sr, cfsr, except_ar);
393 return retval;
394 }
395
396 static int cortex_m_debug_entry(struct target *target)
397 {
398 int i;
399 uint32_t xPSR;
400 int retval;
401 struct cortex_m_common *cortex_m = target_to_cm(target);
402 struct armv7m_common *armv7m = &cortex_m->armv7m;
403 struct arm *arm = &armv7m->arm;
404 struct reg *r;
405
406 LOG_DEBUG(" ");
407
408 cortex_m_clear_halt(target);
409 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
410 if (retval != ERROR_OK)
411 return retval;
412
413 retval = armv7m->examine_debug_reason(target);
414 if (retval != ERROR_OK)
415 return retval;
416
417 /* Examine target state and mode
418 * First load register accessible through core debug port */
419 int num_regs = arm->core_cache->num_regs;
420
421 for (i = 0; i < num_regs; i++) {
422 r = &armv7m->arm.core_cache->reg_list[i];
423 if (!r->valid)
424 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
425 }
426
427 r = arm->cpsr;
428 xPSR = buf_get_u32(r->value, 0, 32);
429
430 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
431 if (xPSR & 0xf00) {
432 r->dirty = r->valid;
433 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
434 }
435
436 /* Are we in an exception handler */
437 if (xPSR & 0x1FF) {
438 armv7m->exception_number = (xPSR & 0x1FF);
439
440 arm->core_mode = ARM_MODE_HANDLER;
441 arm->map = armv7m_msp_reg_map;
442 } else {
443 unsigned control = buf_get_u32(arm->core_cache
444 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
445
446 /* is this thread privileged? */
447 arm->core_mode = control & 1
448 ? ARM_MODE_USER_THREAD
449 : ARM_MODE_THREAD;
450
451 /* which stack is it using? */
452 if (control & 2)
453 arm->map = armv7m_psp_reg_map;
454 else
455 arm->map = armv7m_msp_reg_map;
456
457 armv7m->exception_number = 0;
458 }
459
460 if (armv7m->exception_number)
461 cortex_m_examine_exception_reason(target);
462
463 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
464 arm_mode_name(arm->core_mode),
465 buf_get_u32(arm->pc->value, 0, 32),
466 target_state_name(target));
467
468 if (armv7m->post_debug_entry) {
469 retval = armv7m->post_debug_entry(target);
470 if (retval != ERROR_OK)
471 return retval;
472 }
473
474 return ERROR_OK;
475 }
476
477 static int cortex_m_poll(struct target *target)
478 {
479 int detected_failure = ERROR_OK;
480 int retval = ERROR_OK;
481 enum target_state prev_target_state = target->state;
482 struct cortex_m_common *cortex_m = target_to_cm(target);
483 struct armv7m_common *armv7m = &cortex_m->armv7m;
484
485 /* Read from Debug Halting Control and Status Register */
486 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
487 if (retval != ERROR_OK) {
488 target->state = TARGET_UNKNOWN;
489 return retval;
490 }
491
492 /* Recover from lockup. See ARMv7-M architecture spec,
493 * section B1.5.15 "Unrecoverable exception cases".
494 */
495 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
496 LOG_ERROR("%s -- clearing lockup after double fault",
497 target_name(target));
498 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
499 target->debug_reason = DBG_REASON_DBGRQ;
500
501 /* We have to execute the rest (the "finally" equivalent, but
502 * still throw this exception again).
503 */
504 detected_failure = ERROR_FAIL;
505
506 /* refresh status bits */
507 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
508 if (retval != ERROR_OK)
509 return retval;
510 }
511
512 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
513 target->state = TARGET_RESET;
514 return ERROR_OK;
515 }
516
517 if (target->state == TARGET_RESET) {
518 /* Cannot switch context while running so endreset is
519 * called with target->state == TARGET_RESET
520 */
521 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
522 cortex_m->dcb_dhcsr);
523 retval = cortex_m_endreset_event(target);
524 if (retval != ERROR_OK) {
525 target->state = TARGET_UNKNOWN;
526 return retval;
527 }
528 target->state = TARGET_RUNNING;
529 prev_target_state = TARGET_RUNNING;
530 }
531
532 if (cortex_m->dcb_dhcsr & S_HALT) {
533 target->state = TARGET_HALTED;
534
535 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
536 retval = cortex_m_debug_entry(target);
537 if (retval != ERROR_OK)
538 return retval;
539
540 if (arm_semihosting(target, &retval) != 0)
541 return retval;
542
543 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
544 }
545 if (prev_target_state == TARGET_DEBUG_RUNNING) {
546 LOG_DEBUG(" ");
547 retval = cortex_m_debug_entry(target);
548 if (retval != ERROR_OK)
549 return retval;
550
551 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
552 }
553 }
554
555 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
556 * How best to model low power modes?
557 */
558
559 if (target->state == TARGET_UNKNOWN) {
560 /* check if processor is retiring instructions */
561 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
562 target->state = TARGET_RUNNING;
563 retval = ERROR_OK;
564 }
565 }
566
567 /* Did we detect a failure condition that we cleared? */
568 if (detected_failure != ERROR_OK)
569 retval = detected_failure;
570 return retval;
571 }
572
573 static int cortex_m_halt(struct target *target)
574 {
575 LOG_DEBUG("target->state: %s",
576 target_state_name(target));
577
578 if (target->state == TARGET_HALTED) {
579 LOG_DEBUG("target was already halted");
580 return ERROR_OK;
581 }
582
583 if (target->state == TARGET_UNKNOWN)
584 LOG_WARNING("target was in unknown state when halt was requested");
585
586 if (target->state == TARGET_RESET) {
587 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
588 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
589 return ERROR_TARGET_FAILURE;
590 } else {
591 /* we came here in a reset_halt or reset_init sequence
592 * debug entry was already prepared in cortex_m3_assert_reset()
593 */
594 target->debug_reason = DBG_REASON_DBGRQ;
595
596 return ERROR_OK;
597 }
598 }
599
600 /* Write to Debug Halting Control and Status Register */
601 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
602
603 target->debug_reason = DBG_REASON_DBGRQ;
604
605 return ERROR_OK;
606 }
607
608 static int cortex_m_soft_reset_halt(struct target *target)
609 {
610 struct cortex_m_common *cortex_m = target_to_cm(target);
611 struct armv7m_common *armv7m = &cortex_m->armv7m;
612 uint32_t dcb_dhcsr = 0;
613 int retval, timeout = 0;
614
615 /* soft_reset_halt is deprecated on cortex_m as the same functionality
616 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
617 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
618 * core, not the peripherals */
619 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
620
621 /* Enter debug state on reset; restore DEMCR in endreset_event() */
622 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
623 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
624 if (retval != ERROR_OK)
625 return retval;
626
627 /* Request a core-only reset */
628 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
629 AIRCR_VECTKEY | AIRCR_VECTRESET);
630 if (retval != ERROR_OK)
631 return retval;
632 target->state = TARGET_RESET;
633
634 /* registers are now invalid */
635 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
636
637 while (timeout < 100) {
638 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
639 if (retval == ERROR_OK) {
640 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
641 &cortex_m->nvic_dfsr);
642 if (retval != ERROR_OK)
643 return retval;
644 if ((dcb_dhcsr & S_HALT)
645 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
646 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
647 "DFSR 0x%08x",
648 (unsigned) dcb_dhcsr,
649 (unsigned) cortex_m->nvic_dfsr);
650 cortex_m_poll(target);
651 /* FIXME restore user's vector catch config */
652 return ERROR_OK;
653 } else
654 LOG_DEBUG("waiting for system reset-halt, "
655 "DHCSR 0x%08x, %d ms",
656 (unsigned) dcb_dhcsr, timeout);
657 }
658 timeout++;
659 alive_sleep(1);
660 }
661
662 return ERROR_OK;
663 }
664
665 void cortex_m_enable_breakpoints(struct target *target)
666 {
667 struct breakpoint *breakpoint = target->breakpoints;
668
669 /* set any pending breakpoints */
670 while (breakpoint) {
671 if (!breakpoint->set)
672 cortex_m_set_breakpoint(target, breakpoint);
673 breakpoint = breakpoint->next;
674 }
675 }
676
677 static int cortex_m_resume(struct target *target, int current,
678 target_addr_t address, int handle_breakpoints, int debug_execution)
679 {
680 struct armv7m_common *armv7m = target_to_armv7m(target);
681 struct breakpoint *breakpoint = NULL;
682 uint32_t resume_pc;
683 struct reg *r;
684
685 if (target->state != TARGET_HALTED) {
686 LOG_WARNING("target not halted");
687 return ERROR_TARGET_NOT_HALTED;
688 }
689
690 if (!debug_execution) {
691 target_free_all_working_areas(target);
692 cortex_m_enable_breakpoints(target);
693 cortex_m_enable_watchpoints(target);
694 }
695
696 if (debug_execution) {
697 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
698
699 /* Disable interrupts */
700 /* We disable interrupts in the PRIMASK register instead of
701 * masking with C_MASKINTS. This is probably the same issue
702 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
703 * in parallel with disabled interrupts can cause local faults
704 * to not be taken.
705 *
706 * REVISIT this clearly breaks non-debug execution, since the
707 * PRIMASK register state isn't saved/restored... workaround
708 * by never resuming app code after debug execution.
709 */
710 buf_set_u32(r->value, 0, 1, 1);
711 r->dirty = true;
712 r->valid = true;
713
714 /* Make sure we are in Thumb mode */
715 r = armv7m->arm.cpsr;
716 buf_set_u32(r->value, 24, 1, 1);
717 r->dirty = true;
718 r->valid = true;
719 }
720
721 /* current = 1: continue on current pc, otherwise continue at <address> */
722 r = armv7m->arm.pc;
723 if (!current) {
724 buf_set_u32(r->value, 0, 32, address);
725 r->dirty = true;
726 r->valid = true;
727 }
728
729 /* if we halted last time due to a bkpt instruction
730 * then we have to manually step over it, otherwise
731 * the core will break again */
732
733 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
734 && !debug_execution)
735 armv7m_maybe_skip_bkpt_inst(target, NULL);
736
737 resume_pc = buf_get_u32(r->value, 0, 32);
738
739 armv7m_restore_context(target);
740
741 /* the front-end may request us not to handle breakpoints */
742 if (handle_breakpoints) {
743 /* Single step past breakpoint at current address */
744 breakpoint = breakpoint_find(target, resume_pc);
745 if (breakpoint) {
746 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
747 breakpoint->address,
748 breakpoint->unique_id);
749 cortex_m_unset_breakpoint(target, breakpoint);
750 cortex_m_single_step_core(target);
751 cortex_m_set_breakpoint(target, breakpoint);
752 }
753 }
754
755 /* Restart core */
756 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
757
758 target->debug_reason = DBG_REASON_NOTHALTED;
759
760 /* registers are now invalid */
761 register_cache_invalidate(armv7m->arm.core_cache);
762
763 if (!debug_execution) {
764 target->state = TARGET_RUNNING;
765 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
766 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
767 } else {
768 target->state = TARGET_DEBUG_RUNNING;
769 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
770 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
771 }
772
773 return ERROR_OK;
774 }
775
776 /* int irqstepcount = 0; */
777 static int cortex_m_step(struct target *target, int current,
778 target_addr_t address, int handle_breakpoints)
779 {
780 struct cortex_m_common *cortex_m = target_to_cm(target);
781 struct armv7m_common *armv7m = &cortex_m->armv7m;
782 struct breakpoint *breakpoint = NULL;
783 struct reg *pc = armv7m->arm.pc;
784 bool bkpt_inst_found = false;
785 int retval;
786 bool isr_timed_out = false;
787
788 if (target->state != TARGET_HALTED) {
789 LOG_WARNING("target not halted");
790 return ERROR_TARGET_NOT_HALTED;
791 }
792
793 /* current = 1: continue on current pc, otherwise continue at <address> */
794 if (!current)
795 buf_set_u32(pc->value, 0, 32, address);
796
797 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
798
799 /* the front-end may request us not to handle breakpoints */
800 if (handle_breakpoints) {
801 breakpoint = breakpoint_find(target, pc_value);
802 if (breakpoint)
803 cortex_m_unset_breakpoint(target, breakpoint);
804 }
805
806 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
807
808 target->debug_reason = DBG_REASON_SINGLESTEP;
809
810 armv7m_restore_context(target);
811
812 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
813
814 /* if no bkpt instruction is found at pc then we can perform
815 * a normal step, otherwise we have to manually step over the bkpt
816 * instruction - as such simulate a step */
817 if (bkpt_inst_found == false) {
818 /* Automatic ISR masking mode off: Just step over the next instruction */
819 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
820 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
821 else {
822 /* Process interrupts during stepping in a way they don't interfere
823 * debugging.
824 *
825 * Principle:
826 *
827 * Set a temporary break point at the current pc and let the core run
828 * with interrupts enabled. Pending interrupts get served and we run
829 * into the breakpoint again afterwards. Then we step over the next
830 * instruction with interrupts disabled.
831 *
832 * If the pending interrupts don't complete within time, we leave the
833 * core running. This may happen if the interrupts trigger faster
834 * than the core can process them or the handler doesn't return.
835 *
836 * If no more breakpoints are available we simply do a step with
837 * interrupts enabled.
838 *
839 */
840
841 /* 2012-09-29 ph
842 *
843 * If a break point is already set on the lower half word then a break point on
844 * the upper half word will not break again when the core is restarted. So we
845 * just step over the instruction with interrupts disabled.
846 *
847 * The documentation has no information about this, it was found by observation
848 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
849 * suffer from this problem.
850 *
851 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
852 * address has it always cleared. The former is done to indicate thumb mode
853 * to gdb.
854 *
855 */
856 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
857 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
858 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
859 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
860 /* Re-enable interrupts */
861 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
862 }
863 else {
864
865 /* Set a temporary break point */
866 if (breakpoint)
867 retval = cortex_m_set_breakpoint(target, breakpoint);
868 else
869 retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
870 bool tmp_bp_set = (retval == ERROR_OK);
871
872 /* No more breakpoints left, just do a step */
873 if (!tmp_bp_set)
874 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
875 else {
876 /* Start the core */
877 LOG_DEBUG("Starting core to serve pending interrupts");
878 int64_t t_start = timeval_ms();
879 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
880
881 /* Wait for pending handlers to complete or timeout */
882 do {
883 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
884 DCB_DHCSR,
885 &cortex_m->dcb_dhcsr);
886 if (retval != ERROR_OK) {
887 target->state = TARGET_UNKNOWN;
888 return retval;
889 }
890 isr_timed_out = ((timeval_ms() - t_start) > 500);
891 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
892
893 /* only remove breakpoint if we created it */
894 if (breakpoint)
895 cortex_m_unset_breakpoint(target, breakpoint);
896 else {
897 /* Remove the temporary breakpoint */
898 breakpoint_remove(target, pc_value);
899 }
900
901 if (isr_timed_out) {
902 LOG_DEBUG("Interrupt handlers didn't complete within time, "
903 "leaving target running");
904 } else {
905 /* Step over next instruction with interrupts disabled */
906 cortex_m_write_debug_halt_mask(target,
907 C_HALT | C_MASKINTS,
908 0);
909 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
910 /* Re-enable interrupts */
911 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
912 }
913 }
914 }
915 }
916 }
917
918 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
919 if (retval != ERROR_OK)
920 return retval;
921
922 /* registers are now invalid */
923 register_cache_invalidate(armv7m->arm.core_cache);
924
925 if (breakpoint)
926 cortex_m_set_breakpoint(target, breakpoint);
927
928 if (isr_timed_out) {
929 /* Leave the core running. The user has to stop execution manually. */
930 target->debug_reason = DBG_REASON_NOTHALTED;
931 target->state = TARGET_RUNNING;
932 return ERROR_OK;
933 }
934
935 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
936 " nvic_icsr = 0x%" PRIx32,
937 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
938
939 retval = cortex_m_debug_entry(target);
940 if (retval != ERROR_OK)
941 return retval;
942 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
943
944 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
945 " nvic_icsr = 0x%" PRIx32,
946 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
947
948 return ERROR_OK;
949 }
950
951 static int cortex_m_assert_reset(struct target *target)
952 {
953 struct cortex_m_common *cortex_m = target_to_cm(target);
954 struct armv7m_common *armv7m = &cortex_m->armv7m;
955 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
956
957 LOG_DEBUG("target->state: %s",
958 target_state_name(target));
959
960 enum reset_types jtag_reset_config = jtag_get_reset_config();
961
962 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
963 /* allow scripts to override the reset event */
964
965 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
966 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
967 target->state = TARGET_RESET;
968
969 return ERROR_OK;
970 }
971
972 /* some cores support connecting while srst is asserted
973 * use that mode is it has been configured */
974
975 bool srst_asserted = false;
976
977 if (!target_was_examined(target)) {
978 if (jtag_reset_config & RESET_HAS_SRST) {
979 adapter_assert_reset();
980 if (target->reset_halt)
981 LOG_ERROR("Target not examined, will not halt after reset!");
982 return ERROR_OK;
983 } else {
984 LOG_ERROR("Target not examined, reset NOT asserted!");
985 return ERROR_FAIL;
986 }
987 }
988
989 if ((jtag_reset_config & RESET_HAS_SRST) &&
990 (jtag_reset_config & RESET_SRST_NO_GATING)) {
991 adapter_assert_reset();
992 srst_asserted = true;
993 }
994
995 /* Enable debug requests */
996 int retval;
997 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
998 /* Store important errors instead of failing and proceed to reset assert */
999
1000 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1001 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1002
1003 /* If the processor is sleeping in a WFI or WFE instruction, the
1004 * C_HALT bit must be asserted to regain control */
1005 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1006 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1007
1008 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1009 /* Ignore less important errors */
1010
1011 if (!target->reset_halt) {
1012 /* Set/Clear C_MASKINTS in a separate operation */
1013 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1014 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1015
1016 /* clear any debug flags before resuming */
1017 cortex_m_clear_halt(target);
1018
1019 /* clear C_HALT in dhcsr reg */
1020 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1021 } else {
1022 /* Halt in debug on reset; endreset_event() restores DEMCR.
1023 *
1024 * REVISIT catching BUSERR presumably helps to defend against
1025 * bad vector table entries. Should this include MMERR or
1026 * other flags too?
1027 */
1028 int retval2;
1029 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1030 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1031 if (retval != ERROR_OK || retval2 != ERROR_OK)
1032 LOG_INFO("AP write error, reset will not halt");
1033 }
1034
1035 if (jtag_reset_config & RESET_HAS_SRST) {
1036 /* default to asserting srst */
1037 if (!srst_asserted)
1038 adapter_assert_reset();
1039
1040 /* srst is asserted, ignore AP access errors */
1041 retval = ERROR_OK;
1042 } else {
1043 /* Use a standard Cortex-M3 software reset mechanism.
1044 * We default to using VECRESET as it is supported on all current cores
1045 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1046 * This has the disadvantage of not resetting the peripherals, so a
1047 * reset-init event handler is needed to perform any peripheral resets.
1048 */
1049 if (!cortex_m->vectreset_supported
1050 && reset_config == CORTEX_M_RESET_VECTRESET) {
1051 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1052 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1053 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1054 }
1055
1056 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1057 ? "SYSRESETREQ" : "VECTRESET");
1058
1059 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1060 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1061 "handler to reset any peripherals or configure hardware srst support.");
1062 }
1063
1064 int retval3;
1065 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1066 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1067 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1068 if (retval3 != ERROR_OK)
1069 LOG_DEBUG("Ignoring AP write error right after reset");
1070
1071 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1072 if (retval3 != ERROR_OK)
1073 LOG_ERROR("DP initialisation failed");
1074
1075 else {
1076 /* I do not know why this is necessary, but it
1077 * fixes strange effects (step/resume cause NMI
1078 * after reset) on LM3S6918 -- Michael Schwingen
1079 */
1080 uint32_t tmp;
1081 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1082 }
1083 }
1084
1085 target->state = TARGET_RESET;
1086 jtag_add_sleep(50000);
1087
1088 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1089
1090 /* now return stored error code if any */
1091 if (retval != ERROR_OK)
1092 return retval;
1093
1094 if (target->reset_halt) {
1095 retval = target_halt(target);
1096 if (retval != ERROR_OK)
1097 return retval;
1098 }
1099
1100 return ERROR_OK;
1101 }
1102
1103 static int cortex_m_deassert_reset(struct target *target)
1104 {
1105 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1106
1107 LOG_DEBUG("target->state: %s",
1108 target_state_name(target));
1109
1110 /* deassert reset lines */
1111 adapter_deassert_reset();
1112
1113 enum reset_types jtag_reset_config = jtag_get_reset_config();
1114
1115 if ((jtag_reset_config & RESET_HAS_SRST) &&
1116 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1117 target_was_examined(target)) {
1118 int retval = dap_dp_init(armv7m->debug_ap->dap);
1119 if (retval != ERROR_OK) {
1120 LOG_ERROR("DP initialisation failed");
1121 return retval;
1122 }
1123 }
1124
1125 return ERROR_OK;
1126 }
1127
1128 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1129 {
1130 int retval;
1131 int fp_num = 0;
1132 struct cortex_m_common *cortex_m = target_to_cm(target);
1133 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1134
1135 if (breakpoint->set) {
1136 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1137 return ERROR_OK;
1138 }
1139
1140 if (breakpoint->type == BKPT_HARD) {
1141 uint32_t fpcr_value;
1142 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1143 fp_num++;
1144 if (fp_num >= cortex_m->fp_num_code) {
1145 LOG_ERROR("Can not find free FPB Comparator!");
1146 return ERROR_FAIL;
1147 }
1148 breakpoint->set = fp_num + 1;
1149 fpcr_value = breakpoint->address | 1;
1150 if (cortex_m->fp_rev == 0) {
1151 if (breakpoint->address > 0x1FFFFFFF) {
1152 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1153 return ERROR_FAIL;
1154 }
1155 uint32_t hilo;
1156 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1157 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1158 } else if (cortex_m->fp_rev > 1) {
1159 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1160 return ERROR_FAIL;
1161 }
1162 comparator_list[fp_num].used = 1;
1163 comparator_list[fp_num].fpcr_value = fpcr_value;
1164 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1165 comparator_list[fp_num].fpcr_value);
1166 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1167 fp_num,
1168 comparator_list[fp_num].fpcr_value);
1169 if (!cortex_m->fpb_enabled) {
1170 LOG_DEBUG("FPB wasn't enabled, do it now");
1171 retval = cortex_m_enable_fpb(target);
1172 if (retval != ERROR_OK) {
1173 LOG_ERROR("Failed to enable the FPB");
1174 return retval;
1175 }
1176
1177 cortex_m->fpb_enabled = 1;
1178 }
1179 } else if (breakpoint->type == BKPT_SOFT) {
1180 uint8_t code[4];
1181
1182 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1183 * semihosting; don't use that. Otherwise the BKPT
1184 * parameter is arbitrary.
1185 */
1186 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1187 retval = target_read_memory(target,
1188 breakpoint->address & 0xFFFFFFFE,
1189 breakpoint->length, 1,
1190 breakpoint->orig_instr);
1191 if (retval != ERROR_OK)
1192 return retval;
1193 retval = target_write_memory(target,
1194 breakpoint->address & 0xFFFFFFFE,
1195 breakpoint->length, 1,
1196 code);
1197 if (retval != ERROR_OK)
1198 return retval;
1199 breakpoint->set = true;
1200 }
1201
1202 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1203 breakpoint->unique_id,
1204 (int)(breakpoint->type),
1205 breakpoint->address,
1206 breakpoint->length,
1207 breakpoint->set);
1208
1209 return ERROR_OK;
1210 }
1211
1212 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1213 {
1214 int retval;
1215 struct cortex_m_common *cortex_m = target_to_cm(target);
1216 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1217
1218 if (!breakpoint->set) {
1219 LOG_WARNING("breakpoint not set");
1220 return ERROR_OK;
1221 }
1222
1223 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1224 breakpoint->unique_id,
1225 (int)(breakpoint->type),
1226 breakpoint->address,
1227 breakpoint->length,
1228 breakpoint->set);
1229
1230 if (breakpoint->type == BKPT_HARD) {
1231 int fp_num = breakpoint->set - 1;
1232 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1233 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1234 return ERROR_OK;
1235 }
1236 comparator_list[fp_num].used = 0;
1237 comparator_list[fp_num].fpcr_value = 0;
1238 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1239 comparator_list[fp_num].fpcr_value);
1240 } else {
1241 /* restore original instruction (kept in target endianness) */
1242 if (breakpoint->length == 4) {
1243 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1244 breakpoint->orig_instr);
1245 if (retval != ERROR_OK)
1246 return retval;
1247 } else {
1248 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1249 breakpoint->orig_instr);
1250 if (retval != ERROR_OK)
1251 return retval;
1252 }
1253 }
1254 breakpoint->set = false;
1255
1256 return ERROR_OK;
1257 }
1258
1259 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1260 {
1261 struct cortex_m_common *cortex_m = target_to_cm(target);
1262
1263 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1264 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1265 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1266 }
1267
1268 if (breakpoint->length == 3) {
1269 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1270 breakpoint->length = 2;
1271 }
1272
1273 if ((breakpoint->length != 2)) {
1274 LOG_INFO("only breakpoints of two bytes length supported");
1275 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1276 }
1277
1278 if (breakpoint->type == BKPT_HARD)
1279 cortex_m->fp_code_available--;
1280
1281 return cortex_m_set_breakpoint(target, breakpoint);
1282 }
1283
1284 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1285 {
1286 struct cortex_m_common *cortex_m = target_to_cm(target);
1287
1288 /* REVISIT why check? FPB can be updated with core running ... */
1289 if (target->state != TARGET_HALTED) {
1290 LOG_WARNING("target not halted");
1291 return ERROR_TARGET_NOT_HALTED;
1292 }
1293
1294 if (breakpoint->set)
1295 cortex_m_unset_breakpoint(target, breakpoint);
1296
1297 if (breakpoint->type == BKPT_HARD)
1298 cortex_m->fp_code_available++;
1299
1300 return ERROR_OK;
1301 }
1302
1303 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1304 {
1305 int dwt_num = 0;
1306 uint32_t mask, temp;
1307 struct cortex_m_common *cortex_m = target_to_cm(target);
1308
1309 /* watchpoint params were validated earlier */
1310 mask = 0;
1311 temp = watchpoint->length;
1312 while (temp) {
1313 temp >>= 1;
1314 mask++;
1315 }
1316 mask--;
1317
1318 /* REVISIT Don't fully trust these "not used" records ... users
1319 * may set up breakpoints by hand, e.g. dual-address data value
1320 * watchpoint using comparator #1; comparator #0 matching cycle
1321 * count; send data trace info through ITM and TPIU; etc
1322 */
1323 struct cortex_m_dwt_comparator *comparator;
1324
1325 for (comparator = cortex_m->dwt_comparator_list;
1326 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1327 comparator++, dwt_num++)
1328 continue;
1329 if (dwt_num >= cortex_m->dwt_num_comp) {
1330 LOG_ERROR("Can not find free DWT Comparator");
1331 return ERROR_FAIL;
1332 }
1333 comparator->used = 1;
1334 watchpoint->set = dwt_num + 1;
1335
1336 comparator->comp = watchpoint->address;
1337 target_write_u32(target, comparator->dwt_comparator_address + 0,
1338 comparator->comp);
1339
1340 comparator->mask = mask;
1341 target_write_u32(target, comparator->dwt_comparator_address + 4,
1342 comparator->mask);
1343
1344 switch (watchpoint->rw) {
1345 case WPT_READ:
1346 comparator->function = 5;
1347 break;
1348 case WPT_WRITE:
1349 comparator->function = 6;
1350 break;
1351 case WPT_ACCESS:
1352 comparator->function = 7;
1353 break;
1354 }
1355 target_write_u32(target, comparator->dwt_comparator_address + 8,
1356 comparator->function);
1357
1358 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1359 watchpoint->unique_id, dwt_num,
1360 (unsigned) comparator->comp,
1361 (unsigned) comparator->mask,
1362 (unsigned) comparator->function);
1363 return ERROR_OK;
1364 }
1365
1366 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1367 {
1368 struct cortex_m_common *cortex_m = target_to_cm(target);
1369 struct cortex_m_dwt_comparator *comparator;
1370 int dwt_num;
1371
1372 if (!watchpoint->set) {
1373 LOG_WARNING("watchpoint (wpid: %d) not set",
1374 watchpoint->unique_id);
1375 return ERROR_OK;
1376 }
1377
1378 dwt_num = watchpoint->set - 1;
1379
1380 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1381 watchpoint->unique_id, dwt_num,
1382 (unsigned) watchpoint->address);
1383
1384 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1385 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1386 return ERROR_OK;
1387 }
1388
1389 comparator = cortex_m->dwt_comparator_list + dwt_num;
1390 comparator->used = 0;
1391 comparator->function = 0;
1392 target_write_u32(target, comparator->dwt_comparator_address + 8,
1393 comparator->function);
1394
1395 watchpoint->set = false;
1396
1397 return ERROR_OK;
1398 }
1399
1400 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1401 {
1402 struct cortex_m_common *cortex_m = target_to_cm(target);
1403
1404 if (cortex_m->dwt_comp_available < 1) {
1405 LOG_DEBUG("no comparators?");
1406 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1407 }
1408
1409 /* hardware doesn't support data value masking */
1410 if (watchpoint->mask != ~(uint32_t)0) {
1411 LOG_DEBUG("watchpoint value masks not supported");
1412 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1413 }
1414
1415 /* hardware allows address masks of up to 32K */
1416 unsigned mask;
1417
1418 for (mask = 0; mask < 16; mask++) {
1419 if ((1u << mask) == watchpoint->length)
1420 break;
1421 }
1422 if (mask == 16) {
1423 LOG_DEBUG("unsupported watchpoint length");
1424 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1425 }
1426 if (watchpoint->address & ((1 << mask) - 1)) {
1427 LOG_DEBUG("watchpoint address is unaligned");
1428 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1429 }
1430
1431 /* Caller doesn't seem to be able to describe watching for data
1432 * values of zero; that flags "no value".
1433 *
1434 * REVISIT This DWT may well be able to watch for specific data
1435 * values. Requires comparator #1 to set DATAVMATCH and match
1436 * the data, and another comparator (DATAVADDR0) matching addr.
1437 */
1438 if (watchpoint->value) {
1439 LOG_DEBUG("data value watchpoint not YET supported");
1440 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1441 }
1442
1443 cortex_m->dwt_comp_available--;
1444 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1445
1446 return ERROR_OK;
1447 }
1448
1449 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1450 {
1451 struct cortex_m_common *cortex_m = target_to_cm(target);
1452
1453 /* REVISIT why check? DWT can be updated with core running ... */
1454 if (target->state != TARGET_HALTED) {
1455 LOG_WARNING("target not halted");
1456 return ERROR_TARGET_NOT_HALTED;
1457 }
1458
1459 if (watchpoint->set)
1460 cortex_m_unset_watchpoint(target, watchpoint);
1461
1462 cortex_m->dwt_comp_available++;
1463 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1464
1465 return ERROR_OK;
1466 }
1467
1468 void cortex_m_enable_watchpoints(struct target *target)
1469 {
1470 struct watchpoint *watchpoint = target->watchpoints;
1471
1472 /* set any pending watchpoints */
1473 while (watchpoint) {
1474 if (!watchpoint->set)
1475 cortex_m_set_watchpoint(target, watchpoint);
1476 watchpoint = watchpoint->next;
1477 }
1478 }
1479
1480 static int cortex_m_load_core_reg_u32(struct target *target,
1481 uint32_t num, uint32_t *value)
1482 {
1483 int retval;
1484
1485 /* NOTE: we "know" here that the register identifiers used
1486 * in the v7m header match the Cortex-M3 Debug Core Register
1487 * Selector values for R0..R15, xPSR, MSP, and PSP.
1488 */
1489 switch (num) {
1490 case 0 ... 18:
1491 /* read a normal core register */
1492 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1493
1494 if (retval != ERROR_OK) {
1495 LOG_ERROR("JTAG failure %i", retval);
1496 return ERROR_JTAG_DEVICE_ERROR;
1497 }
1498 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1499 break;
1500
1501 case ARMV7M_FPSCR:
1502 /* Floating-point Status and Registers */
1503 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1504 if (retval != ERROR_OK)
1505 return retval;
1506 retval = target_read_u32(target, DCB_DCRDR, value);
1507 if (retval != ERROR_OK)
1508 return retval;
1509 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1510 break;
1511
1512 case ARMV7M_S0 ... ARMV7M_S31:
1513 /* Floating-point Status and Registers */
1514 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1515 if (retval != ERROR_OK)
1516 return retval;
1517 retval = target_read_u32(target, DCB_DCRDR, value);
1518 if (retval != ERROR_OK)
1519 return retval;
1520 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1521 (int)(num - ARMV7M_S0), *value);
1522 break;
1523
1524 case ARMV7M_PRIMASK:
1525 case ARMV7M_BASEPRI:
1526 case ARMV7M_FAULTMASK:
1527 case ARMV7M_CONTROL:
1528 /* Cortex-M3 packages these four registers as bitfields
1529 * in one Debug Core register. So say r0 and r2 docs;
1530 * it was removed from r1 docs, but still works.
1531 */
1532 cortexm_dap_read_coreregister_u32(target, value, 20);
1533
1534 switch (num) {
1535 case ARMV7M_PRIMASK:
1536 *value = buf_get_u32((uint8_t *)value, 0, 1);
1537 break;
1538
1539 case ARMV7M_BASEPRI:
1540 *value = buf_get_u32((uint8_t *)value, 8, 8);
1541 break;
1542
1543 case ARMV7M_FAULTMASK:
1544 *value = buf_get_u32((uint8_t *)value, 16, 1);
1545 break;
1546
1547 case ARMV7M_CONTROL:
1548 *value = buf_get_u32((uint8_t *)value, 24, 2);
1549 break;
1550 }
1551
1552 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1553 break;
1554
1555 default:
1556 return ERROR_COMMAND_SYNTAX_ERROR;
1557 }
1558
1559 return ERROR_OK;
1560 }
1561
1562 static int cortex_m_store_core_reg_u32(struct target *target,
1563 uint32_t num, uint32_t value)
1564 {
1565 int retval;
1566 uint32_t reg;
1567 struct armv7m_common *armv7m = target_to_armv7m(target);
1568
1569 /* NOTE: we "know" here that the register identifiers used
1570 * in the v7m header match the Cortex-M3 Debug Core Register
1571 * Selector values for R0..R15, xPSR, MSP, and PSP.
1572 */
1573 switch (num) {
1574 case 0 ... 18:
1575 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1576 if (retval != ERROR_OK) {
1577 struct reg *r;
1578
1579 LOG_ERROR("JTAG failure");
1580 r = armv7m->arm.core_cache->reg_list + num;
1581 r->dirty = r->valid;
1582 return ERROR_JTAG_DEVICE_ERROR;
1583 }
1584 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1585 break;
1586
1587 case ARMV7M_FPSCR:
1588 /* Floating-point Status and Registers */
1589 retval = target_write_u32(target, DCB_DCRDR, value);
1590 if (retval != ERROR_OK)
1591 return retval;
1592 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1593 if (retval != ERROR_OK)
1594 return retval;
1595 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1596 break;
1597
1598 case ARMV7M_S0 ... ARMV7M_S31:
1599 /* Floating-point Status and Registers */
1600 retval = target_write_u32(target, DCB_DCRDR, value);
1601 if (retval != ERROR_OK)
1602 return retval;
1603 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1604 if (retval != ERROR_OK)
1605 return retval;
1606 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1607 (int)(num - ARMV7M_S0), value);
1608 break;
1609
1610 case ARMV7M_PRIMASK:
1611 case ARMV7M_BASEPRI:
1612 case ARMV7M_FAULTMASK:
1613 case ARMV7M_CONTROL:
1614 /* Cortex-M3 packages these four registers as bitfields
1615 * in one Debug Core register. So say r0 and r2 docs;
1616 * it was removed from r1 docs, but still works.
1617 */
1618 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1619
1620 switch (num) {
1621 case ARMV7M_PRIMASK:
1622 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1623 break;
1624
1625 case ARMV7M_BASEPRI:
1626 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1627 break;
1628
1629 case ARMV7M_FAULTMASK:
1630 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1631 break;
1632
1633 case ARMV7M_CONTROL:
1634 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1635 break;
1636 }
1637
1638 cortexm_dap_write_coreregister_u32(target, reg, 20);
1639
1640 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1641 break;
1642
1643 default:
1644 return ERROR_COMMAND_SYNTAX_ERROR;
1645 }
1646
1647 return ERROR_OK;
1648 }
1649
1650 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1651 uint32_t size, uint32_t count, uint8_t *buffer)
1652 {
1653 struct armv7m_common *armv7m = target_to_armv7m(target);
1654
1655 if (armv7m->arm.is_armv6m) {
1656 /* armv6m does not handle unaligned memory access */
1657 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1658 return ERROR_TARGET_UNALIGNED_ACCESS;
1659 }
1660
1661 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1662 }
1663
1664 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1665 uint32_t size, uint32_t count, const uint8_t *buffer)
1666 {
1667 struct armv7m_common *armv7m = target_to_armv7m(target);
1668
1669 if (armv7m->arm.is_armv6m) {
1670 /* armv6m does not handle unaligned memory access */
1671 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1672 return ERROR_TARGET_UNALIGNED_ACCESS;
1673 }
1674
1675 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1676 }
1677
1678 static int cortex_m_init_target(struct command_context *cmd_ctx,
1679 struct target *target)
1680 {
1681 armv7m_build_reg_cache(target);
1682 arm_semihosting_init(target);
1683 return ERROR_OK;
1684 }
1685
1686 void cortex_m_deinit_target(struct target *target)
1687 {
1688 struct cortex_m_common *cortex_m = target_to_cm(target);
1689
1690 free(cortex_m->fp_comparator_list);
1691
1692 cortex_m_dwt_free(target);
1693 armv7m_free_reg_cache(target);
1694
1695 free(target->private_config);
1696 free(cortex_m);
1697 }
1698
1699 int cortex_m_profiling(struct target *target, uint32_t *samples,
1700 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1701 {
1702 struct timeval timeout, now;
1703 struct armv7m_common *armv7m = target_to_armv7m(target);
1704 uint32_t reg_value;
1705 bool use_pcsr = false;
1706 int retval = ERROR_OK;
1707 struct reg *reg;
1708
1709 gettimeofday(&timeout, NULL);
1710 timeval_add_time(&timeout, seconds, 0);
1711
1712 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1713 if (retval != ERROR_OK) {
1714 LOG_ERROR("Error while reading PCSR");
1715 return retval;
1716 }
1717
1718 if (reg_value != 0) {
1719 use_pcsr = true;
1720 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1721 } else {
1722 LOG_INFO("Starting profiling. Halting and resuming the"
1723 " target as often as we can...");
1724 reg = register_get_by_name(target->reg_cache, "pc", 1);
1725 }
1726
1727 /* Make sure the target is running */
1728 target_poll(target);
1729 if (target->state == TARGET_HALTED)
1730 retval = target_resume(target, 1, 0, 0, 0);
1731
1732 if (retval != ERROR_OK) {
1733 LOG_ERROR("Error while resuming target");
1734 return retval;
1735 }
1736
1737 uint32_t sample_count = 0;
1738
1739 for (;;) {
1740 if (use_pcsr) {
1741 if (armv7m && armv7m->debug_ap) {
1742 uint32_t read_count = max_num_samples - sample_count;
1743 if (read_count > 1024)
1744 read_count = 1024;
1745
1746 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1747 (void *)&samples[sample_count],
1748 4, read_count, DWT_PCSR);
1749 sample_count += read_count;
1750 } else {
1751 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1752 }
1753 } else {
1754 target_poll(target);
1755 if (target->state == TARGET_HALTED) {
1756 reg_value = buf_get_u32(reg->value, 0, 32);
1757 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1758 retval = target_resume(target, 1, 0, 0, 0);
1759 samples[sample_count++] = reg_value;
1760 target_poll(target);
1761 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1762 } else if (target->state == TARGET_RUNNING) {
1763 /* We want to quickly sample the PC. */
1764 retval = target_halt(target);
1765 } else {
1766 LOG_INFO("Target not halted or running");
1767 retval = ERROR_OK;
1768 break;
1769 }
1770 }
1771
1772 if (retval != ERROR_OK) {
1773 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1774 return retval;
1775 }
1776
1777
1778 gettimeofday(&now, NULL);
1779 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1780 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1781 break;
1782 }
1783 }
1784
1785 *num_samples = sample_count;
1786 return retval;
1787 }
1788
1789
1790 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1791 * on r/w if the core is not running, and clear on resume or reset ... or
1792 * at least, in a post_restore_context() method.
1793 */
1794
1795 struct dwt_reg_state {
1796 struct target *target;
1797 uint32_t addr;
1798 uint8_t value[4]; /* scratch/cache */
1799 };
1800
1801 static int cortex_m_dwt_get_reg(struct reg *reg)
1802 {
1803 struct dwt_reg_state *state = reg->arch_info;
1804
1805 uint32_t tmp;
1806 int retval = target_read_u32(state->target, state->addr, &tmp);
1807 if (retval != ERROR_OK)
1808 return retval;
1809
1810 buf_set_u32(state->value, 0, 32, tmp);
1811 return ERROR_OK;
1812 }
1813
1814 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1815 {
1816 struct dwt_reg_state *state = reg->arch_info;
1817
1818 return target_write_u32(state->target, state->addr,
1819 buf_get_u32(buf, 0, reg->size));
1820 }
1821
1822 struct dwt_reg {
1823 uint32_t addr;
1824 const char *name;
1825 unsigned size;
1826 };
1827
1828 static const struct dwt_reg dwt_base_regs[] = {
1829 { DWT_CTRL, "dwt_ctrl", 32, },
1830 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1831 * increments while the core is asleep.
1832 */
1833 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1834 /* plus some 8 bit counters, useful for profiling with TPIU */
1835 };
1836
1837 static const struct dwt_reg dwt_comp[] = {
1838 #define DWT_COMPARATOR(i) \
1839 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1840 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1841 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1842 DWT_COMPARATOR(0),
1843 DWT_COMPARATOR(1),
1844 DWT_COMPARATOR(2),
1845 DWT_COMPARATOR(3),
1846 DWT_COMPARATOR(4),
1847 DWT_COMPARATOR(5),
1848 DWT_COMPARATOR(6),
1849 DWT_COMPARATOR(7),
1850 DWT_COMPARATOR(8),
1851 DWT_COMPARATOR(9),
1852 DWT_COMPARATOR(10),
1853 DWT_COMPARATOR(11),
1854 DWT_COMPARATOR(12),
1855 DWT_COMPARATOR(13),
1856 DWT_COMPARATOR(14),
1857 DWT_COMPARATOR(15),
1858 #undef DWT_COMPARATOR
1859 };
1860
1861 static const struct reg_arch_type dwt_reg_type = {
1862 .get = cortex_m_dwt_get_reg,
1863 .set = cortex_m_dwt_set_reg,
1864 };
1865
1866 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1867 {
1868 struct dwt_reg_state *state;
1869
1870 state = calloc(1, sizeof *state);
1871 if (!state)
1872 return;
1873 state->addr = d->addr;
1874 state->target = t;
1875
1876 r->name = d->name;
1877 r->size = d->size;
1878 r->value = state->value;
1879 r->arch_info = state;
1880 r->type = &dwt_reg_type;
1881 }
1882
1883 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1884 {
1885 uint32_t dwtcr;
1886 struct reg_cache *cache;
1887 struct cortex_m_dwt_comparator *comparator;
1888 int reg, i;
1889
1890 target_read_u32(target, DWT_CTRL, &dwtcr);
1891 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1892 if (!dwtcr) {
1893 LOG_DEBUG("no DWT");
1894 return;
1895 }
1896
1897 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1898 cm->dwt_comp_available = cm->dwt_num_comp;
1899 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1900 sizeof(struct cortex_m_dwt_comparator));
1901 if (!cm->dwt_comparator_list) {
1902 fail0:
1903 cm->dwt_num_comp = 0;
1904 LOG_ERROR("out of mem");
1905 return;
1906 }
1907
1908 cache = calloc(1, sizeof *cache);
1909 if (!cache) {
1910 fail1:
1911 free(cm->dwt_comparator_list);
1912 goto fail0;
1913 }
1914 cache->name = "Cortex-M DWT registers";
1915 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1916 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1917 if (!cache->reg_list) {
1918 free(cache);
1919 goto fail1;
1920 }
1921
1922 for (reg = 0; reg < 2; reg++)
1923 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1924 dwt_base_regs + reg);
1925
1926 comparator = cm->dwt_comparator_list;
1927 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1928 int j;
1929
1930 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1931 for (j = 0; j < 3; j++, reg++)
1932 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1933 dwt_comp + 3 * i + j);
1934
1935 /* make sure we clear any watchpoints enabled on the target */
1936 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1937 }
1938
1939 *register_get_last_cache_p(&target->reg_cache) = cache;
1940 cm->dwt_cache = cache;
1941
1942 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1943 dwtcr, cm->dwt_num_comp,
1944 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1945
1946 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1947 * implement single-address data value watchpoints ... so we
1948 * won't need to check it later, when asked to set one up.
1949 */
1950 }
1951
1952 static void cortex_m_dwt_free(struct target *target)
1953 {
1954 struct cortex_m_common *cm = target_to_cm(target);
1955 struct reg_cache *cache = cm->dwt_cache;
1956
1957 free(cm->dwt_comparator_list);
1958 cm->dwt_comparator_list = NULL;
1959 cm->dwt_num_comp = 0;
1960
1961 if (cache) {
1962 register_unlink_cache(&target->reg_cache, cache);
1963
1964 if (cache->reg_list) {
1965 for (size_t i = 0; i < cache->num_regs; i++)
1966 free(cache->reg_list[i].arch_info);
1967 free(cache->reg_list);
1968 }
1969 free(cache);
1970 }
1971 cm->dwt_cache = NULL;
1972 }
1973
1974 #define MVFR0 0xe000ef40
1975 #define MVFR1 0xe000ef44
1976
1977 #define MVFR0_DEFAULT_M4 0x10110021
1978 #define MVFR1_DEFAULT_M4 0x11000011
1979
1980 #define MVFR0_DEFAULT_M7_SP 0x10110021
1981 #define MVFR0_DEFAULT_M7_DP 0x10110221
1982 #define MVFR1_DEFAULT_M7_SP 0x11000011
1983 #define MVFR1_DEFAULT_M7_DP 0x12000011
1984
1985 int cortex_m_examine(struct target *target)
1986 {
1987 int retval;
1988 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1989 int i;
1990 struct cortex_m_common *cortex_m = target_to_cm(target);
1991 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1992 struct armv7m_common *armv7m = target_to_armv7m(target);
1993
1994 /* stlink shares the examine handler but does not support
1995 * all its calls */
1996 if (!armv7m->stlink) {
1997 if (cortex_m->apsel == DP_APSEL_INVALID) {
1998 /* Search for the MEM-AP */
1999 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
2000 if (retval != ERROR_OK) {
2001 LOG_ERROR("Could not find MEM-AP to control the core");
2002 return retval;
2003 }
2004 } else {
2005 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2006 }
2007
2008 /* Leave (only) generic DAP stuff for debugport_init(); */
2009 armv7m->debug_ap->memaccess_tck = 8;
2010
2011 retval = mem_ap_init(armv7m->debug_ap);
2012 if (retval != ERROR_OK)
2013 return retval;
2014 }
2015
2016 if (!target_was_examined(target)) {
2017 target_set_examined(target);
2018
2019 /* Read from Device Identification Registers */
2020 retval = target_read_u32(target, CPUID, &cpuid);
2021 if (retval != ERROR_OK)
2022 return retval;
2023
2024 /* Get CPU Type */
2025 i = (cpuid >> 4) & 0xf;
2026
2027 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2028 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2029 if (i == 7) {
2030 uint8_t rev, patch;
2031 rev = (cpuid >> 20) & 0xf;
2032 patch = (cpuid >> 0) & 0xf;
2033 if ((rev == 0) && (patch < 2))
2034 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2035 }
2036 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2037
2038 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2039 cortex_m->vectreset_supported = i > 1;
2040
2041 if (i == 4) {
2042 target_read_u32(target, MVFR0, &mvfr0);
2043 target_read_u32(target, MVFR1, &mvfr1);
2044
2045 /* test for floating point feature on Cortex-M4 */
2046 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2047 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2048 armv7m->fp_feature = FPv4_SP;
2049 }
2050 } else if (i == 7) {
2051 target_read_u32(target, MVFR0, &mvfr0);
2052 target_read_u32(target, MVFR1, &mvfr1);
2053
2054 /* test for floating point features on Cortex-M7 */
2055 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2056 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2057 armv7m->fp_feature = FPv5_SP;
2058 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2059 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2060 armv7m->fp_feature = FPv5_DP;
2061 }
2062 } else if (i == 0) {
2063 /* Cortex-M0 does not support unaligned memory access */
2064 armv7m->arm.is_armv6m = true;
2065 }
2066
2067 if (armv7m->fp_feature == FP_NONE &&
2068 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2069 /* free unavailable FPU registers */
2070 size_t idx;
2071
2072 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2073 idx < armv7m->arm.core_cache->num_regs;
2074 idx++) {
2075 free(armv7m->arm.core_cache->reg_list[idx].value);
2076 free(armv7m->arm.core_cache->reg_list[idx].feature);
2077 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2078 }
2079 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2080 }
2081
2082 if (!armv7m->stlink) {
2083 if (i == 3 || i == 4)
2084 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2085 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2086 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2087 else if (i == 7)
2088 /* Cortex-M7 has only 1024 bytes autoincrement range */
2089 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2090 }
2091
2092 /* Configure trace modules */
2093 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2094 if (retval != ERROR_OK)
2095 return retval;
2096
2097 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2098 armv7m_trace_tpiu_config(target);
2099 armv7m_trace_itm_config(target);
2100 }
2101
2102 /* NOTE: FPB and DWT are both optional. */
2103
2104 /* Setup FPB */
2105 target_read_u32(target, FP_CTRL, &fpcr);
2106 /* bits [14:12] and [7:4] */
2107 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2108 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2109 cortex_m->fp_code_available = cortex_m->fp_num_code;
2110 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2111 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2112 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2113 free(cortex_m->fp_comparator_list);
2114 cortex_m->fp_comparator_list = calloc(
2115 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2116 sizeof(struct cortex_m_fp_comparator));
2117 cortex_m->fpb_enabled = fpcr & 1;
2118 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2119 cortex_m->fp_comparator_list[i].type =
2120 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2121 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2122
2123 /* make sure we clear any breakpoints enabled on the target */
2124 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2125 }
2126 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2127 fpcr,
2128 cortex_m->fp_num_code,
2129 cortex_m->fp_num_lit);
2130
2131 /* Setup DWT */
2132 cortex_m_dwt_free(target);
2133 cortex_m_dwt_setup(cortex_m, target);
2134
2135 /* These hardware breakpoints only work for code in flash! */
2136 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2137 target_name(target),
2138 cortex_m->fp_num_code,
2139 cortex_m->dwt_num_comp);
2140 }
2141
2142 return ERROR_OK;
2143 }
2144
2145 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2146 {
2147 struct armv7m_common *armv7m = target_to_armv7m(target);
2148 uint16_t dcrdr;
2149 uint8_t buf[2];
2150 int retval;
2151
2152 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2153 if (retval != ERROR_OK)
2154 return retval;
2155
2156 dcrdr = target_buffer_get_u16(target, buf);
2157 *ctrl = (uint8_t)dcrdr;
2158 *value = (uint8_t)(dcrdr >> 8);
2159
2160 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2161
2162 /* write ack back to software dcc register
2163 * signify we have read data */
2164 if (dcrdr & (1 << 0)) {
2165 target_buffer_set_u16(target, buf, 0);
2166 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2167 if (retval != ERROR_OK)
2168 return retval;
2169 }
2170
2171 return ERROR_OK;
2172 }
2173
2174 static int cortex_m_target_request_data(struct target *target,
2175 uint32_t size, uint8_t *buffer)
2176 {
2177 uint8_t data;
2178 uint8_t ctrl;
2179 uint32_t i;
2180
2181 for (i = 0; i < (size * 4); i++) {
2182 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2183 if (retval != ERROR_OK)
2184 return retval;
2185 buffer[i] = data;
2186 }
2187
2188 return ERROR_OK;
2189 }
2190
2191 static int cortex_m_handle_target_request(void *priv)
2192 {
2193 struct target *target = priv;
2194 if (!target_was_examined(target))
2195 return ERROR_OK;
2196
2197 if (!target->dbg_msg_enabled)
2198 return ERROR_OK;
2199
2200 if (target->state == TARGET_RUNNING) {
2201 uint8_t data;
2202 uint8_t ctrl;
2203 int retval;
2204
2205 retval = cortex_m_dcc_read(target, &data, &ctrl);
2206 if (retval != ERROR_OK)
2207 return retval;
2208
2209 /* check if we have data */
2210 if (ctrl & (1 << 0)) {
2211 uint32_t request;
2212
2213 /* we assume target is quick enough */
2214 request = data;
2215 for (int i = 1; i <= 3; i++) {
2216 retval = cortex_m_dcc_read(target, &data, &ctrl);
2217 if (retval != ERROR_OK)
2218 return retval;
2219 request |= ((uint32_t)data << (i * 8));
2220 }
2221 target_request(target, request);
2222 }
2223 }
2224
2225 return ERROR_OK;
2226 }
2227
2228 static int cortex_m_init_arch_info(struct target *target,
2229 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2230 {
2231 struct armv7m_common *armv7m = &cortex_m->armv7m;
2232
2233 armv7m_init_arch_info(target, armv7m);
2234
2235 /* default reset mode is to use srst if fitted
2236 * if not it will use CORTEX_M3_RESET_VECTRESET */
2237 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2238
2239 armv7m->arm.dap = dap;
2240
2241 /* register arch-specific functions */
2242 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2243
2244 armv7m->post_debug_entry = NULL;
2245
2246 armv7m->pre_restore_context = NULL;
2247
2248 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2249 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2250
2251 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2252
2253 return ERROR_OK;
2254 }
2255
2256 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2257 {
2258 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2259 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2260 struct adiv5_private_config *pc;
2261
2262 pc = (struct adiv5_private_config *)target->private_config;
2263 if (adiv5_verify_config(pc) != ERROR_OK)
2264 return ERROR_FAIL;
2265
2266 cortex_m->apsel = pc->ap_num;
2267
2268 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2269
2270 return ERROR_OK;
2271 }
2272
2273 /*--------------------------------------------------------------------------*/
2274
2275 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2276 struct cortex_m_common *cm)
2277 {
2278 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2279 command_print(cmd_ctx, "target is not a Cortex-M");
2280 return ERROR_TARGET_INVALID;
2281 }
2282 return ERROR_OK;
2283 }
2284
2285 /*
2286 * Only stuff below this line should need to verify that its target
2287 * is a Cortex-M3. Everything else should have indirected through the
2288 * cortexm3_target structure, which is only used with CM3 targets.
2289 */
2290
2291 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2292 {
2293 struct target *target = get_current_target(CMD_CTX);
2294 struct cortex_m_common *cortex_m = target_to_cm(target);
2295 struct armv7m_common *armv7m = &cortex_m->armv7m;
2296 uint32_t demcr = 0;
2297 int retval;
2298
2299 static const struct {
2300 char name[10];
2301 unsigned mask;
2302 } vec_ids[] = {
2303 { "hard_err", VC_HARDERR, },
2304 { "int_err", VC_INTERR, },
2305 { "bus_err", VC_BUSERR, },
2306 { "state_err", VC_STATERR, },
2307 { "chk_err", VC_CHKERR, },
2308 { "nocp_err", VC_NOCPERR, },
2309 { "mm_err", VC_MMERR, },
2310 { "reset", VC_CORERESET, },
2311 };
2312
2313 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2314 if (retval != ERROR_OK)
2315 return retval;
2316
2317 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2318 if (retval != ERROR_OK)
2319 return retval;
2320
2321 if (CMD_ARGC > 0) {
2322 unsigned catch = 0;
2323
2324 if (CMD_ARGC == 1) {
2325 if (strcmp(CMD_ARGV[0], "all") == 0) {
2326 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2327 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2328 | VC_MMERR | VC_CORERESET;
2329 goto write;
2330 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2331 goto write;
2332 }
2333 while (CMD_ARGC-- > 0) {
2334 unsigned i;
2335 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2336 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2337 continue;
2338 catch |= vec_ids[i].mask;
2339 break;
2340 }
2341 if (i == ARRAY_SIZE(vec_ids)) {
2342 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2343 return ERROR_COMMAND_SYNTAX_ERROR;
2344 }
2345 }
2346 write:
2347 /* For now, armv7m->demcr only stores vector catch flags. */
2348 armv7m->demcr = catch;
2349
2350 demcr &= ~0xffff;
2351 demcr |= catch;
2352
2353 /* write, but don't assume it stuck (why not??) */
2354 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2355 if (retval != ERROR_OK)
2356 return retval;
2357 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2358 if (retval != ERROR_OK)
2359 return retval;
2360
2361 /* FIXME be sure to clear DEMCR on clean server shutdown.
2362 * Otherwise the vector catch hardware could fire when there's
2363 * no debugger hooked up, causing much confusion...
2364 */
2365 }
2366
2367 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2368 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2369 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2370 }
2371
2372 return ERROR_OK;
2373 }
2374
2375 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2376 {
2377 struct target *target = get_current_target(CMD_CTX);
2378 struct cortex_m_common *cortex_m = target_to_cm(target);
2379 int retval;
2380
2381 static const Jim_Nvp nvp_maskisr_modes[] = {
2382 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2383 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2384 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2385 { .name = NULL, .value = -1 },
2386 };
2387 const Jim_Nvp *n;
2388
2389
2390 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2391 if (retval != ERROR_OK)
2392 return retval;
2393
2394 if (target->state != TARGET_HALTED) {
2395 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2396 return ERROR_OK;
2397 }
2398
2399 if (CMD_ARGC > 0) {
2400 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2401 if (n->name == NULL)
2402 return ERROR_COMMAND_SYNTAX_ERROR;
2403 cortex_m->isrmasking_mode = n->value;
2404
2405
2406 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2407 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2408 else
2409 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2410 }
2411
2412 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2413 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2414
2415 return ERROR_OK;
2416 }
2417
2418 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2419 {
2420 struct target *target = get_current_target(CMD_CTX);
2421 struct cortex_m_common *cortex_m = target_to_cm(target);
2422 int retval;
2423 char *reset_config;
2424
2425 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2426 if (retval != ERROR_OK)
2427 return retval;
2428
2429 if (CMD_ARGC > 0) {
2430 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2431 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2432
2433 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2434 if (target_was_examined(target)
2435 && !cortex_m->vectreset_supported)
2436 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2437 else
2438 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2439
2440 } else
2441 return ERROR_COMMAND_SYNTAX_ERROR;
2442 }
2443
2444 switch (cortex_m->soft_reset_config) {
2445 case CORTEX_M_RESET_SYSRESETREQ:
2446 reset_config = "sysresetreq";
2447 break;
2448
2449 case CORTEX_M_RESET_VECTRESET:
2450 reset_config = "vectreset";
2451 break;
2452
2453 default:
2454 reset_config = "unknown";
2455 break;
2456 }
2457
2458 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2459
2460 return ERROR_OK;
2461 }
2462
2463 static const struct command_registration cortex_m_exec_command_handlers[] = {
2464 {
2465 .name = "maskisr",
2466 .handler = handle_cortex_m_mask_interrupts_command,
2467 .mode = COMMAND_EXEC,
2468 .help = "mask cortex_m interrupts",
2469 .usage = "['auto'|'on'|'off']",
2470 },
2471 {
2472 .name = "vector_catch",
2473 .handler = handle_cortex_m_vector_catch_command,
2474 .mode = COMMAND_EXEC,
2475 .help = "configure hardware vectors to trigger debug entry",
2476 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2477 },
2478 {
2479 .name = "reset_config",
2480 .handler = handle_cortex_m_reset_config_command,
2481 .mode = COMMAND_ANY,
2482 .help = "configure software reset handling",
2483 .usage = "['sysresetreq'|'vectreset']",
2484 },
2485 COMMAND_REGISTRATION_DONE
2486 };
2487 static const struct command_registration cortex_m_command_handlers[] = {
2488 {
2489 .chain = armv7m_command_handlers,
2490 },
2491 {
2492 .chain = armv7m_trace_command_handlers,
2493 },
2494 {
2495 .name = "cortex_m",
2496 .mode = COMMAND_EXEC,
2497 .help = "Cortex-M command group",
2498 .usage = "",
2499 .chain = cortex_m_exec_command_handlers,
2500 },
2501 COMMAND_REGISTRATION_DONE
2502 };
2503
2504 struct target_type cortexm_target = {
2505 .name = "cortex_m",
2506 .deprecated_name = "cortex_m3",
2507
2508 .poll = cortex_m_poll,
2509 .arch_state = armv7m_arch_state,
2510
2511 .target_request_data = cortex_m_target_request_data,
2512
2513 .halt = cortex_m_halt,
2514 .resume = cortex_m_resume,
2515 .step = cortex_m_step,
2516
2517 .assert_reset = cortex_m_assert_reset,
2518 .deassert_reset = cortex_m_deassert_reset,
2519 .soft_reset_halt = cortex_m_soft_reset_halt,
2520
2521 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2522
2523 .read_memory = cortex_m_read_memory,
2524 .write_memory = cortex_m_write_memory,
2525 .checksum_memory = armv7m_checksum_memory,
2526 .blank_check_memory = armv7m_blank_check_memory,
2527
2528 .run_algorithm = armv7m_run_algorithm,
2529 .start_algorithm = armv7m_start_algorithm,
2530 .wait_algorithm = armv7m_wait_algorithm,
2531
2532 .add_breakpoint = cortex_m_add_breakpoint,
2533 .remove_breakpoint = cortex_m_remove_breakpoint,
2534 .add_watchpoint = cortex_m_add_watchpoint,
2535 .remove_watchpoint = cortex_m_remove_watchpoint,
2536
2537 .commands = cortex_m_command_handlers,
2538 .target_create = cortex_m_target_create,
2539 .target_jim_configure = adiv5_jim_configure,
2540 .init_target = cortex_m_init_target,
2541 .examine = cortex_m_examine,
2542 .deinit_target = cortex_m_deinit_target,
2543
2544 .profiling = cortex_m_profiling,
2545 };
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