1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
57 * Returns the type of a break point required by address location
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
62 /* forward declarations */
63 static int cortex_m3_store_core_reg_u32(struct target
*target
,
64 uint32_t num
, uint32_t value
);
66 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
67 uint32_t *value
, int regnum
)
72 /* because the DCB_DCRDR is used for the emulated dcc channel
73 * we have to save/restore the DCB_DCRDR when used */
75 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
76 if (retval
!= ERROR_OK
)
79 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
80 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
81 if (retval
!= ERROR_OK
)
83 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
84 if (retval
!= ERROR_OK
)
87 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
88 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
89 if (retval
!= ERROR_OK
)
91 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
92 if (retval
!= ERROR_OK
)
95 retval
= dap_run(swjdp
);
96 if (retval
!= ERROR_OK
)
99 /* restore DCB_DCRDR - this needs to be in a seperate
100 * transaction otherwise the emulated DCC channel breaks */
101 if (retval
== ERROR_OK
)
102 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
107 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
108 uint32_t value
, int regnum
)
113 /* because the DCB_DCRDR is used for the emulated dcc channel
114 * we have to save/restore the DCB_DCRDR when used */
116 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
117 if (retval
!= ERROR_OK
)
120 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
121 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
122 if (retval
!= ERROR_OK
)
124 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
125 if (retval
!= ERROR_OK
)
128 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
129 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
130 if (retval
!= ERROR_OK
)
132 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
133 if (retval
!= ERROR_OK
)
136 retval
= dap_run(swjdp
);
137 if (retval
!= ERROR_OK
)
140 /* restore DCB_DCRDR - this needs to be in a seperate
141 * transaction otherwise the emulated DCC channel breaks */
142 if (retval
== ERROR_OK
)
143 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
148 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
149 uint32_t mask_on
, uint32_t mask_off
)
151 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
152 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
154 /* mask off status bits */
155 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
156 /* create new register mask */
157 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
159 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
162 static int cortex_m3_clear_halt(struct target
*target
)
164 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
165 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
168 /* clear step if any */
169 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
171 /* Read Debug Fault Status Register */
172 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
173 if (retval
!= ERROR_OK
)
176 /* Clear Debug Fault Status */
177 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
178 if (retval
!= ERROR_OK
)
180 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
185 static int cortex_m3_single_step_core(struct target
*target
)
187 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
188 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
192 /* backup dhcsr reg */
193 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
195 /* Mask interrupts before clearing halt, if done already. This avoids
196 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
197 * HALT can put the core into an unknown state.
199 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
)) {
200 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
201 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
202 if (retval
!= ERROR_OK
)
205 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
206 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
207 if (retval
!= ERROR_OK
)
211 /* restore dhcsr reg */
212 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
213 cortex_m3_clear_halt(target
);
218 static int cortex_m3_endreset_event(struct target
*target
)
223 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
224 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
225 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
226 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
227 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
231 if (retval
!= ERROR_OK
)
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
235 /* this register is used for emulated dcc channel */
236 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
237 if (retval
!= ERROR_OK
)
240 /* Enable debug requests */
241 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
242 if (retval
!= ERROR_OK
)
244 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
)) {
245 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
246 if (retval
!= ERROR_OK
)
250 /* clear any interrupt masking */
251 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
253 /* Enable features controlled by ITM and DWT blocks, and catch only
254 * the vectors we were told to pay attention to.
256 * Target firmware is responsible for all fault handling policy
257 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
258 * or manual updates to the NVIC SHCSR and CCR registers.
260 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
261 if (retval
!= ERROR_OK
)
264 /* Paranoia: evidently some (early?) chips don't preserve all the
265 * debug state (including FBP, DWT, etc) across reset...
269 retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 cortex_m3
->fpb_enabled
= 1;
275 /* Restore FPB registers */
276 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++) {
277 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
278 if (retval
!= ERROR_OK
)
282 /* Restore DWT registers */
283 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++) {
284 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
286 if (retval
!= ERROR_OK
)
288 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
290 if (retval
!= ERROR_OK
)
292 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
293 dwt_list
[i
].function
);
294 if (retval
!= ERROR_OK
)
297 retval
= dap_run(swjdp
);
298 if (retval
!= ERROR_OK
)
301 register_cache_invalidate(armv7m
->arm
.core_cache
);
303 /* make sure we have latest dhcsr flags */
304 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
309 static int cortex_m3_examine_debug_reason(struct target
*target
)
311 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
313 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
314 * only check the debug reason if we don't know it already */
316 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
317 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
318 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
) {
319 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
320 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
321 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
322 } else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
323 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
324 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
325 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
326 else /* EXTERNAL, HALTED */
327 target
->debug_reason
= DBG_REASON_UNDEFINED
;
333 static int cortex_m3_examine_exception_reason(struct target
*target
)
335 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
336 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
337 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
340 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
341 if (retval
!= ERROR_OK
)
343 switch (armv7m
->exception_number
) {
346 case 3: /* Hard Fault */
347 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
348 if (retval
!= ERROR_OK
)
350 if (except_sr
& 0x40000000) {
351 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
352 if (retval
!= ERROR_OK
)
356 case 4: /* Memory Management */
357 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
358 if (retval
!= ERROR_OK
)
360 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
361 if (retval
!= ERROR_OK
)
364 case 5: /* Bus Fault */
365 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
366 if (retval
!= ERROR_OK
)
368 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
369 if (retval
!= ERROR_OK
)
372 case 6: /* Usage Fault */
373 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
374 if (retval
!= ERROR_OK
)
377 case 11: /* SVCall */
379 case 12: /* Debug Monitor */
380 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
381 if (retval
!= ERROR_OK
)
384 case 14: /* PendSV */
386 case 15: /* SysTick */
392 retval
= dap_run(swjdp
);
393 if (retval
== ERROR_OK
)
394 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
395 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
396 armv7m_exception_string(armv7m
->exception_number
),
397 shcsr
, except_sr
, cfsr
, except_ar
);
401 static int cortex_m3_debug_entry(struct target
*target
)
406 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
407 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
408 struct arm
*arm
= &armv7m
->arm
;
409 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
414 cortex_m3_clear_halt(target
);
415 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
416 if (retval
!= ERROR_OK
)
419 retval
= armv7m
->examine_debug_reason(target
);
420 if (retval
!= ERROR_OK
)
423 /* Examine target state and mode
424 * First load register accessible through core debug port */
425 int num_regs
= arm
->core_cache
->num_regs
;
427 for (i
= 0; i
< num_regs
; i
++) {
428 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
430 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
434 xPSR
= buf_get_u32(r
->value
, 0, 32);
436 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
439 cortex_m3_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
442 /* Are we in an exception handler */
444 armv7m
->exception_number
= (xPSR
& 0x1FF);
446 arm
->core_mode
= ARM_MODE_HANDLER
;
447 arm
->map
= armv7m_msp_reg_map
;
449 unsigned control
= buf_get_u32(arm
->core_cache
450 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
452 /* is this thread privileged? */
453 arm
->core_mode
= control
& 1
454 ? ARM_MODE_USER_THREAD
457 /* which stack is it using? */
459 arm
->map
= armv7m_psp_reg_map
;
461 arm
->map
= armv7m_msp_reg_map
;
463 armv7m
->exception_number
= 0;
466 if (armv7m
->exception_number
)
467 cortex_m3_examine_exception_reason(target
);
469 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
470 arm_mode_name(arm
->core_mode
),
471 *(uint32_t *)(arm
->pc
->value
),
472 target_state_name(target
));
474 if (armv7m
->post_debug_entry
) {
475 retval
= armv7m
->post_debug_entry(target
);
476 if (retval
!= ERROR_OK
)
483 static int cortex_m3_poll(struct target
*target
)
485 int detected_failure
= ERROR_OK
;
486 int retval
= ERROR_OK
;
487 enum target_state prev_target_state
= target
->state
;
488 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
489 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
491 /* Read from Debug Halting Control and Status Register */
492 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
493 if (retval
!= ERROR_OK
) {
494 target
->state
= TARGET_UNKNOWN
;
498 /* Recover from lockup. See ARMv7-M architecture spec,
499 * section B1.5.15 "Unrecoverable exception cases".
501 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
502 LOG_ERROR("%s -- clearing lockup after double fault",
503 target_name(target
));
504 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
505 target
->debug_reason
= DBG_REASON_DBGRQ
;
507 /* We have to execute the rest (the "finally" equivalent, but
508 * still throw this exception again).
510 detected_failure
= ERROR_FAIL
;
512 /* refresh status bits */
513 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
514 if (retval
!= ERROR_OK
)
518 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
) {
519 /* check if still in reset */
520 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
521 if (retval
!= ERROR_OK
)
524 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
) {
525 target
->state
= TARGET_RESET
;
530 if (target
->state
== TARGET_RESET
) {
531 /* Cannot switch context while running so endreset is
532 * called with target->state == TARGET_RESET
534 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
535 cortex_m3
->dcb_dhcsr
);
536 cortex_m3_endreset_event(target
);
537 target
->state
= TARGET_RUNNING
;
538 prev_target_state
= TARGET_RUNNING
;
541 if (cortex_m3
->dcb_dhcsr
& S_HALT
) {
542 target
->state
= TARGET_HALTED
;
544 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
545 retval
= cortex_m3_debug_entry(target
);
546 if (retval
!= ERROR_OK
)
549 if (arm_semihosting(target
, &retval
) != 0)
552 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
554 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
556 retval
= cortex_m3_debug_entry(target
);
557 if (retval
!= ERROR_OK
)
560 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
564 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
565 * How best to model low power modes?
568 if (target
->state
== TARGET_UNKNOWN
) {
569 /* check if processor is retiring instructions */
570 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
) {
571 target
->state
= TARGET_RUNNING
;
576 /* Did we detect a failure condition that we cleared? */
577 if (detected_failure
!= ERROR_OK
)
578 retval
= detected_failure
;
582 static int cortex_m3_halt(struct target
*target
)
584 LOG_DEBUG("target->state: %s",
585 target_state_name(target
));
587 if (target
->state
== TARGET_HALTED
) {
588 LOG_DEBUG("target was already halted");
592 if (target
->state
== TARGET_UNKNOWN
)
593 LOG_WARNING("target was in unknown state when halt was requested");
595 if (target
->state
== TARGET_RESET
) {
596 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
597 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
598 return ERROR_TARGET_FAILURE
;
600 /* we came here in a reset_halt or reset_init sequence
601 * debug entry was already prepared in cortex_m3_assert_reset()
603 target
->debug_reason
= DBG_REASON_DBGRQ
;
609 /* Write to Debug Halting Control and Status Register */
610 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
612 target
->debug_reason
= DBG_REASON_DBGRQ
;
617 static int cortex_m3_soft_reset_halt(struct target
*target
)
619 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
620 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
621 uint32_t dcb_dhcsr
= 0;
622 int retval
, timeout
= 0;
624 /* soft_reset_halt is deprecated on cortex_m as the same functionality
625 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
626 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
627 * core, not the peripherals */
628 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
630 /* Enter debug state on reset; restore DEMCR in endreset_event() */
631 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
632 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
633 if (retval
!= ERROR_OK
)
636 /* Request a core-only reset */
637 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
638 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
639 if (retval
!= ERROR_OK
)
641 target
->state
= TARGET_RESET
;
643 /* registers are now invalid */
644 register_cache_invalidate(cortex_m3
->armv7m
.arm
.core_cache
);
646 while (timeout
< 100) {
647 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
648 if (retval
== ERROR_OK
) {
649 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
650 &cortex_m3
->nvic_dfsr
);
651 if (retval
!= ERROR_OK
)
653 if ((dcb_dhcsr
& S_HALT
)
654 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)) {
655 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
657 (unsigned) dcb_dhcsr
,
658 (unsigned) cortex_m3
->nvic_dfsr
);
659 cortex_m3_poll(target
);
660 /* FIXME restore user's vector catch config */
663 LOG_DEBUG("waiting for system reset-halt, "
664 "DHCSR 0x%08x, %d ms",
665 (unsigned) dcb_dhcsr
, timeout
);
674 void cortex_m3_enable_breakpoints(struct target
*target
)
676 struct breakpoint
*breakpoint
= target
->breakpoints
;
678 /* set any pending breakpoints */
680 if (!breakpoint
->set
)
681 cortex_m3_set_breakpoint(target
, breakpoint
);
682 breakpoint
= breakpoint
->next
;
686 static int cortex_m3_resume(struct target
*target
, int current
,
687 uint32_t address
, int handle_breakpoints
, int debug_execution
)
689 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
690 struct breakpoint
*breakpoint
= NULL
;
694 if (target
->state
!= TARGET_HALTED
) {
695 LOG_WARNING("target not halted");
696 return ERROR_TARGET_NOT_HALTED
;
699 if (!debug_execution
) {
700 target_free_all_working_areas(target
);
701 cortex_m3_enable_breakpoints(target
);
702 cortex_m3_enable_watchpoints(target
);
705 if (debug_execution
) {
706 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
708 /* Disable interrupts */
709 /* We disable interrupts in the PRIMASK register instead of
710 * masking with C_MASKINTS. This is probably the same issue
711 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
712 * in parallel with disabled interrupts can cause local faults
715 * REVISIT this clearly breaks non-debug execution, since the
716 * PRIMASK register state isn't saved/restored... workaround
717 * by never resuming app code after debug execution.
719 buf_set_u32(r
->value
, 0, 1, 1);
723 /* Make sure we are in Thumb mode */
724 r
= armv7m
->arm
.cpsr
;
725 buf_set_u32(r
->value
, 24, 1, 1);
730 /* current = 1: continue on current pc, otherwise continue at <address> */
733 buf_set_u32(r
->value
, 0, 32, address
);
738 /* if we halted last time due to a bkpt instruction
739 * then we have to manually step over it, otherwise
740 * the core will break again */
742 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
744 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
746 resume_pc
= buf_get_u32(r
->value
, 0, 32);
748 armv7m_restore_context(target
);
750 /* the front-end may request us not to handle breakpoints */
751 if (handle_breakpoints
) {
752 /* Single step past breakpoint at current address */
753 breakpoint
= breakpoint_find(target
, resume_pc
);
755 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
757 breakpoint
->unique_id
);
758 cortex_m3_unset_breakpoint(target
, breakpoint
);
759 cortex_m3_single_step_core(target
);
760 cortex_m3_set_breakpoint(target
, breakpoint
);
765 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
767 target
->debug_reason
= DBG_REASON_NOTHALTED
;
769 /* registers are now invalid */
770 register_cache_invalidate(armv7m
->arm
.core_cache
);
772 if (!debug_execution
) {
773 target
->state
= TARGET_RUNNING
;
774 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
775 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
777 target
->state
= TARGET_DEBUG_RUNNING
;
778 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
779 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
785 /* int irqstepcount = 0; */
786 static int cortex_m3_step(struct target
*target
, int current
,
787 uint32_t address
, int handle_breakpoints
)
789 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
790 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
791 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
792 struct breakpoint
*breakpoint
= NULL
;
793 struct reg
*pc
= armv7m
->arm
.pc
;
794 bool bkpt_inst_found
= false;
796 bool isr_timed_out
= false;
798 if (target
->state
!= TARGET_HALTED
) {
799 LOG_WARNING("target not halted");
800 return ERROR_TARGET_NOT_HALTED
;
803 /* current = 1: continue on current pc, otherwise continue at <address> */
805 buf_set_u32(pc
->value
, 0, 32, address
);
807 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
809 /* the front-end may request us not to handle breakpoints */
810 if (handle_breakpoints
) {
811 breakpoint
= breakpoint_find(target
, pc_value
);
813 cortex_m3_unset_breakpoint(target
, breakpoint
);
816 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
818 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
820 armv7m_restore_context(target
);
822 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
824 /* if no bkpt instruction is found at pc then we can perform
825 * a normal step, otherwise we have to manually step over the bkpt
826 * instruction - as such simulate a step */
827 if (bkpt_inst_found
== false) {
828 /* Automatic ISR masking mode off: Just step over the next instruction */
829 if ((cortex_m3
->isrmasking_mode
!= CORTEX_M3_ISRMASK_AUTO
))
830 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
832 /* Process interrupts during stepping in a way they don't interfere
837 * Set a temporary break point at the current pc and let the core run
838 * with interrupts enabled. Pending interrupts get served and we run
839 * into the breakpoint again afterwards. Then we step over the next
840 * instruction with interrupts disabled.
842 * If the pending interrupts don't complete within time, we leave the
843 * core running. This may happen if the interrupts trigger faster
844 * than the core can process them or the handler doesn't return.
846 * If no more breakpoints are available we simply do a step with
847 * interrupts enabled.
853 * If a break point is already set on the lower half word then a break point on
854 * the upper half word will not break again when the core is restarted. So we
855 * just step over the instruction with interrupts disabled.
857 * The documentation has no information about this, it was found by observation
858 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
859 * suffer from this problem.
861 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
862 * address has it always cleared. The former is done to indicate thumb mode
866 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
867 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
868 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
869 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
870 /* Re-enable interrupts */
871 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
875 /* Set a temporary break point */
877 retval
= cortex_m3_set_breakpoint(target
, breakpoint
);
879 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
880 bool tmp_bp_set
= (retval
== ERROR_OK
);
882 /* No more breakpoints left, just do a step */
884 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
887 LOG_DEBUG("Starting core to serve pending interrupts");
888 int64_t t_start
= timeval_ms();
889 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
891 /* Wait for pending handlers to complete or timeout */
893 retval
= mem_ap_read_atomic_u32(swjdp
,
895 &cortex_m3
->dcb_dhcsr
);
896 if (retval
!= ERROR_OK
) {
897 target
->state
= TARGET_UNKNOWN
;
900 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
901 } while (!((cortex_m3
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
903 /* only remove breakpoint if we created it */
905 cortex_m3_unset_breakpoint(target
, breakpoint
);
907 /* Remove the temporary breakpoint */
908 breakpoint_remove(target
, pc_value
);
912 LOG_DEBUG("Interrupt handlers didn't complete within time, "
913 "leaving target running");
915 /* Step over next instruction with interrupts disabled */
916 cortex_m3_write_debug_halt_mask(target
,
919 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
920 /* Re-enable interrupts */
921 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
928 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
929 if (retval
!= ERROR_OK
)
932 /* registers are now invalid */
933 register_cache_invalidate(armv7m
->arm
.core_cache
);
936 cortex_m3_set_breakpoint(target
, breakpoint
);
939 /* Leave the core running. The user has to stop execution manually. */
940 target
->debug_reason
= DBG_REASON_NOTHALTED
;
941 target
->state
= TARGET_RUNNING
;
945 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
946 " nvic_icsr = 0x%" PRIx32
,
947 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
949 retval
= cortex_m3_debug_entry(target
);
950 if (retval
!= ERROR_OK
)
952 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
954 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
955 " nvic_icsr = 0x%" PRIx32
,
956 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
961 static int cortex_m3_assert_reset(struct target
*target
)
963 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
964 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
965 enum cortex_m3_soft_reset_config reset_config
= cortex_m3
->soft_reset_config
;
967 LOG_DEBUG("target->state: %s",
968 target_state_name(target
));
970 enum reset_types jtag_reset_config
= jtag_get_reset_config();
972 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
973 /* allow scripts to override the reset event */
975 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
976 register_cache_invalidate(cortex_m3
->armv7m
.arm
.core_cache
);
977 target
->state
= TARGET_RESET
;
982 /* some cores support connecting while srst is asserted
983 * use that mode is it has been configured */
985 bool srst_asserted
= false;
987 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
988 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
989 adapter_assert_reset();
990 srst_asserted
= true;
993 /* Enable debug requests */
995 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
996 if (retval
!= ERROR_OK
)
998 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
)) {
999 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
1000 if (retval
!= ERROR_OK
)
1004 /* If the processor is sleeping in a WFI or WFE instruction, the
1005 * C_HALT bit must be asserted to regain control */
1006 if (cortex_m3
->dcb_dhcsr
& S_SLEEP
) {
1007 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1008 if (retval
!= ERROR_OK
)
1012 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1013 if (retval
!= ERROR_OK
)
1016 if (!target
->reset_halt
) {
1017 /* Set/Clear C_MASKINTS in a separate operation */
1018 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) {
1019 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1020 DBGKEY
| C_DEBUGEN
| C_HALT
);
1021 if (retval
!= ERROR_OK
)
1025 /* clear any debug flags before resuming */
1026 cortex_m3_clear_halt(target
);
1028 /* clear C_HALT in dhcsr reg */
1029 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
1031 /* Halt in debug on reset; endreset_event() restores DEMCR.
1033 * REVISIT catching BUSERR presumably helps to defend against
1034 * bad vector table entries. Should this include MMERR or
1037 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1038 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1039 if (retval
!= ERROR_OK
)
1043 if (jtag_reset_config
& RESET_HAS_SRST
) {
1044 /* default to asserting srst */
1046 adapter_assert_reset();
1048 /* Use a standard Cortex-M3 software reset mechanism.
1049 * We default to using VECRESET as it is supported on all current cores.
1050 * This has the disadvantage of not resetting the peripherals, so a
1051 * reset-init event handler is needed to perform any peripheral resets.
1053 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1054 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1055 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1056 if (retval
!= ERROR_OK
)
1059 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1060 ? "SYSRESETREQ" : "VECTRESET");
1062 if (reset_config
== CORTEX_M3_RESET_VECTRESET
) {
1063 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1064 "handler to reset any peripherals or configure hardware srst support.");
1068 /* I do not know why this is necessary, but it
1069 * fixes strange effects (step/resume cause NMI
1070 * after reset) on LM3S6918 -- Michael Schwingen
1073 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1074 if (retval
!= ERROR_OK
)
1079 target
->state
= TARGET_RESET
;
1080 jtag_add_sleep(50000);
1082 register_cache_invalidate(cortex_m3
->armv7m
.arm
.core_cache
);
1084 if (target
->reset_halt
) {
1085 retval
= target_halt(target
);
1086 if (retval
!= ERROR_OK
)
1093 static int cortex_m3_deassert_reset(struct target
*target
)
1095 LOG_DEBUG("target->state: %s",
1096 target_state_name(target
));
1098 /* deassert reset lines */
1099 adapter_deassert_reset();
1104 int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1109 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1110 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1112 if (breakpoint
->set
) {
1113 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1117 if (cortex_m3
->auto_bp_type
)
1118 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1120 if (breakpoint
->type
== BKPT_HARD
) {
1121 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
1123 if (fp_num
>= cortex_m3
->fp_num_code
) {
1124 LOG_ERROR("Can not find free FPB Comparator!");
1127 breakpoint
->set
= fp_num
+ 1;
1128 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1129 comparator_list
[fp_num
].used
= 1;
1130 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1131 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1132 comparator_list
[fp_num
].fpcr_value
);
1133 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1135 comparator_list
[fp_num
].fpcr_value
);
1136 if (!cortex_m3
->fpb_enabled
) {
1137 LOG_DEBUG("FPB wasn't enabled, do it now");
1138 target_write_u32(target
, FP_CTRL
, 3);
1140 } else if (breakpoint
->type
== BKPT_SOFT
) {
1143 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1144 * semihosting; don't use that. Otherwise the BKPT
1145 * parameter is arbitrary.
1147 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1148 retval
= target_read_memory(target
,
1149 breakpoint
->address
& 0xFFFFFFFE,
1150 breakpoint
->length
, 1,
1151 breakpoint
->orig_instr
);
1152 if (retval
!= ERROR_OK
)
1154 retval
= target_write_memory(target
,
1155 breakpoint
->address
& 0xFFFFFFFE,
1156 breakpoint
->length
, 1,
1158 if (retval
!= ERROR_OK
)
1160 breakpoint
->set
= true;
1163 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1164 breakpoint
->unique_id
,
1165 (int)(breakpoint
->type
),
1166 breakpoint
->address
,
1173 int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1176 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1177 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1179 if (!breakpoint
->set
) {
1180 LOG_WARNING("breakpoint not set");
1184 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1185 breakpoint
->unique_id
,
1186 (int)(breakpoint
->type
),
1187 breakpoint
->address
,
1191 if (breakpoint
->type
== BKPT_HARD
) {
1192 int fp_num
= breakpoint
->set
- 1;
1193 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
)) {
1194 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1197 comparator_list
[fp_num
].used
= 0;
1198 comparator_list
[fp_num
].fpcr_value
= 0;
1199 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1200 comparator_list
[fp_num
].fpcr_value
);
1202 /* restore original instruction (kept in target endianness) */
1203 if (breakpoint
->length
== 4) {
1204 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1205 breakpoint
->orig_instr
);
1206 if (retval
!= ERROR_OK
)
1209 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1210 breakpoint
->orig_instr
);
1211 if (retval
!= ERROR_OK
)
1215 breakpoint
->set
= false;
1220 int cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1222 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1224 if (cortex_m3
->auto_bp_type
)
1225 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1227 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1228 if (breakpoint
->type
== BKPT_HARD
) {
1229 LOG_INFO("flash patch comparator requested outside code memory region");
1230 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1233 if (breakpoint
->type
== BKPT_SOFT
) {
1234 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1235 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1239 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1)) {
1240 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1241 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1244 if ((breakpoint
->length
!= 2)) {
1245 LOG_INFO("only breakpoints of two bytes length supported");
1246 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1249 if (breakpoint
->type
== BKPT_HARD
)
1250 cortex_m3
->fp_code_available
--;
1252 return cortex_m3_set_breakpoint(target
, breakpoint
);
1255 int cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1257 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1259 /* REVISIT why check? FBP can be updated with core running ... */
1260 if (target
->state
!= TARGET_HALTED
) {
1261 LOG_WARNING("target not halted");
1262 return ERROR_TARGET_NOT_HALTED
;
1265 if (cortex_m3
->auto_bp_type
)
1266 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1268 if (breakpoint
->set
)
1269 cortex_m3_unset_breakpoint(target
, breakpoint
);
1271 if (breakpoint
->type
== BKPT_HARD
)
1272 cortex_m3
->fp_code_available
++;
1277 int cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1280 uint32_t mask
, temp
;
1281 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1283 /* watchpoint params were validated earlier */
1285 temp
= watchpoint
->length
;
1292 /* REVISIT Don't fully trust these "not used" records ... users
1293 * may set up breakpoints by hand, e.g. dual-address data value
1294 * watchpoint using comparator #1; comparator #0 matching cycle
1295 * count; send data trace info through ITM and TPIU; etc
1297 struct cortex_m3_dwt_comparator
*comparator
;
1299 for (comparator
= cortex_m3
->dwt_comparator_list
;
1300 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1301 comparator
++, dwt_num
++)
1303 if (dwt_num
>= cortex_m3
->dwt_num_comp
) {
1304 LOG_ERROR("Can not find free DWT Comparator");
1307 comparator
->used
= 1;
1308 watchpoint
->set
= dwt_num
+ 1;
1310 comparator
->comp
= watchpoint
->address
;
1311 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1314 comparator
->mask
= mask
;
1315 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1318 switch (watchpoint
->rw
) {
1320 comparator
->function
= 5;
1323 comparator
->function
= 6;
1326 comparator
->function
= 7;
1329 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1330 comparator
->function
);
1332 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1333 watchpoint
->unique_id
, dwt_num
,
1334 (unsigned) comparator
->comp
,
1335 (unsigned) comparator
->mask
,
1336 (unsigned) comparator
->function
);
1340 int cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1342 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1343 struct cortex_m3_dwt_comparator
*comparator
;
1346 if (!watchpoint
->set
) {
1347 LOG_WARNING("watchpoint (wpid: %d) not set",
1348 watchpoint
->unique_id
);
1352 dwt_num
= watchpoint
->set
- 1;
1354 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1355 watchpoint
->unique_id
, dwt_num
,
1356 (unsigned) watchpoint
->address
);
1358 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
)) {
1359 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1363 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1364 comparator
->used
= 0;
1365 comparator
->function
= 0;
1366 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1367 comparator
->function
);
1369 watchpoint
->set
= false;
1374 int cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1376 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1378 if (cortex_m3
->dwt_comp_available
< 1) {
1379 LOG_DEBUG("no comparators?");
1380 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1383 /* hardware doesn't support data value masking */
1384 if (watchpoint
->mask
!= ~(uint32_t)0) {
1385 LOG_DEBUG("watchpoint value masks not supported");
1386 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1389 /* hardware allows address masks of up to 32K */
1392 for (mask
= 0; mask
< 16; mask
++) {
1393 if ((1u << mask
) == watchpoint
->length
)
1397 LOG_DEBUG("unsupported watchpoint length");
1398 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1400 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1401 LOG_DEBUG("watchpoint address is unaligned");
1402 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1405 /* Caller doesn't seem to be able to describe watching for data
1406 * values of zero; that flags "no value".
1408 * REVISIT This DWT may well be able to watch for specific data
1409 * values. Requires comparator #1 to set DATAVMATCH and match
1410 * the data, and another comparator (DATAVADDR0) matching addr.
1412 if (watchpoint
->value
) {
1413 LOG_DEBUG("data value watchpoint not YET supported");
1414 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1417 cortex_m3
->dwt_comp_available
--;
1418 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1423 int cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1425 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1427 /* REVISIT why check? DWT can be updated with core running ... */
1428 if (target
->state
!= TARGET_HALTED
) {
1429 LOG_WARNING("target not halted");
1430 return ERROR_TARGET_NOT_HALTED
;
1433 if (watchpoint
->set
)
1434 cortex_m3_unset_watchpoint(target
, watchpoint
);
1436 cortex_m3
->dwt_comp_available
++;
1437 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1442 void cortex_m3_enable_watchpoints(struct target
*target
)
1444 struct watchpoint
*watchpoint
= target
->watchpoints
;
1446 /* set any pending watchpoints */
1447 while (watchpoint
) {
1448 if (!watchpoint
->set
)
1449 cortex_m3_set_watchpoint(target
, watchpoint
);
1450 watchpoint
= watchpoint
->next
;
1454 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1455 uint32_t num
, uint32_t *value
)
1458 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1459 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1461 /* NOTE: we "know" here that the register identifiers used
1462 * in the v7m header match the Cortex-M3 Debug Core Register
1463 * Selector values for R0..R15, xPSR, MSP, and PSP.
1467 /* read a normal core register */
1468 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1470 if (retval
!= ERROR_OK
) {
1471 LOG_ERROR("JTAG failure %i", retval
);
1472 return ERROR_JTAG_DEVICE_ERROR
;
1474 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1477 case ARMV7M_PRIMASK
:
1478 case ARMV7M_BASEPRI
:
1479 case ARMV7M_FAULTMASK
:
1480 case ARMV7M_CONTROL
:
1481 /* Cortex-M3 packages these four registers as bitfields
1482 * in one Debug Core register. So say r0 and r2 docs;
1483 * it was removed from r1 docs, but still works.
1485 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1488 case ARMV7M_PRIMASK
:
1489 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1492 case ARMV7M_BASEPRI
:
1493 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1496 case ARMV7M_FAULTMASK
:
1497 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1500 case ARMV7M_CONTROL
:
1501 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1505 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1509 return ERROR_COMMAND_SYNTAX_ERROR
;
1515 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1516 uint32_t num
, uint32_t value
)
1520 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1521 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1523 /* NOTE: we "know" here that the register identifiers used
1524 * in the v7m header match the Cortex-M3 Debug Core Register
1525 * Selector values for R0..R15, xPSR, MSP, and PSP.
1529 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1530 if (retval
!= ERROR_OK
) {
1533 LOG_ERROR("JTAG failure");
1534 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1535 r
->dirty
= r
->valid
;
1536 return ERROR_JTAG_DEVICE_ERROR
;
1538 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1541 case ARMV7M_PRIMASK
:
1542 case ARMV7M_BASEPRI
:
1543 case ARMV7M_FAULTMASK
:
1544 case ARMV7M_CONTROL
:
1545 /* Cortex-M3 packages these four registers as bitfields
1546 * in one Debug Core register. So say r0 and r2 docs;
1547 * it was removed from r1 docs, but still works.
1549 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1552 case ARMV7M_PRIMASK
:
1553 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1556 case ARMV7M_BASEPRI
:
1557 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1560 case ARMV7M_FAULTMASK
:
1561 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1564 case ARMV7M_CONTROL
:
1565 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1569 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1571 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1575 return ERROR_COMMAND_SYNTAX_ERROR
;
1581 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1582 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1584 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1585 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1586 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1588 if (armv7m
->arm
.is_armv6m
) {
1589 /* armv6m does not handle unaligned memory access */
1590 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1591 return ERROR_TARGET_UNALIGNED_ACCESS
;
1594 /* cortex_m3 handles unaligned memory access */
1595 if (count
&& buffer
) {
1598 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
, true);
1601 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1604 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1612 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1613 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1615 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1616 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1617 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1619 if (armv7m
->arm
.is_armv6m
) {
1620 /* armv6m does not handle unaligned memory access */
1621 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1622 return ERROR_TARGET_UNALIGNED_ACCESS
;
1625 if (count
&& buffer
) {
1628 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
, true);
1631 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1634 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1642 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1643 struct target
*target
)
1645 armv7m_build_reg_cache(target
);
1649 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1650 * on r/w if the core is not running, and clear on resume or reset ... or
1651 * at least, in a post_restore_context() method.
1654 struct dwt_reg_state
{
1655 struct target
*target
;
1657 uint32_t value
; /* scratch/cache */
1660 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1662 struct dwt_reg_state
*state
= reg
->arch_info
;
1664 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1667 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1669 struct dwt_reg_state
*state
= reg
->arch_info
;
1671 return target_write_u32(state
->target
, state
->addr
,
1672 buf_get_u32(buf
, 0, reg
->size
));
1681 static struct dwt_reg dwt_base_regs
[] = {
1682 { DWT_CTRL
, "dwt_ctrl", 32, },
1683 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1684 * increments while the core is asleep.
1686 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1687 /* plus some 8 bit counters, useful for profiling with TPIU */
1690 static struct dwt_reg dwt_comp
[] = {
1691 #define DWT_COMPARATOR(i) \
1692 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1693 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1694 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1699 #undef DWT_COMPARATOR
1702 static const struct reg_arch_type dwt_reg_type
= {
1703 .get
= cortex_m3_dwt_get_reg
,
1704 .set
= cortex_m3_dwt_set_reg
,
1707 static void cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1709 struct dwt_reg_state
*state
;
1711 state
= calloc(1, sizeof *state
);
1714 state
->addr
= d
->addr
;
1719 r
->value
= &state
->value
;
1720 r
->arch_info
= state
;
1721 r
->type
= &dwt_reg_type
;
1724 void cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1727 struct reg_cache
*cache
;
1728 struct cortex_m3_dwt_comparator
*comparator
;
1731 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1733 LOG_DEBUG("no DWT");
1737 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1738 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1739 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1740 sizeof(struct cortex_m3_dwt_comparator
));
1741 if (!cm3
->dwt_comparator_list
) {
1743 cm3
->dwt_num_comp
= 0;
1744 LOG_ERROR("out of mem");
1748 cache
= calloc(1, sizeof *cache
);
1751 free(cm3
->dwt_comparator_list
);
1754 cache
->name
= "cortex-m3 dwt registers";
1755 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1756 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1757 if (!cache
->reg_list
) {
1762 for (reg
= 0; reg
< 2; reg
++)
1763 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1764 dwt_base_regs
+ reg
);
1766 comparator
= cm3
->dwt_comparator_list
;
1767 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1770 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1771 for (j
= 0; j
< 3; j
++, reg
++)
1772 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1773 dwt_comp
+ 3 * i
+ j
);
1775 /* make sure we clear any watchpoints enabled on the target */
1776 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1779 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1780 cm3
->dwt_cache
= cache
;
1782 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1783 dwtcr
, cm3
->dwt_num_comp
,
1784 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1786 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1787 * implement single-address data value watchpoints ... so we
1788 * won't need to check it later, when asked to set one up.
1792 #define MVFR0 0xe000ef40
1793 #define MVFR1 0xe000ef44
1795 #define MVFR0_DEFAULT_M4 0x10110021
1796 #define MVFR1_DEFAULT_M4 0x11000011
1798 int cortex_m3_examine(struct target
*target
)
1801 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1803 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1804 struct adiv5_dap
*swjdp
= cortex_m3
->armv7m
.arm
.dap
;
1805 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1807 /* stlink shares the examine handler but does not support
1809 if (!armv7m
->stlink
) {
1810 retval
= ahbap_debugport_init(swjdp
);
1811 if (retval
!= ERROR_OK
)
1815 if (!target_was_examined(target
)) {
1816 target_set_examined(target
);
1818 /* Read from Device Identification Registers */
1819 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1820 if (retval
!= ERROR_OK
)
1824 i
= (cpuid
>> 4) & 0xf;
1826 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1827 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1828 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1830 /* test for floating point feature on cortex-m4 */
1832 target_read_u32(target
, MVFR0
, &mvfr0
);
1833 target_read_u32(target
, MVFR1
, &mvfr1
);
1835 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1836 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1837 armv7m
->fp_feature
= FPv4_SP
;
1839 } else if (i
== 0) {
1840 /* Cortex-M0 does not support unaligned memory access */
1841 armv7m
->arm
.is_armv6m
= true;
1844 if (i
== 4 || i
== 3) {
1845 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1846 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
1849 /* NOTE: FPB and DWT are both optional. */
1852 target_read_u32(target
, FP_CTRL
, &fpcr
);
1853 cortex_m3
->auto_bp_type
= 1;
1854 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits
1858 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1859 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1860 cortex_m3
->fp_comparator_list
= calloc(
1861 cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
,
1862 sizeof(struct cortex_m3_fp_comparator
));
1863 cortex_m3
->fpb_enabled
= fpcr
& 1;
1864 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++) {
1865 cortex_m3
->fp_comparator_list
[i
].type
=
1866 (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1867 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1869 /* make sure we clear any breakpoints enabled on the target */
1870 target_write_u32(target
, cortex_m3
->fp_comparator_list
[i
].fpcr_address
, 0);
1872 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
1874 cortex_m3
->fp_num_code
,
1875 cortex_m3
->fp_num_lit
);
1878 cortex_m3_dwt_setup(cortex_m3
, target
);
1880 /* These hardware breakpoints only work for code in flash! */
1881 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1882 target_name(target
),
1883 cortex_m3
->fp_num_code
,
1884 cortex_m3
->dwt_num_comp
);
1890 static int cortex_m3_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1895 mem_ap_read_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 1, DCB_DCRDR
);
1896 *ctrl
= (uint8_t)dcrdr
;
1897 *value
= (uint8_t)(dcrdr
>> 8);
1899 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1901 /* write ack back to software dcc register
1902 * signify we have read data */
1903 if (dcrdr
& (1 << 0)) {
1905 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 1, DCB_DCRDR
);
1906 if (retval
!= ERROR_OK
)
1913 static int cortex_m3_target_request_data(struct target
*target
,
1914 uint32_t size
, uint8_t *buffer
)
1916 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1917 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1922 for (i
= 0; i
< (size
* 4); i
++) {
1923 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1930 static int cortex_m3_handle_target_request(void *priv
)
1932 struct target
*target
= priv
;
1933 if (!target_was_examined(target
))
1935 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1936 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1938 if (!target
->dbg_msg_enabled
)
1941 if (target
->state
== TARGET_RUNNING
) {
1945 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1947 /* check if we have data */
1948 if (ctrl
& (1 << 0)) {
1951 /* we assume target is quick enough */
1953 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1954 request
|= (data
<< 8);
1955 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1956 request
|= (data
<< 16);
1957 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1958 request
|= (data
<< 24);
1959 target_request(target
, request
);
1966 static int cortex_m3_init_arch_info(struct target
*target
,
1967 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1970 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1972 armv7m_init_arch_info(target
, armv7m
);
1974 /* prepare JTAG information for the new target */
1975 cortex_m3
->jtag_info
.tap
= tap
;
1976 cortex_m3
->jtag_info
.scann_size
= 4;
1978 /* default reset mode is to use srst if fitted
1979 * if not it will use CORTEX_M3_RESET_VECTRESET */
1980 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
1982 armv7m
->arm
.dap
= &armv7m
->dap
;
1984 /* Leave (only) generic DAP stuff for debugport_init(); */
1985 armv7m
->dap
.jtag_info
= &cortex_m3
->jtag_info
;
1986 armv7m
->dap
.memaccess_tck
= 8;
1988 /* Cortex-M3/M4 has 4096 bytes autoincrement range
1989 * but set a safe default to 1024 to support Cortex-M0
1990 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
1991 armv7m
->dap
.tar_autoincr_block
= (1 << 10);
1993 /* register arch-specific functions */
1994 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1996 armv7m
->post_debug_entry
= NULL
;
1998 armv7m
->pre_restore_context
= NULL
;
2000 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
2001 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
2003 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
2005 retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
);
2006 if (retval
!= ERROR_OK
)
2012 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
2014 struct cortex_m3_common
*cortex_m3
= calloc(1, sizeof(struct cortex_m3_common
));
2016 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
2017 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
2022 /*--------------------------------------------------------------------------*/
2024 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
2025 struct cortex_m3_common
*cm3
)
2027 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
2028 command_print(cmd_ctx
, "target is not a Cortex-M");
2029 return ERROR_TARGET_INVALID
;
2035 * Only stuff below this line should need to verify that its target
2036 * is a Cortex-M3. Everything else should have indirected through the
2037 * cortexm3_target structure, which is only used with CM3 targets.
2040 static const struct {
2044 { "hard_err", VC_HARDERR
, },
2045 { "int_err", VC_INTERR
, },
2046 { "bus_err", VC_BUSERR
, },
2047 { "state_err", VC_STATERR
, },
2048 { "chk_err", VC_CHKERR
, },
2049 { "nocp_err", VC_NOCPERR
, },
2050 { "mm_err", VC_MMERR
, },
2051 { "reset", VC_CORERESET
, },
2054 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
2056 struct target
*target
= get_current_target(CMD_CTX
);
2057 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2058 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2059 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
2063 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2064 if (retval
!= ERROR_OK
)
2067 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2068 if (retval
!= ERROR_OK
)
2074 if (CMD_ARGC
== 1) {
2075 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2076 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2077 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2078 | VC_MMERR
| VC_CORERESET
;
2080 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2083 while (CMD_ARGC
-- > 0) {
2085 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2086 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2088 catch |= vec_ids
[i
].mask
;
2091 if (i
== ARRAY_SIZE(vec_ids
)) {
2092 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2093 return ERROR_COMMAND_SYNTAX_ERROR
;
2097 /* For now, armv7m->demcr only stores vector catch flags. */
2098 armv7m
->demcr
= catch;
2103 /* write, but don't assume it stuck (why not??) */
2104 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2105 if (retval
!= ERROR_OK
)
2107 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2108 if (retval
!= ERROR_OK
)
2111 /* FIXME be sure to clear DEMCR on clean server shutdown.
2112 * Otherwise the vector catch hardware could fire when there's
2113 * no debugger hooked up, causing much confusion...
2117 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2118 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2119 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2125 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
2127 struct target
*target
= get_current_target(CMD_CTX
);
2128 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2131 static const Jim_Nvp nvp_maskisr_modes
[] = {
2132 { .name
= "auto", .value
= CORTEX_M3_ISRMASK_AUTO
},
2133 { .name
= "off", .value
= CORTEX_M3_ISRMASK_OFF
},
2134 { .name
= "on", .value
= CORTEX_M3_ISRMASK_ON
},
2135 { .name
= NULL
, .value
= -1 },
2140 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2141 if (retval
!= ERROR_OK
)
2144 if (target
->state
!= TARGET_HALTED
) {
2145 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2150 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2151 if (n
->name
== NULL
)
2152 return ERROR_COMMAND_SYNTAX_ERROR
;
2153 cortex_m3
->isrmasking_mode
= n
->value
;
2156 if (cortex_m3
->isrmasking_mode
== CORTEX_M3_ISRMASK_ON
)
2157 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2159 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2162 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m3
->isrmasking_mode
);
2163 command_print(CMD_CTX
, "cortex_m interrupt mask %s", n
->name
);
2168 COMMAND_HANDLER(handle_cortex_m3_reset_config_command
)
2170 struct target
*target
= get_current_target(CMD_CTX
);
2171 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2175 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2176 if (retval
!= ERROR_OK
)
2180 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2181 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SYSRESETREQ
;
2182 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2183 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2186 switch (cortex_m3
->soft_reset_config
) {
2187 case CORTEX_M3_RESET_SYSRESETREQ
:
2188 reset_config
= "sysresetreq";
2191 case CORTEX_M3_RESET_VECTRESET
:
2192 reset_config
= "vectreset";
2196 reset_config
= "unknown";
2200 command_print(CMD_CTX
, "cortex_m reset_config %s", reset_config
);
2205 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2208 .handler
= handle_cortex_m3_mask_interrupts_command
,
2209 .mode
= COMMAND_EXEC
,
2210 .help
= "mask cortex_m interrupts",
2211 .usage
= "['auto'|'on'|'off']",
2214 .name
= "vector_catch",
2215 .handler
= handle_cortex_m3_vector_catch_command
,
2216 .mode
= COMMAND_EXEC
,
2217 .help
= "configure hardware vectors to trigger debug entry",
2218 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2221 .name
= "reset_config",
2222 .handler
= handle_cortex_m3_reset_config_command
,
2223 .mode
= COMMAND_ANY
,
2224 .help
= "configure software reset handling",
2225 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2227 COMMAND_REGISTRATION_DONE
2229 static const struct command_registration cortex_m3_command_handlers
[] = {
2231 .chain
= armv7m_command_handlers
,
2235 .mode
= COMMAND_EXEC
,
2236 .help
= "Cortex-M command group",
2238 .chain
= cortex_m3_exec_command_handlers
,
2240 COMMAND_REGISTRATION_DONE
2243 struct target_type cortexm3_target
= {
2245 .deprecated_name
= "cortex_m3",
2247 .poll
= cortex_m3_poll
,
2248 .arch_state
= armv7m_arch_state
,
2250 .target_request_data
= cortex_m3_target_request_data
,
2252 .halt
= cortex_m3_halt
,
2253 .resume
= cortex_m3_resume
,
2254 .step
= cortex_m3_step
,
2256 .assert_reset
= cortex_m3_assert_reset
,
2257 .deassert_reset
= cortex_m3_deassert_reset
,
2258 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2260 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2262 .read_memory
= cortex_m3_read_memory
,
2263 .write_memory
= cortex_m3_write_memory
,
2264 .checksum_memory
= armv7m_checksum_memory
,
2265 .blank_check_memory
= armv7m_blank_check_memory
,
2267 .run_algorithm
= armv7m_run_algorithm
,
2268 .start_algorithm
= armv7m_start_algorithm
,
2269 .wait_algorithm
= armv7m_wait_algorithm
,
2271 .add_breakpoint
= cortex_m3_add_breakpoint
,
2272 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2273 .add_watchpoint
= cortex_m3_add_watchpoint
,
2274 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2276 .commands
= cortex_m3_command_handlers
,
2277 .target_create
= cortex_m3_target_create
,
2278 .init_target
= cortex_m3_init_target
,
2279 .examine
= cortex_m3_examine
,
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