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cortex_m: use cortex_m_write_debug_halt_mask() in cortex_m_single_step_core()
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_adi_v5.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42 #include <helper/time_support.h>
43 #include <rtt/rtt.h>
44
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FPB remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
50 *
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
53 * any longer.
54 */
55
56 /* Supported Cortex-M Cores */
57 static const struct cortex_m_part_info cortex_m_parts[] = {
58 {
59 .partno = CORTEX_M0_PARTNO,
60 .name = "Cortex-M0",
61 .arch = ARM_ARCH_V6M,
62 },
63 {
64 .partno = CORTEX_M0P_PARTNO,
65 .name = "Cortex-M0+",
66 .arch = ARM_ARCH_V6M,
67 },
68 {
69 .partno = CORTEX_M1_PARTNO,
70 .name = "Cortex-M1",
71 .arch = ARM_ARCH_V6M,
72 },
73 {
74 .partno = CORTEX_M3_PARTNO,
75 .name = "Cortex-M3",
76 .arch = ARM_ARCH_V7M,
77 .flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
78 },
79 {
80 .partno = CORTEX_M4_PARTNO,
81 .name = "Cortex-M4",
82 .arch = ARM_ARCH_V7M,
83 .flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
84 },
85 {
86 .partno = CORTEX_M7_PARTNO,
87 .name = "Cortex-M7",
88 .arch = ARM_ARCH_V7M,
89 .flags = CORTEX_M_F_HAS_FPV5,
90 },
91 {
92 .partno = CORTEX_M23_PARTNO,
93 .name = "Cortex-M23",
94 .arch = ARM_ARCH_V8M,
95 },
96 {
97 .partno = CORTEX_M33_PARTNO,
98 .name = "Cortex-M33",
99 .arch = ARM_ARCH_V8M,
100 .flags = CORTEX_M_F_HAS_FPV5,
101 },
102 {
103 .partno = CORTEX_M35P_PARTNO,
104 .name = "Cortex-M35P",
105 .arch = ARM_ARCH_V8M,
106 .flags = CORTEX_M_F_HAS_FPV5,
107 },
108 {
109 .partno = CORTEX_M55_PARTNO,
110 .name = "Cortex-M55",
111 .arch = ARM_ARCH_V8M,
112 .flags = CORTEX_M_F_HAS_FPV5,
113 },
114 };
115
116 /* forward declarations */
117 static int cortex_m_store_core_reg_u32(struct target *target,
118 uint32_t num, uint32_t value);
119 static void cortex_m_dwt_free(struct target *target);
120
121 static int cortex_m_load_core_reg_u32(struct target *target,
122 uint32_t regsel, uint32_t *value)
123 {
124 struct armv7m_common *armv7m = target_to_armv7m(target);
125 int retval;
126 uint32_t dcrdr;
127
128 /* because the DCB_DCRDR is used for the emulated dcc channel
129 * we have to save/restore the DCB_DCRDR when used */
130 if (target->dbg_msg_enabled) {
131 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
132 if (retval != ERROR_OK)
133 return retval;
134 }
135
136 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
137 if (retval != ERROR_OK)
138 return retval;
139
140 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
141 if (retval != ERROR_OK)
142 return retval;
143
144 if (target->dbg_msg_enabled) {
145 /* restore DCB_DCRDR - this needs to be in a separate
146 * transaction otherwise the emulated DCC channel breaks */
147 if (retval == ERROR_OK)
148 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
149 }
150
151 return retval;
152 }
153
154 static int cortex_m_store_core_reg_u32(struct target *target,
155 uint32_t regsel, uint32_t value)
156 {
157 struct armv7m_common *armv7m = target_to_armv7m(target);
158 int retval;
159 uint32_t dcrdr;
160
161 /* because the DCB_DCRDR is used for the emulated dcc channel
162 * we have to save/restore the DCB_DCRDR when used */
163 if (target->dbg_msg_enabled) {
164 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
165 if (retval != ERROR_OK)
166 return retval;
167 }
168
169 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
170 if (retval != ERROR_OK)
171 return retval;
172
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR);
174 if (retval != ERROR_OK)
175 return retval;
176
177 if (target->dbg_msg_enabled) {
178 /* restore DCB_DCRDR - this needs to be in a separate
179 * transaction otherwise the emulated DCC channel breaks */
180 if (retval == ERROR_OK)
181 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
182 }
183
184 return retval;
185 }
186
187 static int cortex_m_write_debug_halt_mask(struct target *target,
188 uint32_t mask_on, uint32_t mask_off)
189 {
190 struct cortex_m_common *cortex_m = target_to_cm(target);
191 struct armv7m_common *armv7m = &cortex_m->armv7m;
192
193 /* mask off status bits */
194 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
195 /* create new register mask */
196 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
197
198 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
199 }
200
201 static int cortex_m_set_maskints(struct target *target, bool mask)
202 {
203 struct cortex_m_common *cortex_m = target_to_cm(target);
204 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
205 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
206 else
207 return ERROR_OK;
208 }
209
210 static int cortex_m_set_maskints_for_halt(struct target *target)
211 {
212 struct cortex_m_common *cortex_m = target_to_cm(target);
213 switch (cortex_m->isrmasking_mode) {
214 case CORTEX_M_ISRMASK_AUTO:
215 /* interrupts taken at resume, whether for step or run -> no mask */
216 return cortex_m_set_maskints(target, false);
217
218 case CORTEX_M_ISRMASK_OFF:
219 /* interrupts never masked */
220 return cortex_m_set_maskints(target, false);
221
222 case CORTEX_M_ISRMASK_ON:
223 /* interrupts always masked */
224 return cortex_m_set_maskints(target, true);
225
226 case CORTEX_M_ISRMASK_STEPONLY:
227 /* interrupts masked for single step only -> mask now if MASKINTS
228 * erratum, otherwise only mask before stepping */
229 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
230 }
231 return ERROR_OK;
232 }
233
234 static int cortex_m_set_maskints_for_run(struct target *target)
235 {
236 switch (target_to_cm(target)->isrmasking_mode) {
237 case CORTEX_M_ISRMASK_AUTO:
238 /* interrupts taken at resume, whether for step or run -> no mask */
239 return cortex_m_set_maskints(target, false);
240
241 case CORTEX_M_ISRMASK_OFF:
242 /* interrupts never masked */
243 return cortex_m_set_maskints(target, false);
244
245 case CORTEX_M_ISRMASK_ON:
246 /* interrupts always masked */
247 return cortex_m_set_maskints(target, true);
248
249 case CORTEX_M_ISRMASK_STEPONLY:
250 /* interrupts masked for single step only -> no mask */
251 return cortex_m_set_maskints(target, false);
252 }
253 return ERROR_OK;
254 }
255
256 static int cortex_m_set_maskints_for_step(struct target *target)
257 {
258 switch (target_to_cm(target)->isrmasking_mode) {
259 case CORTEX_M_ISRMASK_AUTO:
260 /* the auto-interrupt should already be done -> mask */
261 return cortex_m_set_maskints(target, true);
262
263 case CORTEX_M_ISRMASK_OFF:
264 /* interrupts never masked */
265 return cortex_m_set_maskints(target, false);
266
267 case CORTEX_M_ISRMASK_ON:
268 /* interrupts always masked */
269 return cortex_m_set_maskints(target, true);
270
271 case CORTEX_M_ISRMASK_STEPONLY:
272 /* interrupts masked for single step only -> mask */
273 return cortex_m_set_maskints(target, true);
274 }
275 return ERROR_OK;
276 }
277
278 static int cortex_m_clear_halt(struct target *target)
279 {
280 struct cortex_m_common *cortex_m = target_to_cm(target);
281 struct armv7m_common *armv7m = &cortex_m->armv7m;
282 int retval;
283
284 /* clear step if any */
285 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
286
287 /* Read Debug Fault Status Register */
288 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
289 if (retval != ERROR_OK)
290 return retval;
291
292 /* Clear Debug Fault Status */
293 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
294 if (retval != ERROR_OK)
295 return retval;
296 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
297
298 return ERROR_OK;
299 }
300
301 static int cortex_m_single_step_core(struct target *target)
302 {
303 struct cortex_m_common *cortex_m = target_to_cm(target);
304 int retval;
305
306 /* Mask interrupts before clearing halt, if not done already. This avoids
307 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
308 * HALT can put the core into an unknown state.
309 */
310 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
311 retval = cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
312 if (retval != ERROR_OK)
313 return retval;
314 }
315 retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
316 if (retval != ERROR_OK)
317 return retval;
318 LOG_DEBUG(" ");
319
320 /* restore dhcsr reg */
321 cortex_m_clear_halt(target);
322
323 return ERROR_OK;
324 }
325
326 static int cortex_m_enable_fpb(struct target *target)
327 {
328 int retval = target_write_u32(target, FP_CTRL, 3);
329 if (retval != ERROR_OK)
330 return retval;
331
332 /* check the fpb is actually enabled */
333 uint32_t fpctrl;
334 retval = target_read_u32(target, FP_CTRL, &fpctrl);
335 if (retval != ERROR_OK)
336 return retval;
337
338 if (fpctrl & 1)
339 return ERROR_OK;
340
341 return ERROR_FAIL;
342 }
343
344 static int cortex_m_endreset_event(struct target *target)
345 {
346 int retval;
347 uint32_t dcb_demcr;
348 struct cortex_m_common *cortex_m = target_to_cm(target);
349 struct armv7m_common *armv7m = &cortex_m->armv7m;
350 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
351 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
352 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
353
354 /* REVISIT The four debug monitor bits are currently ignored... */
355 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
356 if (retval != ERROR_OK)
357 return retval;
358 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
359
360 /* this register is used for emulated dcc channel */
361 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
362 if (retval != ERROR_OK)
363 return retval;
364
365 /* Enable debug requests */
366 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
367 if (retval != ERROR_OK)
368 return retval;
369 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
370 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
371 if (retval != ERROR_OK)
372 return retval;
373 }
374
375 /* Restore proper interrupt masking setting for running CPU. */
376 cortex_m_set_maskints_for_run(target);
377
378 /* Enable features controlled by ITM and DWT blocks, and catch only
379 * the vectors we were told to pay attention to.
380 *
381 * Target firmware is responsible for all fault handling policy
382 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
383 * or manual updates to the NVIC SHCSR and CCR registers.
384 */
385 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
386 if (retval != ERROR_OK)
387 return retval;
388
389 /* Paranoia: evidently some (early?) chips don't preserve all the
390 * debug state (including FPB, DWT, etc) across reset...
391 */
392
393 /* Enable FPB */
394 retval = cortex_m_enable_fpb(target);
395 if (retval != ERROR_OK) {
396 LOG_ERROR("Failed to enable the FPB");
397 return retval;
398 }
399
400 cortex_m->fpb_enabled = true;
401
402 /* Restore FPB registers */
403 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
404 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
405 if (retval != ERROR_OK)
406 return retval;
407 }
408
409 /* Restore DWT registers */
410 for (unsigned int i = 0; i < cortex_m->dwt_num_comp; i++) {
411 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
412 dwt_list[i].comp);
413 if (retval != ERROR_OK)
414 return retval;
415 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
416 dwt_list[i].mask);
417 if (retval != ERROR_OK)
418 return retval;
419 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
420 dwt_list[i].function);
421 if (retval != ERROR_OK)
422 return retval;
423 }
424 retval = dap_run(swjdp);
425 if (retval != ERROR_OK)
426 return retval;
427
428 register_cache_invalidate(armv7m->arm.core_cache);
429
430 /* make sure we have latest dhcsr flags */
431 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
432
433 return retval;
434 }
435
436 static int cortex_m_examine_debug_reason(struct target *target)
437 {
438 struct cortex_m_common *cortex_m = target_to_cm(target);
439
440 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
441 * only check the debug reason if we don't know it already */
442
443 if ((target->debug_reason != DBG_REASON_DBGRQ)
444 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
445 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
446 target->debug_reason = DBG_REASON_BREAKPOINT;
447 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
448 target->debug_reason = DBG_REASON_WPTANDBKPT;
449 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
450 target->debug_reason = DBG_REASON_WATCHPOINT;
451 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
452 target->debug_reason = DBG_REASON_BREAKPOINT;
453 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
454 target->debug_reason = DBG_REASON_DBGRQ;
455 else /* HALTED */
456 target->debug_reason = DBG_REASON_UNDEFINED;
457 }
458
459 return ERROR_OK;
460 }
461
462 static int cortex_m_examine_exception_reason(struct target *target)
463 {
464 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
465 struct armv7m_common *armv7m = target_to_armv7m(target);
466 struct adiv5_dap *swjdp = armv7m->arm.dap;
467 int retval;
468
469 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
470 if (retval != ERROR_OK)
471 return retval;
472 switch (armv7m->exception_number) {
473 case 2: /* NMI */
474 break;
475 case 3: /* Hard Fault */
476 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
477 if (retval != ERROR_OK)
478 return retval;
479 if (except_sr & 0x40000000) {
480 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
481 if (retval != ERROR_OK)
482 return retval;
483 }
484 break;
485 case 4: /* Memory Management */
486 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
487 if (retval != ERROR_OK)
488 return retval;
489 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
490 if (retval != ERROR_OK)
491 return retval;
492 break;
493 case 5: /* Bus Fault */
494 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
495 if (retval != ERROR_OK)
496 return retval;
497 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
498 if (retval != ERROR_OK)
499 return retval;
500 break;
501 case 6: /* Usage Fault */
502 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
503 if (retval != ERROR_OK)
504 return retval;
505 break;
506 case 7: /* Secure Fault */
507 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
508 if (retval != ERROR_OK)
509 return retval;
510 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
511 if (retval != ERROR_OK)
512 return retval;
513 break;
514 case 11: /* SVCall */
515 break;
516 case 12: /* Debug Monitor */
517 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
518 if (retval != ERROR_OK)
519 return retval;
520 break;
521 case 14: /* PendSV */
522 break;
523 case 15: /* SysTick */
524 break;
525 default:
526 except_sr = 0;
527 break;
528 }
529 retval = dap_run(swjdp);
530 if (retval == ERROR_OK)
531 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
532 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
533 armv7m_exception_string(armv7m->exception_number),
534 shcsr, except_sr, cfsr, except_ar);
535 return retval;
536 }
537
538 static int cortex_m_debug_entry(struct target *target)
539 {
540 int i;
541 uint32_t xPSR;
542 int retval;
543 struct cortex_m_common *cortex_m = target_to_cm(target);
544 struct armv7m_common *armv7m = &cortex_m->armv7m;
545 struct arm *arm = &armv7m->arm;
546 struct reg *r;
547
548 LOG_DEBUG(" ");
549
550 /* Do this really early to minimize the window where the MASKINTS erratum
551 * can pile up pending interrupts. */
552 cortex_m_set_maskints_for_halt(target);
553
554 cortex_m_clear_halt(target);
555 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
556 if (retval != ERROR_OK)
557 return retval;
558
559 retval = armv7m->examine_debug_reason(target);
560 if (retval != ERROR_OK)
561 return retval;
562
563 /* examine PE security state */
564 bool secure_state = false;
565 if (armv7m->arm.arch == ARM_ARCH_V8M) {
566 uint32_t dscsr;
567
568 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
569 if (retval != ERROR_OK)
570 return retval;
571
572 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
573 }
574
575 /* Examine target state and mode
576 * First load register accessible through core debug port */
577 int num_regs = arm->core_cache->num_regs;
578
579 for (i = 0; i < num_regs; i++) {
580 r = &armv7m->arm.core_cache->reg_list[i];
581 if (r->exist && !r->valid)
582 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
583 }
584
585 r = arm->cpsr;
586 xPSR = buf_get_u32(r->value, 0, 32);
587
588 /* Are we in an exception handler */
589 if (xPSR & 0x1FF) {
590 armv7m->exception_number = (xPSR & 0x1FF);
591
592 arm->core_mode = ARM_MODE_HANDLER;
593 arm->map = armv7m_msp_reg_map;
594 } else {
595 unsigned control = buf_get_u32(arm->core_cache
596 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
597
598 /* is this thread privileged? */
599 arm->core_mode = control & 1
600 ? ARM_MODE_USER_THREAD
601 : ARM_MODE_THREAD;
602
603 /* which stack is it using? */
604 if (control & 2)
605 arm->map = armv7m_psp_reg_map;
606 else
607 arm->map = armv7m_msp_reg_map;
608
609 armv7m->exception_number = 0;
610 }
611
612 if (armv7m->exception_number)
613 cortex_m_examine_exception_reason(target);
614
615 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
616 arm_mode_name(arm->core_mode),
617 buf_get_u32(arm->pc->value, 0, 32),
618 secure_state ? "Secure" : "Non-Secure",
619 target_state_name(target));
620
621 if (armv7m->post_debug_entry) {
622 retval = armv7m->post_debug_entry(target);
623 if (retval != ERROR_OK)
624 return retval;
625 }
626
627 return ERROR_OK;
628 }
629
630 static int cortex_m_poll(struct target *target)
631 {
632 int detected_failure = ERROR_OK;
633 int retval = ERROR_OK;
634 enum target_state prev_target_state = target->state;
635 struct cortex_m_common *cortex_m = target_to_cm(target);
636 struct armv7m_common *armv7m = &cortex_m->armv7m;
637
638 /* Read from Debug Halting Control and Status Register */
639 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
640 if (retval != ERROR_OK) {
641 target->state = TARGET_UNKNOWN;
642 return retval;
643 }
644
645 /* Recover from lockup. See ARMv7-M architecture spec,
646 * section B1.5.15 "Unrecoverable exception cases".
647 */
648 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
649 LOG_ERROR("%s -- clearing lockup after double fault",
650 target_name(target));
651 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
652 target->debug_reason = DBG_REASON_DBGRQ;
653
654 /* We have to execute the rest (the "finally" equivalent, but
655 * still throw this exception again).
656 */
657 detected_failure = ERROR_FAIL;
658
659 /* refresh status bits */
660 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
661 if (retval != ERROR_OK)
662 return retval;
663 }
664
665 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
666 if (target->state != TARGET_RESET) {
667 target->state = TARGET_RESET;
668 LOG_INFO("%s: external reset detected", target_name(target));
669 }
670 return ERROR_OK;
671 }
672
673 if (target->state == TARGET_RESET) {
674 /* Cannot switch context while running so endreset is
675 * called with target->state == TARGET_RESET
676 */
677 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
678 cortex_m->dcb_dhcsr);
679 retval = cortex_m_endreset_event(target);
680 if (retval != ERROR_OK) {
681 target->state = TARGET_UNKNOWN;
682 return retval;
683 }
684 target->state = TARGET_RUNNING;
685 prev_target_state = TARGET_RUNNING;
686 }
687
688 if (cortex_m->dcb_dhcsr & S_HALT) {
689 target->state = TARGET_HALTED;
690
691 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
692 retval = cortex_m_debug_entry(target);
693 if (retval != ERROR_OK)
694 return retval;
695
696 if (arm_semihosting(target, &retval) != 0)
697 return retval;
698
699 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
700 }
701 if (prev_target_state == TARGET_DEBUG_RUNNING) {
702 LOG_DEBUG(" ");
703 retval = cortex_m_debug_entry(target);
704 if (retval != ERROR_OK)
705 return retval;
706
707 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
708 }
709 }
710
711 if (target->state == TARGET_UNKNOWN) {
712 /* check if processor is retiring instructions or sleeping */
713 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
714 target->state = TARGET_RUNNING;
715 retval = ERROR_OK;
716 }
717 }
718
719 /* Check that target is truly halted, since the target could be resumed externally */
720 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
721 /* registers are now invalid */
722 register_cache_invalidate(armv7m->arm.core_cache);
723
724 target->state = TARGET_RUNNING;
725 LOG_WARNING("%s: external resume detected", target_name(target));
726 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
727 retval = ERROR_OK;
728 }
729
730 /* Did we detect a failure condition that we cleared? */
731 if (detected_failure != ERROR_OK)
732 retval = detected_failure;
733 return retval;
734 }
735
736 static int cortex_m_halt(struct target *target)
737 {
738 LOG_DEBUG("target->state: %s",
739 target_state_name(target));
740
741 if (target->state == TARGET_HALTED) {
742 LOG_DEBUG("target was already halted");
743 return ERROR_OK;
744 }
745
746 if (target->state == TARGET_UNKNOWN)
747 LOG_WARNING("target was in unknown state when halt was requested");
748
749 if (target->state == TARGET_RESET) {
750 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
751 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
752 return ERROR_TARGET_FAILURE;
753 } else {
754 /* we came here in a reset_halt or reset_init sequence
755 * debug entry was already prepared in cortex_m3_assert_reset()
756 */
757 target->debug_reason = DBG_REASON_DBGRQ;
758
759 return ERROR_OK;
760 }
761 }
762
763 /* Write to Debug Halting Control and Status Register */
764 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
765
766 /* Do this really early to minimize the window where the MASKINTS erratum
767 * can pile up pending interrupts. */
768 cortex_m_set_maskints_for_halt(target);
769
770 target->debug_reason = DBG_REASON_DBGRQ;
771
772 return ERROR_OK;
773 }
774
775 static int cortex_m_soft_reset_halt(struct target *target)
776 {
777 struct cortex_m_common *cortex_m = target_to_cm(target);
778 struct armv7m_common *armv7m = &cortex_m->armv7m;
779 uint32_t dcb_dhcsr = 0;
780 int retval, timeout = 0;
781
782 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
783 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
784 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
785 * core, not the peripherals */
786 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
787
788 if (!cortex_m->vectreset_supported) {
789 LOG_ERROR("VECTRESET is not supported on this Cortex-M core");
790 return ERROR_FAIL;
791 }
792
793 /* Set C_DEBUGEN */
794 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
795 if (retval != ERROR_OK)
796 return retval;
797
798 /* Enter debug state on reset; restore DEMCR in endreset_event() */
799 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
800 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
801 if (retval != ERROR_OK)
802 return retval;
803
804 /* Request a core-only reset */
805 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
806 AIRCR_VECTKEY | AIRCR_VECTRESET);
807 if (retval != ERROR_OK)
808 return retval;
809 target->state = TARGET_RESET;
810
811 /* registers are now invalid */
812 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
813
814 while (timeout < 100) {
815 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
816 if (retval == ERROR_OK) {
817 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
818 &cortex_m->nvic_dfsr);
819 if (retval != ERROR_OK)
820 return retval;
821 if ((dcb_dhcsr & S_HALT)
822 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
823 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
824 "DFSR 0x%08x",
825 (unsigned) dcb_dhcsr,
826 (unsigned) cortex_m->nvic_dfsr);
827 cortex_m_poll(target);
828 /* FIXME restore user's vector catch config */
829 return ERROR_OK;
830 } else
831 LOG_DEBUG("waiting for system reset-halt, "
832 "DHCSR 0x%08x, %d ms",
833 (unsigned) dcb_dhcsr, timeout);
834 }
835 timeout++;
836 alive_sleep(1);
837 }
838
839 return ERROR_OK;
840 }
841
842 void cortex_m_enable_breakpoints(struct target *target)
843 {
844 struct breakpoint *breakpoint = target->breakpoints;
845
846 /* set any pending breakpoints */
847 while (breakpoint) {
848 if (!breakpoint->set)
849 cortex_m_set_breakpoint(target, breakpoint);
850 breakpoint = breakpoint->next;
851 }
852 }
853
854 static int cortex_m_resume(struct target *target, int current,
855 target_addr_t address, int handle_breakpoints, int debug_execution)
856 {
857 struct armv7m_common *armv7m = target_to_armv7m(target);
858 struct breakpoint *breakpoint = NULL;
859 uint32_t resume_pc;
860 struct reg *r;
861
862 if (target->state != TARGET_HALTED) {
863 LOG_WARNING("target not halted");
864 return ERROR_TARGET_NOT_HALTED;
865 }
866
867 if (!debug_execution) {
868 target_free_all_working_areas(target);
869 cortex_m_enable_breakpoints(target);
870 cortex_m_enable_watchpoints(target);
871 }
872
873 if (debug_execution) {
874 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
875
876 /* Disable interrupts */
877 /* We disable interrupts in the PRIMASK register instead of
878 * masking with C_MASKINTS. This is probably the same issue
879 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
880 * in parallel with disabled interrupts can cause local faults
881 * to not be taken.
882 *
883 * This breaks non-debug (application) execution if not
884 * called from armv7m_start_algorithm() which saves registers.
885 */
886 buf_set_u32(r->value, 0, 1, 1);
887 r->dirty = true;
888 r->valid = true;
889
890 /* Make sure we are in Thumb mode, set xPSR.T bit */
891 /* armv7m_start_algorithm() initializes entire xPSR register.
892 * This duplicity handles the case when cortex_m_resume()
893 * is used with the debug_execution flag directly,
894 * not called through armv7m_start_algorithm().
895 */
896 r = armv7m->arm.cpsr;
897 buf_set_u32(r->value, 24, 1, 1);
898 r->dirty = true;
899 r->valid = true;
900 }
901
902 /* current = 1: continue on current pc, otherwise continue at <address> */
903 r = armv7m->arm.pc;
904 if (!current) {
905 buf_set_u32(r->value, 0, 32, address);
906 r->dirty = true;
907 r->valid = true;
908 }
909
910 /* if we halted last time due to a bkpt instruction
911 * then we have to manually step over it, otherwise
912 * the core will break again */
913
914 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
915 && !debug_execution)
916 armv7m_maybe_skip_bkpt_inst(target, NULL);
917
918 resume_pc = buf_get_u32(r->value, 0, 32);
919
920 armv7m_restore_context(target);
921
922 /* the front-end may request us not to handle breakpoints */
923 if (handle_breakpoints) {
924 /* Single step past breakpoint at current address */
925 breakpoint = breakpoint_find(target, resume_pc);
926 if (breakpoint) {
927 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
928 breakpoint->address,
929 breakpoint->unique_id);
930 cortex_m_unset_breakpoint(target, breakpoint);
931 cortex_m_single_step_core(target);
932 cortex_m_set_breakpoint(target, breakpoint);
933 }
934 }
935
936 /* Restart core */
937 cortex_m_set_maskints_for_run(target);
938 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
939
940 target->debug_reason = DBG_REASON_NOTHALTED;
941
942 /* registers are now invalid */
943 register_cache_invalidate(armv7m->arm.core_cache);
944
945 if (!debug_execution) {
946 target->state = TARGET_RUNNING;
947 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
948 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
949 } else {
950 target->state = TARGET_DEBUG_RUNNING;
951 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
952 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
953 }
954
955 return ERROR_OK;
956 }
957
958 /* int irqstepcount = 0; */
959 static int cortex_m_step(struct target *target, int current,
960 target_addr_t address, int handle_breakpoints)
961 {
962 struct cortex_m_common *cortex_m = target_to_cm(target);
963 struct armv7m_common *armv7m = &cortex_m->armv7m;
964 struct breakpoint *breakpoint = NULL;
965 struct reg *pc = armv7m->arm.pc;
966 bool bkpt_inst_found = false;
967 int retval;
968 bool isr_timed_out = false;
969
970 if (target->state != TARGET_HALTED) {
971 LOG_WARNING("target not halted");
972 return ERROR_TARGET_NOT_HALTED;
973 }
974
975 /* current = 1: continue on current pc, otherwise continue at <address> */
976 if (!current) {
977 buf_set_u32(pc->value, 0, 32, address);
978 pc->dirty = true;
979 pc->valid = true;
980 }
981
982 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
983
984 /* the front-end may request us not to handle breakpoints */
985 if (handle_breakpoints) {
986 breakpoint = breakpoint_find(target, pc_value);
987 if (breakpoint)
988 cortex_m_unset_breakpoint(target, breakpoint);
989 }
990
991 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
992
993 target->debug_reason = DBG_REASON_SINGLESTEP;
994
995 armv7m_restore_context(target);
996
997 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
998
999 /* if no bkpt instruction is found at pc then we can perform
1000 * a normal step, otherwise we have to manually step over the bkpt
1001 * instruction - as such simulate a step */
1002 if (bkpt_inst_found == false) {
1003 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
1004 /* Automatic ISR masking mode off: Just step over the next
1005 * instruction, with interrupts on or off as appropriate. */
1006 cortex_m_set_maskints_for_step(target);
1007 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1008 } else {
1009 /* Process interrupts during stepping in a way they don't interfere
1010 * debugging.
1011 *
1012 * Principle:
1013 *
1014 * Set a temporary break point at the current pc and let the core run
1015 * with interrupts enabled. Pending interrupts get served and we run
1016 * into the breakpoint again afterwards. Then we step over the next
1017 * instruction with interrupts disabled.
1018 *
1019 * If the pending interrupts don't complete within time, we leave the
1020 * core running. This may happen if the interrupts trigger faster
1021 * than the core can process them or the handler doesn't return.
1022 *
1023 * If no more breakpoints are available we simply do a step with
1024 * interrupts enabled.
1025 *
1026 */
1027
1028 /* 2012-09-29 ph
1029 *
1030 * If a break point is already set on the lower half word then a break point on
1031 * the upper half word will not break again when the core is restarted. So we
1032 * just step over the instruction with interrupts disabled.
1033 *
1034 * The documentation has no information about this, it was found by observation
1035 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
1036 * suffer from this problem.
1037 *
1038 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
1039 * address has it always cleared. The former is done to indicate thumb mode
1040 * to gdb.
1041 *
1042 */
1043 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
1044 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
1045 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
1046 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1047 /* Re-enable interrupts if appropriate */
1048 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1049 cortex_m_set_maskints_for_halt(target);
1050 } else {
1051
1052 /* Set a temporary break point */
1053 if (breakpoint) {
1054 retval = cortex_m_set_breakpoint(target, breakpoint);
1055 } else {
1056 enum breakpoint_type type = BKPT_HARD;
1057 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
1058 /* FPB rev.1 cannot handle such addr, try BKPT instr */
1059 type = BKPT_SOFT;
1060 }
1061 retval = breakpoint_add(target, pc_value, 2, type);
1062 }
1063
1064 bool tmp_bp_set = (retval == ERROR_OK);
1065
1066 /* No more breakpoints left, just do a step */
1067 if (!tmp_bp_set) {
1068 cortex_m_set_maskints_for_step(target);
1069 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1070 /* Re-enable interrupts if appropriate */
1071 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1072 cortex_m_set_maskints_for_halt(target);
1073 } else {
1074 /* Start the core */
1075 LOG_DEBUG("Starting core to serve pending interrupts");
1076 int64_t t_start = timeval_ms();
1077 cortex_m_set_maskints_for_run(target);
1078 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1079
1080 /* Wait for pending handlers to complete or timeout */
1081 do {
1082 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1083 DCB_DHCSR,
1084 &cortex_m->dcb_dhcsr);
1085 if (retval != ERROR_OK) {
1086 target->state = TARGET_UNKNOWN;
1087 return retval;
1088 }
1089 isr_timed_out = ((timeval_ms() - t_start) > 500);
1090 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1091
1092 /* only remove breakpoint if we created it */
1093 if (breakpoint)
1094 cortex_m_unset_breakpoint(target, breakpoint);
1095 else {
1096 /* Remove the temporary breakpoint */
1097 breakpoint_remove(target, pc_value);
1098 }
1099
1100 if (isr_timed_out) {
1101 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1102 "leaving target running");
1103 } else {
1104 /* Step over next instruction with interrupts disabled */
1105 cortex_m_set_maskints_for_step(target);
1106 cortex_m_write_debug_halt_mask(target,
1107 C_HALT | C_MASKINTS,
1108 0);
1109 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1110 /* Re-enable interrupts if appropriate */
1111 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1112 cortex_m_set_maskints_for_halt(target);
1113 }
1114 }
1115 }
1116 }
1117 }
1118
1119 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1120 if (retval != ERROR_OK)
1121 return retval;
1122
1123 /* registers are now invalid */
1124 register_cache_invalidate(armv7m->arm.core_cache);
1125
1126 if (breakpoint)
1127 cortex_m_set_breakpoint(target, breakpoint);
1128
1129 if (isr_timed_out) {
1130 /* Leave the core running. The user has to stop execution manually. */
1131 target->debug_reason = DBG_REASON_NOTHALTED;
1132 target->state = TARGET_RUNNING;
1133 return ERROR_OK;
1134 }
1135
1136 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1137 " nvic_icsr = 0x%" PRIx32,
1138 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1139
1140 retval = cortex_m_debug_entry(target);
1141 if (retval != ERROR_OK)
1142 return retval;
1143 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1144
1145 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1146 " nvic_icsr = 0x%" PRIx32,
1147 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1148
1149 return ERROR_OK;
1150 }
1151
1152 static int cortex_m_assert_reset(struct target *target)
1153 {
1154 struct cortex_m_common *cortex_m = target_to_cm(target);
1155 struct armv7m_common *armv7m = &cortex_m->armv7m;
1156 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1157
1158 LOG_DEBUG("target->state: %s",
1159 target_state_name(target));
1160
1161 enum reset_types jtag_reset_config = jtag_get_reset_config();
1162
1163 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1164 /* allow scripts to override the reset event */
1165
1166 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1167 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1168 target->state = TARGET_RESET;
1169
1170 return ERROR_OK;
1171 }
1172
1173 /* some cores support connecting while srst is asserted
1174 * use that mode is it has been configured */
1175
1176 bool srst_asserted = false;
1177
1178 if (!target_was_examined(target)) {
1179 if (jtag_reset_config & RESET_HAS_SRST) {
1180 adapter_assert_reset();
1181 if (target->reset_halt)
1182 LOG_ERROR("Target not examined, will not halt after reset!");
1183 return ERROR_OK;
1184 } else {
1185 LOG_ERROR("Target not examined, reset NOT asserted!");
1186 return ERROR_FAIL;
1187 }
1188 }
1189
1190 if ((jtag_reset_config & RESET_HAS_SRST) &&
1191 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1192 adapter_assert_reset();
1193 srst_asserted = true;
1194 }
1195
1196 /* Enable debug requests */
1197 int retval;
1198 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1199 /* Store important errors instead of failing and proceed to reset assert */
1200
1201 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1202 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1203
1204 /* If the processor is sleeping in a WFI or WFE instruction, the
1205 * C_HALT bit must be asserted to regain control */
1206 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1207 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1208
1209 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1210 /* Ignore less important errors */
1211
1212 if (!target->reset_halt) {
1213 /* Set/Clear C_MASKINTS in a separate operation */
1214 cortex_m_set_maskints_for_run(target);
1215
1216 /* clear any debug flags before resuming */
1217 cortex_m_clear_halt(target);
1218
1219 /* clear C_HALT in dhcsr reg */
1220 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1221 } else {
1222 /* Halt in debug on reset; endreset_event() restores DEMCR.
1223 *
1224 * REVISIT catching BUSERR presumably helps to defend against
1225 * bad vector table entries. Should this include MMERR or
1226 * other flags too?
1227 */
1228 int retval2;
1229 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1230 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1231 if (retval != ERROR_OK || retval2 != ERROR_OK)
1232 LOG_INFO("AP write error, reset will not halt");
1233 }
1234
1235 if (jtag_reset_config & RESET_HAS_SRST) {
1236 /* default to asserting srst */
1237 if (!srst_asserted)
1238 adapter_assert_reset();
1239
1240 /* srst is asserted, ignore AP access errors */
1241 retval = ERROR_OK;
1242 } else {
1243 /* Use a standard Cortex-M3 software reset mechanism.
1244 * We default to using VECTRESET as it is supported on all current cores
1245 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1246 * This has the disadvantage of not resetting the peripherals, so a
1247 * reset-init event handler is needed to perform any peripheral resets.
1248 */
1249 if (!cortex_m->vectreset_supported
1250 && reset_config == CORTEX_M_RESET_VECTRESET) {
1251 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1252 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1253 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1254 }
1255
1256 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1257 ? "SYSRESETREQ" : "VECTRESET");
1258
1259 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1260 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1261 "handler to reset any peripherals or configure hardware srst support.");
1262 }
1263
1264 int retval3;
1265 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1266 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1267 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1268 if (retval3 != ERROR_OK)
1269 LOG_DEBUG("Ignoring AP write error right after reset");
1270
1271 retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1272 if (retval3 != ERROR_OK) {
1273 LOG_ERROR("DP initialisation failed");
1274 /* The error return value must not be propagated in this case.
1275 * SYSRESETREQ or VECTRESET have been possibly triggered
1276 * so reset processing should continue */
1277 } else {
1278 /* I do not know why this is necessary, but it
1279 * fixes strange effects (step/resume cause NMI
1280 * after reset) on LM3S6918 -- Michael Schwingen
1281 */
1282 uint32_t tmp;
1283 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1284 }
1285 }
1286
1287 target->state = TARGET_RESET;
1288 jtag_sleep(50000);
1289
1290 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1291
1292 /* now return stored error code if any */
1293 if (retval != ERROR_OK)
1294 return retval;
1295
1296 if (target->reset_halt) {
1297 retval = target_halt(target);
1298 if (retval != ERROR_OK)
1299 return retval;
1300 }
1301
1302 return ERROR_OK;
1303 }
1304
1305 static int cortex_m_deassert_reset(struct target *target)
1306 {
1307 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1308
1309 LOG_DEBUG("target->state: %s",
1310 target_state_name(target));
1311
1312 /* deassert reset lines */
1313 adapter_deassert_reset();
1314
1315 enum reset_types jtag_reset_config = jtag_get_reset_config();
1316
1317 if ((jtag_reset_config & RESET_HAS_SRST) &&
1318 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1319 target_was_examined(target)) {
1320
1321 int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1322 if (retval != ERROR_OK) {
1323 LOG_ERROR("DP initialisation failed");
1324 return retval;
1325 }
1326 }
1327
1328 return ERROR_OK;
1329 }
1330
1331 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1332 {
1333 int retval;
1334 unsigned int fp_num = 0;
1335 struct cortex_m_common *cortex_m = target_to_cm(target);
1336 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1337
1338 if (breakpoint->set) {
1339 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1340 return ERROR_OK;
1341 }
1342
1343 if (breakpoint->type == BKPT_HARD) {
1344 uint32_t fpcr_value;
1345 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1346 fp_num++;
1347 if (fp_num >= cortex_m->fp_num_code) {
1348 LOG_ERROR("Can not find free FPB Comparator!");
1349 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1350 }
1351 breakpoint->set = fp_num + 1;
1352 fpcr_value = breakpoint->address | 1;
1353 if (cortex_m->fp_rev == 0) {
1354 if (breakpoint->address > 0x1FFFFFFF) {
1355 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1356 return ERROR_FAIL;
1357 }
1358 uint32_t hilo;
1359 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1360 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1361 } else if (cortex_m->fp_rev > 1) {
1362 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1363 return ERROR_FAIL;
1364 }
1365 comparator_list[fp_num].used = true;
1366 comparator_list[fp_num].fpcr_value = fpcr_value;
1367 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1368 comparator_list[fp_num].fpcr_value);
1369 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1370 fp_num,
1371 comparator_list[fp_num].fpcr_value);
1372 if (!cortex_m->fpb_enabled) {
1373 LOG_DEBUG("FPB wasn't enabled, do it now");
1374 retval = cortex_m_enable_fpb(target);
1375 if (retval != ERROR_OK) {
1376 LOG_ERROR("Failed to enable the FPB");
1377 return retval;
1378 }
1379
1380 cortex_m->fpb_enabled = true;
1381 }
1382 } else if (breakpoint->type == BKPT_SOFT) {
1383 uint8_t code[4];
1384
1385 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1386 * semihosting; don't use that. Otherwise the BKPT
1387 * parameter is arbitrary.
1388 */
1389 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1390 retval = target_read_memory(target,
1391 breakpoint->address & 0xFFFFFFFE,
1392 breakpoint->length, 1,
1393 breakpoint->orig_instr);
1394 if (retval != ERROR_OK)
1395 return retval;
1396 retval = target_write_memory(target,
1397 breakpoint->address & 0xFFFFFFFE,
1398 breakpoint->length, 1,
1399 code);
1400 if (retval != ERROR_OK)
1401 return retval;
1402 breakpoint->set = true;
1403 }
1404
1405 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1406 breakpoint->unique_id,
1407 (int)(breakpoint->type),
1408 breakpoint->address,
1409 breakpoint->length,
1410 breakpoint->set);
1411
1412 return ERROR_OK;
1413 }
1414
1415 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1416 {
1417 int retval;
1418 struct cortex_m_common *cortex_m = target_to_cm(target);
1419 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1420
1421 if (breakpoint->set <= 0) {
1422 LOG_WARNING("breakpoint not set");
1423 return ERROR_OK;
1424 }
1425
1426 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1427 breakpoint->unique_id,
1428 (int)(breakpoint->type),
1429 breakpoint->address,
1430 breakpoint->length,
1431 breakpoint->set);
1432
1433 if (breakpoint->type == BKPT_HARD) {
1434 unsigned int fp_num = breakpoint->set - 1;
1435 if (fp_num >= cortex_m->fp_num_code) {
1436 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1437 return ERROR_OK;
1438 }
1439 comparator_list[fp_num].used = false;
1440 comparator_list[fp_num].fpcr_value = 0;
1441 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1442 comparator_list[fp_num].fpcr_value);
1443 } else {
1444 /* restore original instruction (kept in target endianness) */
1445 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1446 breakpoint->length, 1,
1447 breakpoint->orig_instr);
1448 if (retval != ERROR_OK)
1449 return retval;
1450 }
1451 breakpoint->set = false;
1452
1453 return ERROR_OK;
1454 }
1455
1456 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1457 {
1458 if (breakpoint->length == 3) {
1459 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1460 breakpoint->length = 2;
1461 }
1462
1463 if ((breakpoint->length != 2)) {
1464 LOG_INFO("only breakpoints of two bytes length supported");
1465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1466 }
1467
1468 return cortex_m_set_breakpoint(target, breakpoint);
1469 }
1470
1471 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1472 {
1473 if (!breakpoint->set)
1474 return ERROR_OK;
1475
1476 return cortex_m_unset_breakpoint(target, breakpoint);
1477 }
1478
1479 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1480 {
1481 unsigned int dwt_num = 0;
1482 struct cortex_m_common *cortex_m = target_to_cm(target);
1483
1484 /* REVISIT Don't fully trust these "not used" records ... users
1485 * may set up breakpoints by hand, e.g. dual-address data value
1486 * watchpoint using comparator #1; comparator #0 matching cycle
1487 * count; send data trace info through ITM and TPIU; etc
1488 */
1489 struct cortex_m_dwt_comparator *comparator;
1490
1491 for (comparator = cortex_m->dwt_comparator_list;
1492 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1493 comparator++, dwt_num++)
1494 continue;
1495 if (dwt_num >= cortex_m->dwt_num_comp) {
1496 LOG_ERROR("Can not find free DWT Comparator");
1497 return ERROR_FAIL;
1498 }
1499 comparator->used = true;
1500 watchpoint->set = dwt_num + 1;
1501
1502 comparator->comp = watchpoint->address;
1503 target_write_u32(target, comparator->dwt_comparator_address + 0,
1504 comparator->comp);
1505
1506 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1507 uint32_t mask = 0, temp;
1508
1509 /* watchpoint params were validated earlier */
1510 temp = watchpoint->length;
1511 while (temp) {
1512 temp >>= 1;
1513 mask++;
1514 }
1515 mask--;
1516
1517 comparator->mask = mask;
1518 target_write_u32(target, comparator->dwt_comparator_address + 4,
1519 comparator->mask);
1520
1521 switch (watchpoint->rw) {
1522 case WPT_READ:
1523 comparator->function = 5;
1524 break;
1525 case WPT_WRITE:
1526 comparator->function = 6;
1527 break;
1528 case WPT_ACCESS:
1529 comparator->function = 7;
1530 break;
1531 }
1532 } else {
1533 uint32_t data_size = watchpoint->length >> 1;
1534 comparator->mask = (watchpoint->length >> 1) | 1;
1535
1536 switch (watchpoint->rw) {
1537 case WPT_ACCESS:
1538 comparator->function = 4;
1539 break;
1540 case WPT_WRITE:
1541 comparator->function = 5;
1542 break;
1543 case WPT_READ:
1544 comparator->function = 6;
1545 break;
1546 }
1547 comparator->function = comparator->function | (1 << 4) |
1548 (data_size << 10);
1549 }
1550
1551 target_write_u32(target, comparator->dwt_comparator_address + 8,
1552 comparator->function);
1553
1554 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1555 watchpoint->unique_id, dwt_num,
1556 (unsigned) comparator->comp,
1557 (unsigned) comparator->mask,
1558 (unsigned) comparator->function);
1559 return ERROR_OK;
1560 }
1561
1562 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1563 {
1564 struct cortex_m_common *cortex_m = target_to_cm(target);
1565 struct cortex_m_dwt_comparator *comparator;
1566
1567 if (watchpoint->set <= 0) {
1568 LOG_WARNING("watchpoint (wpid: %d) not set",
1569 watchpoint->unique_id);
1570 return ERROR_OK;
1571 }
1572
1573 unsigned int dwt_num = watchpoint->set - 1;
1574
1575 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1576 watchpoint->unique_id, dwt_num,
1577 (unsigned) watchpoint->address);
1578
1579 if (dwt_num >= cortex_m->dwt_num_comp) {
1580 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1581 return ERROR_OK;
1582 }
1583
1584 comparator = cortex_m->dwt_comparator_list + dwt_num;
1585 comparator->used = false;
1586 comparator->function = 0;
1587 target_write_u32(target, comparator->dwt_comparator_address + 8,
1588 comparator->function);
1589
1590 watchpoint->set = false;
1591
1592 return ERROR_OK;
1593 }
1594
1595 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1596 {
1597 struct cortex_m_common *cortex_m = target_to_cm(target);
1598
1599 if (cortex_m->dwt_comp_available < 1) {
1600 LOG_DEBUG("no comparators?");
1601 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1602 }
1603
1604 /* hardware doesn't support data value masking */
1605 if (watchpoint->mask != ~(uint32_t)0) {
1606 LOG_DEBUG("watchpoint value masks not supported");
1607 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1608 }
1609
1610 /* hardware allows address masks of up to 32K */
1611 unsigned mask;
1612
1613 for (mask = 0; mask < 16; mask++) {
1614 if ((1u << mask) == watchpoint->length)
1615 break;
1616 }
1617 if (mask == 16) {
1618 LOG_DEBUG("unsupported watchpoint length");
1619 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1620 }
1621 if (watchpoint->address & ((1 << mask) - 1)) {
1622 LOG_DEBUG("watchpoint address is unaligned");
1623 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1624 }
1625
1626 /* Caller doesn't seem to be able to describe watching for data
1627 * values of zero; that flags "no value".
1628 *
1629 * REVISIT This DWT may well be able to watch for specific data
1630 * values. Requires comparator #1 to set DATAVMATCH and match
1631 * the data, and another comparator (DATAVADDR0) matching addr.
1632 */
1633 if (watchpoint->value) {
1634 LOG_DEBUG("data value watchpoint not YET supported");
1635 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1636 }
1637
1638 cortex_m->dwt_comp_available--;
1639 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1640
1641 return ERROR_OK;
1642 }
1643
1644 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1645 {
1646 struct cortex_m_common *cortex_m = target_to_cm(target);
1647
1648 /* REVISIT why check? DWT can be updated with core running ... */
1649 if (target->state != TARGET_HALTED) {
1650 LOG_WARNING("target not halted");
1651 return ERROR_TARGET_NOT_HALTED;
1652 }
1653
1654 if (watchpoint->set)
1655 cortex_m_unset_watchpoint(target, watchpoint);
1656
1657 cortex_m->dwt_comp_available++;
1658 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1659
1660 return ERROR_OK;
1661 }
1662
1663 int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1664 {
1665 if (target->debug_reason != DBG_REASON_WATCHPOINT)
1666 return ERROR_FAIL;
1667
1668 struct cortex_m_common *cortex_m = target_to_cm(target);
1669
1670 for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
1671 if (!wp->set)
1672 continue;
1673
1674 unsigned int dwt_num = wp->set - 1;
1675 struct cortex_m_dwt_comparator *comparator = cortex_m->dwt_comparator_list + dwt_num;
1676
1677 uint32_t dwt_function;
1678 int retval = target_read_u32(target, comparator->dwt_comparator_address + 8, &dwt_function);
1679 if (retval != ERROR_OK)
1680 return ERROR_FAIL;
1681
1682 /* check the MATCHED bit */
1683 if (dwt_function & BIT(24)) {
1684 *hit_watchpoint = wp;
1685 return ERROR_OK;
1686 }
1687 }
1688
1689 return ERROR_FAIL;
1690 }
1691
1692 void cortex_m_enable_watchpoints(struct target *target)
1693 {
1694 struct watchpoint *watchpoint = target->watchpoints;
1695
1696 /* set any pending watchpoints */
1697 while (watchpoint) {
1698 if (!watchpoint->set)
1699 cortex_m_set_watchpoint(target, watchpoint);
1700 watchpoint = watchpoint->next;
1701 }
1702 }
1703
1704 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1705 uint32_t size, uint32_t count, uint8_t *buffer)
1706 {
1707 struct armv7m_common *armv7m = target_to_armv7m(target);
1708
1709 if (armv7m->arm.arch == ARM_ARCH_V6M) {
1710 /* armv6m does not handle unaligned memory access */
1711 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1712 return ERROR_TARGET_UNALIGNED_ACCESS;
1713 }
1714
1715 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1716 }
1717
1718 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1719 uint32_t size, uint32_t count, const uint8_t *buffer)
1720 {
1721 struct armv7m_common *armv7m = target_to_armv7m(target);
1722
1723 if (armv7m->arm.arch == ARM_ARCH_V6M) {
1724 /* armv6m does not handle unaligned memory access */
1725 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1726 return ERROR_TARGET_UNALIGNED_ACCESS;
1727 }
1728
1729 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1730 }
1731
1732 static int cortex_m_init_target(struct command_context *cmd_ctx,
1733 struct target *target)
1734 {
1735 armv7m_build_reg_cache(target);
1736 arm_semihosting_init(target);
1737 return ERROR_OK;
1738 }
1739
1740 void cortex_m_deinit_target(struct target *target)
1741 {
1742 struct cortex_m_common *cortex_m = target_to_cm(target);
1743
1744 free(cortex_m->fp_comparator_list);
1745
1746 cortex_m_dwt_free(target);
1747 armv7m_free_reg_cache(target);
1748
1749 free(target->private_config);
1750 free(cortex_m);
1751 }
1752
1753 int cortex_m_profiling(struct target *target, uint32_t *samples,
1754 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1755 {
1756 struct timeval timeout, now;
1757 struct armv7m_common *armv7m = target_to_armv7m(target);
1758 uint32_t reg_value;
1759 int retval;
1760
1761 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1762 if (retval != ERROR_OK) {
1763 LOG_ERROR("Error while reading PCSR");
1764 return retval;
1765 }
1766 if (reg_value == 0) {
1767 LOG_INFO("PCSR sampling not supported on this processor.");
1768 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1769 }
1770
1771 gettimeofday(&timeout, NULL);
1772 timeval_add_time(&timeout, seconds, 0);
1773
1774 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1775
1776 /* Make sure the target is running */
1777 target_poll(target);
1778 if (target->state == TARGET_HALTED)
1779 retval = target_resume(target, 1, 0, 0, 0);
1780
1781 if (retval != ERROR_OK) {
1782 LOG_ERROR("Error while resuming target");
1783 return retval;
1784 }
1785
1786 uint32_t sample_count = 0;
1787
1788 for (;;) {
1789 if (armv7m && armv7m->debug_ap) {
1790 uint32_t read_count = max_num_samples - sample_count;
1791 if (read_count > 1024)
1792 read_count = 1024;
1793
1794 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1795 (void *)&samples[sample_count],
1796 4, read_count, DWT_PCSR);
1797 sample_count += read_count;
1798 } else {
1799 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1800 }
1801
1802 if (retval != ERROR_OK) {
1803 LOG_ERROR("Error while reading PCSR");
1804 return retval;
1805 }
1806
1807
1808 gettimeofday(&now, NULL);
1809 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1810 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1811 break;
1812 }
1813 }
1814
1815 *num_samples = sample_count;
1816 return retval;
1817 }
1818
1819
1820 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1821 * on r/w if the core is not running, and clear on resume or reset ... or
1822 * at least, in a post_restore_context() method.
1823 */
1824
1825 struct dwt_reg_state {
1826 struct target *target;
1827 uint32_t addr;
1828 uint8_t value[4]; /* scratch/cache */
1829 };
1830
1831 static int cortex_m_dwt_get_reg(struct reg *reg)
1832 {
1833 struct dwt_reg_state *state = reg->arch_info;
1834
1835 uint32_t tmp;
1836 int retval = target_read_u32(state->target, state->addr, &tmp);
1837 if (retval != ERROR_OK)
1838 return retval;
1839
1840 buf_set_u32(state->value, 0, 32, tmp);
1841 return ERROR_OK;
1842 }
1843
1844 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1845 {
1846 struct dwt_reg_state *state = reg->arch_info;
1847
1848 return target_write_u32(state->target, state->addr,
1849 buf_get_u32(buf, 0, reg->size));
1850 }
1851
1852 struct dwt_reg {
1853 uint32_t addr;
1854 const char *name;
1855 unsigned size;
1856 };
1857
1858 static const struct dwt_reg dwt_base_regs[] = {
1859 { DWT_CTRL, "dwt_ctrl", 32, },
1860 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1861 * increments while the core is asleep.
1862 */
1863 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1864 /* plus some 8 bit counters, useful for profiling with TPIU */
1865 };
1866
1867 static const struct dwt_reg dwt_comp[] = {
1868 #define DWT_COMPARATOR(i) \
1869 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1870 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1871 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1872 DWT_COMPARATOR(0),
1873 DWT_COMPARATOR(1),
1874 DWT_COMPARATOR(2),
1875 DWT_COMPARATOR(3),
1876 DWT_COMPARATOR(4),
1877 DWT_COMPARATOR(5),
1878 DWT_COMPARATOR(6),
1879 DWT_COMPARATOR(7),
1880 DWT_COMPARATOR(8),
1881 DWT_COMPARATOR(9),
1882 DWT_COMPARATOR(10),
1883 DWT_COMPARATOR(11),
1884 DWT_COMPARATOR(12),
1885 DWT_COMPARATOR(13),
1886 DWT_COMPARATOR(14),
1887 DWT_COMPARATOR(15),
1888 #undef DWT_COMPARATOR
1889 };
1890
1891 static const struct reg_arch_type dwt_reg_type = {
1892 .get = cortex_m_dwt_get_reg,
1893 .set = cortex_m_dwt_set_reg,
1894 };
1895
1896 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1897 {
1898 struct dwt_reg_state *state;
1899
1900 state = calloc(1, sizeof(*state));
1901 if (!state)
1902 return;
1903 state->addr = d->addr;
1904 state->target = t;
1905
1906 r->name = d->name;
1907 r->size = d->size;
1908 r->value = state->value;
1909 r->arch_info = state;
1910 r->type = &dwt_reg_type;
1911 }
1912
1913 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1914 {
1915 uint32_t dwtcr;
1916 struct reg_cache *cache;
1917 struct cortex_m_dwt_comparator *comparator;
1918 int reg;
1919
1920 target_read_u32(target, DWT_CTRL, &dwtcr);
1921 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1922 if (!dwtcr) {
1923 LOG_DEBUG("no DWT");
1924 return;
1925 }
1926
1927 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
1928 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
1929
1930 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1931 cm->dwt_comp_available = cm->dwt_num_comp;
1932 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1933 sizeof(struct cortex_m_dwt_comparator));
1934 if (!cm->dwt_comparator_list) {
1935 fail0:
1936 cm->dwt_num_comp = 0;
1937 LOG_ERROR("out of mem");
1938 return;
1939 }
1940
1941 cache = calloc(1, sizeof(*cache));
1942 if (!cache) {
1943 fail1:
1944 free(cm->dwt_comparator_list);
1945 goto fail0;
1946 }
1947 cache->name = "Cortex-M DWT registers";
1948 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1949 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
1950 if (!cache->reg_list) {
1951 free(cache);
1952 goto fail1;
1953 }
1954
1955 for (reg = 0; reg < 2; reg++)
1956 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1957 dwt_base_regs + reg);
1958
1959 comparator = cm->dwt_comparator_list;
1960 for (unsigned int i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1961 int j;
1962
1963 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1964 for (j = 0; j < 3; j++, reg++)
1965 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1966 dwt_comp + 3 * i + j);
1967
1968 /* make sure we clear any watchpoints enabled on the target */
1969 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1970 }
1971
1972 *register_get_last_cache_p(&target->reg_cache) = cache;
1973 cm->dwt_cache = cache;
1974
1975 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1976 dwtcr, cm->dwt_num_comp,
1977 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1978
1979 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1980 * implement single-address data value watchpoints ... so we
1981 * won't need to check it later, when asked to set one up.
1982 */
1983 }
1984
1985 static void cortex_m_dwt_free(struct target *target)
1986 {
1987 struct cortex_m_common *cm = target_to_cm(target);
1988 struct reg_cache *cache = cm->dwt_cache;
1989
1990 free(cm->dwt_comparator_list);
1991 cm->dwt_comparator_list = NULL;
1992 cm->dwt_num_comp = 0;
1993
1994 if (cache) {
1995 register_unlink_cache(&target->reg_cache, cache);
1996
1997 if (cache->reg_list) {
1998 for (size_t i = 0; i < cache->num_regs; i++)
1999 free(cache->reg_list[i].arch_info);
2000 free(cache->reg_list);
2001 }
2002 free(cache);
2003 }
2004 cm->dwt_cache = NULL;
2005 }
2006
2007 #define MVFR0 0xe000ef40
2008 #define MVFR1 0xe000ef44
2009
2010 #define MVFR0_DEFAULT_M4 0x10110021
2011 #define MVFR1_DEFAULT_M4 0x11000011
2012
2013 #define MVFR0_DEFAULT_M7_SP 0x10110021
2014 #define MVFR0_DEFAULT_M7_DP 0x10110221
2015 #define MVFR1_DEFAULT_M7_SP 0x11000011
2016 #define MVFR1_DEFAULT_M7_DP 0x12000011
2017
2018 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2019 struct adiv5_ap **debug_ap)
2020 {
2021 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2022 return ERROR_OK;
2023
2024 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2025 }
2026
2027 int cortex_m_examine(struct target *target)
2028 {
2029 int retval;
2030 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2031 struct cortex_m_common *cortex_m = target_to_cm(target);
2032 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2033 struct armv7m_common *armv7m = target_to_armv7m(target);
2034
2035 /* hla_target shares the examine handler but does not support
2036 * all its calls */
2037 if (!armv7m->is_hla_target) {
2038 if (cortex_m->apsel == DP_APSEL_INVALID) {
2039 /* Search for the MEM-AP */
2040 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2041 if (retval != ERROR_OK) {
2042 LOG_ERROR("Could not find MEM-AP to control the core");
2043 return retval;
2044 }
2045 } else {
2046 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2047 }
2048
2049 /* Leave (only) generic DAP stuff for debugport_init(); */
2050 armv7m->debug_ap->memaccess_tck = 8;
2051
2052 retval = mem_ap_init(armv7m->debug_ap);
2053 if (retval != ERROR_OK)
2054 return retval;
2055 }
2056
2057 if (!target_was_examined(target)) {
2058 target_set_examined(target);
2059
2060 /* Read from Device Identification Registers */
2061 retval = target_read_u32(target, CPUID, &cpuid);
2062 if (retval != ERROR_OK)
2063 return retval;
2064
2065 /* Get ARCH and CPU types */
2066 const enum cortex_m_partno core_partno = (cpuid & ARM_CPUID_PARTNO_MASK) >> ARM_CPUID_PARTNO_POS;
2067
2068 for (unsigned int n = 0; n < ARRAY_SIZE(cortex_m_parts); n++) {
2069 if (core_partno == cortex_m_parts[n].partno) {
2070 cortex_m->core_info = &cortex_m_parts[n];
2071 break;
2072 }
2073 }
2074
2075 if (!cortex_m->core_info) {
2076 LOG_ERROR("Cortex-M PARTNO 0x%x is unrecognized", core_partno);
2077 return ERROR_FAIL;
2078 }
2079
2080 armv7m->arm.arch = cortex_m->core_info->arch;
2081
2082 LOG_INFO("%s: %s r%" PRId8 "p%" PRId8 " processor detected",
2083 target_name(target),
2084 cortex_m->core_info->name,
2085 (uint8_t)((cpuid >> 20) & 0xf),
2086 (uint8_t)((cpuid >> 0) & 0xf));
2087
2088 cortex_m->maskints_erratum = false;
2089 if (core_partno == CORTEX_M7_PARTNO) {
2090 uint8_t rev, patch;
2091 rev = (cpuid >> 20) & 0xf;
2092 patch = (cpuid >> 0) & 0xf;
2093 if ((rev == 0) && (patch < 2)) {
2094 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2095 cortex_m->maskints_erratum = true;
2096 }
2097 }
2098 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2099
2100 if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
2101 target_read_u32(target, MVFR0, &mvfr0);
2102 target_read_u32(target, MVFR1, &mvfr1);
2103
2104 /* test for floating point feature on Cortex-M4 */
2105 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2106 LOG_DEBUG("%s floating point feature FPv4_SP found", cortex_m->core_info->name);
2107 armv7m->fp_feature = FPV4_SP;
2108 }
2109 } else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
2110 target_read_u32(target, MVFR0, &mvfr0);
2111 target_read_u32(target, MVFR1, &mvfr1);
2112
2113 /* test for floating point features on Cortex-M7 */
2114 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2115 LOG_DEBUG("%s floating point feature FPv5_SP found", cortex_m->core_info->name);
2116 armv7m->fp_feature = FPV5_SP;
2117 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2118 LOG_DEBUG("%s floating point feature FPv5_DP found", cortex_m->core_info->name);
2119 armv7m->fp_feature = FPV5_DP;
2120 }
2121 }
2122
2123 /* VECTRESET is supported only on ARMv7-M cores */
2124 cortex_m->vectreset_supported = armv7m->arm.arch == ARM_ARCH_V7M;
2125
2126 /* Check for FPU, otherwise mark FPU register as non-existent */
2127 if (armv7m->fp_feature == FP_NONE)
2128 for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
2129 armv7m->arm.core_cache->reg_list[idx].exist = false;
2130
2131 if (armv7m->arm.arch != ARM_ARCH_V8M)
2132 for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
2133 armv7m->arm.core_cache->reg_list[idx].exist = false;
2134
2135 if (!armv7m->is_hla_target) {
2136 if (cortex_m->core_info->flags & CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K)
2137 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2138 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2139 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2140 }
2141
2142 /* Enable debug requests */
2143 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2144 if (retval != ERROR_OK)
2145 return retval;
2146 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2147 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2148
2149 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2150 if (retval != ERROR_OK)
2151 return retval;
2152 cortex_m->dcb_dhcsr = dhcsr;
2153 }
2154
2155 /* Configure trace modules */
2156 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2157 if (retval != ERROR_OK)
2158 return retval;
2159
2160 if (armv7m->trace_config.itm_deferred_config)
2161 armv7m_trace_itm_config(target);
2162
2163 /* NOTE: FPB and DWT are both optional. */
2164
2165 /* Setup FPB */
2166 target_read_u32(target, FP_CTRL, &fpcr);
2167 /* bits [14:12] and [7:4] */
2168 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2169 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2170 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2171 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2172 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2173 free(cortex_m->fp_comparator_list);
2174 cortex_m->fp_comparator_list = calloc(
2175 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2176 sizeof(struct cortex_m_fp_comparator));
2177 cortex_m->fpb_enabled = fpcr & 1;
2178 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2179 cortex_m->fp_comparator_list[i].type =
2180 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2181 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2182
2183 /* make sure we clear any breakpoints enabled on the target */
2184 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2185 }
2186 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2187 fpcr,
2188 cortex_m->fp_num_code,
2189 cortex_m->fp_num_lit);
2190
2191 /* Setup DWT */
2192 cortex_m_dwt_free(target);
2193 cortex_m_dwt_setup(cortex_m, target);
2194
2195 /* These hardware breakpoints only work for code in flash! */
2196 LOG_INFO("%s: target has %d breakpoints, %d watchpoints",
2197 target_name(target),
2198 cortex_m->fp_num_code,
2199 cortex_m->dwt_num_comp);
2200 }
2201
2202 return ERROR_OK;
2203 }
2204
2205 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2206 {
2207 struct armv7m_common *armv7m = target_to_armv7m(target);
2208 uint16_t dcrdr;
2209 uint8_t buf[2];
2210 int retval;
2211
2212 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2213 if (retval != ERROR_OK)
2214 return retval;
2215
2216 dcrdr = target_buffer_get_u16(target, buf);
2217 *ctrl = (uint8_t)dcrdr;
2218 *value = (uint8_t)(dcrdr >> 8);
2219
2220 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2221
2222 /* write ack back to software dcc register
2223 * signify we have read data */
2224 if (dcrdr & (1 << 0)) {
2225 target_buffer_set_u16(target, buf, 0);
2226 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2227 if (retval != ERROR_OK)
2228 return retval;
2229 }
2230
2231 return ERROR_OK;
2232 }
2233
2234 static int cortex_m_target_request_data(struct target *target,
2235 uint32_t size, uint8_t *buffer)
2236 {
2237 uint8_t data;
2238 uint8_t ctrl;
2239 uint32_t i;
2240
2241 for (i = 0; i < (size * 4); i++) {
2242 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2243 if (retval != ERROR_OK)
2244 return retval;
2245 buffer[i] = data;
2246 }
2247
2248 return ERROR_OK;
2249 }
2250
2251 static int cortex_m_handle_target_request(void *priv)
2252 {
2253 struct target *target = priv;
2254 if (!target_was_examined(target))
2255 return ERROR_OK;
2256
2257 if (!target->dbg_msg_enabled)
2258 return ERROR_OK;
2259
2260 if (target->state == TARGET_RUNNING) {
2261 uint8_t data;
2262 uint8_t ctrl;
2263 int retval;
2264
2265 retval = cortex_m_dcc_read(target, &data, &ctrl);
2266 if (retval != ERROR_OK)
2267 return retval;
2268
2269 /* check if we have data */
2270 if (ctrl & (1 << 0)) {
2271 uint32_t request;
2272
2273 /* we assume target is quick enough */
2274 request = data;
2275 for (int i = 1; i <= 3; i++) {
2276 retval = cortex_m_dcc_read(target, &data, &ctrl);
2277 if (retval != ERROR_OK)
2278 return retval;
2279 request |= ((uint32_t)data << (i * 8));
2280 }
2281 target_request(target, request);
2282 }
2283 }
2284
2285 return ERROR_OK;
2286 }
2287
2288 static int cortex_m_init_arch_info(struct target *target,
2289 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2290 {
2291 struct armv7m_common *armv7m = &cortex_m->armv7m;
2292
2293 armv7m_init_arch_info(target, armv7m);
2294
2295 /* default reset mode is to use srst if fitted
2296 * if not it will use CORTEX_M3_RESET_VECTRESET */
2297 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2298
2299 armv7m->arm.dap = dap;
2300
2301 /* register arch-specific functions */
2302 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2303
2304 armv7m->post_debug_entry = NULL;
2305
2306 armv7m->pre_restore_context = NULL;
2307
2308 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2309 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2310
2311 target_register_timer_callback(cortex_m_handle_target_request, 1,
2312 TARGET_TIMER_TYPE_PERIODIC, target);
2313
2314 return ERROR_OK;
2315 }
2316
2317 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2318 {
2319 struct adiv5_private_config *pc;
2320
2321 pc = (struct adiv5_private_config *)target->private_config;
2322 if (adiv5_verify_config(pc) != ERROR_OK)
2323 return ERROR_FAIL;
2324
2325 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2326 if (!cortex_m) {
2327 LOG_ERROR("No memory creating target");
2328 return ERROR_FAIL;
2329 }
2330
2331 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2332 cortex_m->apsel = pc->ap_num;
2333
2334 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2335
2336 return ERROR_OK;
2337 }
2338
2339 /*--------------------------------------------------------------------------*/
2340
2341 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2342 struct cortex_m_common *cm)
2343 {
2344 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2345 command_print(cmd, "target is not a Cortex-M");
2346 return ERROR_TARGET_INVALID;
2347 }
2348 return ERROR_OK;
2349 }
2350
2351 /*
2352 * Only stuff below this line should need to verify that its target
2353 * is a Cortex-M3. Everything else should have indirected through the
2354 * cortexm3_target structure, which is only used with CM3 targets.
2355 */
2356
2357 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2358 {
2359 struct target *target = get_current_target(CMD_CTX);
2360 struct cortex_m_common *cortex_m = target_to_cm(target);
2361 struct armv7m_common *armv7m = &cortex_m->armv7m;
2362 uint32_t demcr = 0;
2363 int retval;
2364
2365 static const struct {
2366 char name[10];
2367 unsigned mask;
2368 } vec_ids[] = {
2369 { "hard_err", VC_HARDERR, },
2370 { "int_err", VC_INTERR, },
2371 { "bus_err", VC_BUSERR, },
2372 { "state_err", VC_STATERR, },
2373 { "chk_err", VC_CHKERR, },
2374 { "nocp_err", VC_NOCPERR, },
2375 { "mm_err", VC_MMERR, },
2376 { "reset", VC_CORERESET, },
2377 };
2378
2379 retval = cortex_m_verify_pointer(CMD, cortex_m);
2380 if (retval != ERROR_OK)
2381 return retval;
2382
2383 if (!target_was_examined(target)) {
2384 LOG_ERROR("Target not examined yet");
2385 return ERROR_FAIL;
2386 }
2387
2388 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2389 if (retval != ERROR_OK)
2390 return retval;
2391
2392 if (CMD_ARGC > 0) {
2393 unsigned catch = 0;
2394
2395 if (CMD_ARGC == 1) {
2396 if (strcmp(CMD_ARGV[0], "all") == 0) {
2397 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2398 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2399 | VC_MMERR | VC_CORERESET;
2400 goto write;
2401 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2402 goto write;
2403 }
2404 while (CMD_ARGC-- > 0) {
2405 unsigned i;
2406 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2407 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2408 continue;
2409 catch |= vec_ids[i].mask;
2410 break;
2411 }
2412 if (i == ARRAY_SIZE(vec_ids)) {
2413 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2414 return ERROR_COMMAND_SYNTAX_ERROR;
2415 }
2416 }
2417 write:
2418 /* For now, armv7m->demcr only stores vector catch flags. */
2419 armv7m->demcr = catch;
2420
2421 demcr &= ~0xffff;
2422 demcr |= catch;
2423
2424 /* write, but don't assume it stuck (why not??) */
2425 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2426 if (retval != ERROR_OK)
2427 return retval;
2428 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2429 if (retval != ERROR_OK)
2430 return retval;
2431
2432 /* FIXME be sure to clear DEMCR on clean server shutdown.
2433 * Otherwise the vector catch hardware could fire when there's
2434 * no debugger hooked up, causing much confusion...
2435 */
2436 }
2437
2438 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2439 command_print(CMD, "%9s: %s", vec_ids[i].name,
2440 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2441 }
2442
2443 return ERROR_OK;
2444 }
2445
2446 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2447 {
2448 struct target *target = get_current_target(CMD_CTX);
2449 struct cortex_m_common *cortex_m = target_to_cm(target);
2450 int retval;
2451
2452 static const struct jim_nvp nvp_maskisr_modes[] = {
2453 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2454 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2455 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2456 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2457 { .name = NULL, .value = -1 },
2458 };
2459 const struct jim_nvp *n;
2460
2461
2462 retval = cortex_m_verify_pointer(CMD, cortex_m);
2463 if (retval != ERROR_OK)
2464 return retval;
2465
2466 if (target->state != TARGET_HALTED) {
2467 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2468 return ERROR_OK;
2469 }
2470
2471 if (CMD_ARGC > 0) {
2472 n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2473 if (!n->name)
2474 return ERROR_COMMAND_SYNTAX_ERROR;
2475 cortex_m->isrmasking_mode = n->value;
2476 cortex_m_set_maskints_for_halt(target);
2477 }
2478
2479 n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2480 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2481
2482 return ERROR_OK;
2483 }
2484
2485 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2486 {
2487 struct target *target = get_current_target(CMD_CTX);
2488 struct cortex_m_common *cortex_m = target_to_cm(target);
2489 int retval;
2490 char *reset_config;
2491
2492 retval = cortex_m_verify_pointer(CMD, cortex_m);
2493 if (retval != ERROR_OK)
2494 return retval;
2495
2496 if (CMD_ARGC > 0) {
2497 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2498 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2499
2500 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2501 if (target_was_examined(target)
2502 && !cortex_m->vectreset_supported)
2503 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2504 else
2505 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2506
2507 } else
2508 return ERROR_COMMAND_SYNTAX_ERROR;
2509 }
2510
2511 switch (cortex_m->soft_reset_config) {
2512 case CORTEX_M_RESET_SYSRESETREQ:
2513 reset_config = "sysresetreq";
2514 break;
2515
2516 case CORTEX_M_RESET_VECTRESET:
2517 reset_config = "vectreset";
2518 break;
2519
2520 default:
2521 reset_config = "unknown";
2522 break;
2523 }
2524
2525 command_print(CMD, "cortex_m reset_config %s", reset_config);
2526
2527 return ERROR_OK;
2528 }
2529
2530 static const struct command_registration cortex_m_exec_command_handlers[] = {
2531 {
2532 .name = "maskisr",
2533 .handler = handle_cortex_m_mask_interrupts_command,
2534 .mode = COMMAND_EXEC,
2535 .help = "mask cortex_m interrupts",
2536 .usage = "['auto'|'on'|'off'|'steponly']",
2537 },
2538 {
2539 .name = "vector_catch",
2540 .handler = handle_cortex_m_vector_catch_command,
2541 .mode = COMMAND_EXEC,
2542 .help = "configure hardware vectors to trigger debug entry",
2543 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2544 },
2545 {
2546 .name = "reset_config",
2547 .handler = handle_cortex_m_reset_config_command,
2548 .mode = COMMAND_ANY,
2549 .help = "configure software reset handling",
2550 .usage = "['sysresetreq'|'vectreset']",
2551 },
2552 COMMAND_REGISTRATION_DONE
2553 };
2554 static const struct command_registration cortex_m_command_handlers[] = {
2555 {
2556 .chain = armv7m_command_handlers,
2557 },
2558 {
2559 .chain = armv7m_trace_command_handlers,
2560 },
2561 /* START_DEPRECATED_TPIU */
2562 {
2563 .chain = arm_tpiu_deprecated_command_handlers,
2564 },
2565 /* END_DEPRECATED_TPIU */
2566 {
2567 .name = "cortex_m",
2568 .mode = COMMAND_EXEC,
2569 .help = "Cortex-M command group",
2570 .usage = "",
2571 .chain = cortex_m_exec_command_handlers,
2572 },
2573 {
2574 .chain = rtt_target_command_handlers,
2575 },
2576 COMMAND_REGISTRATION_DONE
2577 };
2578
2579 struct target_type cortexm_target = {
2580 .name = "cortex_m",
2581
2582 .poll = cortex_m_poll,
2583 .arch_state = armv7m_arch_state,
2584
2585 .target_request_data = cortex_m_target_request_data,
2586
2587 .halt = cortex_m_halt,
2588 .resume = cortex_m_resume,
2589 .step = cortex_m_step,
2590
2591 .assert_reset = cortex_m_assert_reset,
2592 .deassert_reset = cortex_m_deassert_reset,
2593 .soft_reset_halt = cortex_m_soft_reset_halt,
2594
2595 .get_gdb_arch = arm_get_gdb_arch,
2596 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2597
2598 .read_memory = cortex_m_read_memory,
2599 .write_memory = cortex_m_write_memory,
2600 .checksum_memory = armv7m_checksum_memory,
2601 .blank_check_memory = armv7m_blank_check_memory,
2602
2603 .run_algorithm = armv7m_run_algorithm,
2604 .start_algorithm = armv7m_start_algorithm,
2605 .wait_algorithm = armv7m_wait_algorithm,
2606
2607 .add_breakpoint = cortex_m_add_breakpoint,
2608 .remove_breakpoint = cortex_m_remove_breakpoint,
2609 .add_watchpoint = cortex_m_add_watchpoint,
2610 .remove_watchpoint = cortex_m_remove_watchpoint,
2611 .hit_watchpoint = cortex_m_hit_watchpoint,
2612
2613 .commands = cortex_m_command_handlers,
2614 .target_create = cortex_m_target_create,
2615 .target_jim_configure = adiv5_jim_configure,
2616 .init_target = cortex_m_init_target,
2617 .examine = cortex_m_examine,
2618 .deinit_target = cortex_m_deinit_target,
2619
2620 .profiling = cortex_m_profiling,
2621 };
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