1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
55 * Returns the type of a break point required by address location
57 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
59 /* forward declarations */
60 static int cortex_m_store_core_reg_u32(struct target
*target
,
61 uint32_t num
, uint32_t value
);
62 static void cortex_m_dwt_free(struct target
*target
);
64 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
65 uint32_t *value
, int regnum
)
67 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
71 /* because the DCB_DCRDR is used for the emulated dcc channel
72 * we have to save/restore the DCB_DCRDR when used */
73 if (target
->dbg_msg_enabled
) {
74 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
75 if (retval
!= ERROR_OK
)
79 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
);
80 if (retval
!= ERROR_OK
)
83 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
84 if (retval
!= ERROR_OK
)
87 if (target
->dbg_msg_enabled
) {
88 /* restore DCB_DCRDR - this needs to be in a separate
89 * transaction otherwise the emulated DCC channel breaks */
90 if (retval
== ERROR_OK
)
91 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
97 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
98 uint32_t value
, int regnum
)
100 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
104 /* because the DCB_DCRDR is used for the emulated dcc channel
105 * we have to save/restore the DCB_DCRDR when used */
106 if (target
->dbg_msg_enabled
) {
107 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
108 if (retval
!= ERROR_OK
)
112 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
113 if (retval
!= ERROR_OK
)
116 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
117 if (retval
!= ERROR_OK
)
120 if (target
->dbg_msg_enabled
) {
121 /* restore DCB_DCRDR - this needs to be in a seperate
122 * transaction otherwise the emulated DCC channel breaks */
123 if (retval
== ERROR_OK
)
124 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
130 static int cortex_m_write_debug_halt_mask(struct target
*target
,
131 uint32_t mask_on
, uint32_t mask_off
)
133 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
134 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
136 /* mask off status bits */
137 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
138 /* create new register mask */
139 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
141 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
144 static int cortex_m_clear_halt(struct target
*target
)
146 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
147 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
150 /* clear step if any */
151 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
153 /* Read Debug Fault Status Register */
154 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
155 if (retval
!= ERROR_OK
)
158 /* Clear Debug Fault Status */
159 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
160 if (retval
!= ERROR_OK
)
162 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
167 static int cortex_m_single_step_core(struct target
*target
)
169 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
170 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
174 /* backup dhcsr reg */
175 dhcsr_save
= cortex_m
->dcb_dhcsr
;
177 /* Mask interrupts before clearing halt, if done already. This avoids
178 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
179 * HALT can put the core into an unknown state.
181 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
182 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
183 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
184 if (retval
!= ERROR_OK
)
187 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
188 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
189 if (retval
!= ERROR_OK
)
193 /* restore dhcsr reg */
194 cortex_m
->dcb_dhcsr
= dhcsr_save
;
195 cortex_m_clear_halt(target
);
200 static int cortex_m_enable_fpb(struct target
*target
)
202 int retval
= target_write_u32(target
, FP_CTRL
, 3);
203 if (retval
!= ERROR_OK
)
206 /* check the fpb is actually enabled */
208 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
209 if (retval
!= ERROR_OK
)
218 static int cortex_m_endreset_event(struct target
*target
)
223 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
224 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
225 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
226 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
227 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
231 if (retval
!= ERROR_OK
)
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
235 /* this register is used for emulated dcc channel */
236 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
237 if (retval
!= ERROR_OK
)
240 /* Enable debug requests */
241 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
242 if (retval
!= ERROR_OK
)
244 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
245 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
246 if (retval
!= ERROR_OK
)
250 /* clear any interrupt masking */
251 cortex_m_write_debug_halt_mask(target
, 0, C_MASKINTS
);
253 /* Enable features controlled by ITM and DWT blocks, and catch only
254 * the vectors we were told to pay attention to.
256 * Target firmware is responsible for all fault handling policy
257 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
258 * or manual updates to the NVIC SHCSR and CCR registers.
260 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
261 if (retval
!= ERROR_OK
)
264 /* Paranoia: evidently some (early?) chips don't preserve all the
265 * debug state (including FBP, DWT, etc) across reset...
269 retval
= cortex_m_enable_fpb(target
);
270 if (retval
!= ERROR_OK
) {
271 LOG_ERROR("Failed to enable the FPB");
275 cortex_m
->fpb_enabled
= 1;
277 /* Restore FPB registers */
278 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
279 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
280 if (retval
!= ERROR_OK
)
284 /* Restore DWT registers */
285 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
286 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
288 if (retval
!= ERROR_OK
)
290 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
292 if (retval
!= ERROR_OK
)
294 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
295 dwt_list
[i
].function
);
296 if (retval
!= ERROR_OK
)
299 retval
= dap_run(swjdp
);
300 if (retval
!= ERROR_OK
)
303 register_cache_invalidate(armv7m
->arm
.core_cache
);
305 /* make sure we have latest dhcsr flags */
306 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
311 static int cortex_m_examine_debug_reason(struct target
*target
)
313 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
315 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
316 * only check the debug reason if we don't know it already */
318 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
319 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
320 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
321 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
322 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
323 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
324 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
325 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
326 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
327 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
328 else /* EXTERNAL, HALTED */
329 target
->debug_reason
= DBG_REASON_UNDEFINED
;
335 static int cortex_m_examine_exception_reason(struct target
*target
)
337 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
338 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
339 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
342 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
343 if (retval
!= ERROR_OK
)
345 switch (armv7m
->exception_number
) {
348 case 3: /* Hard Fault */
349 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
350 if (retval
!= ERROR_OK
)
352 if (except_sr
& 0x40000000) {
353 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
354 if (retval
!= ERROR_OK
)
358 case 4: /* Memory Management */
359 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
360 if (retval
!= ERROR_OK
)
362 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
363 if (retval
!= ERROR_OK
)
366 case 5: /* Bus Fault */
367 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
368 if (retval
!= ERROR_OK
)
370 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
371 if (retval
!= ERROR_OK
)
374 case 6: /* Usage Fault */
375 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
376 if (retval
!= ERROR_OK
)
379 case 11: /* SVCall */
381 case 12: /* Debug Monitor */
382 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
383 if (retval
!= ERROR_OK
)
386 case 14: /* PendSV */
388 case 15: /* SysTick */
394 retval
= dap_run(swjdp
);
395 if (retval
== ERROR_OK
)
396 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
397 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
398 armv7m_exception_string(armv7m
->exception_number
),
399 shcsr
, except_sr
, cfsr
, except_ar
);
403 static int cortex_m_debug_entry(struct target
*target
)
408 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
409 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
410 struct arm
*arm
= &armv7m
->arm
;
415 cortex_m_clear_halt(target
);
416 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
417 if (retval
!= ERROR_OK
)
420 retval
= armv7m
->examine_debug_reason(target
);
421 if (retval
!= ERROR_OK
)
424 /* Examine target state and mode
425 * First load register accessible through core debug port */
426 int num_regs
= arm
->core_cache
->num_regs
;
428 for (i
= 0; i
< num_regs
; i
++) {
429 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
431 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
435 xPSR
= buf_get_u32(r
->value
, 0, 32);
437 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
440 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
443 /* Are we in an exception handler */
445 armv7m
->exception_number
= (xPSR
& 0x1FF);
447 arm
->core_mode
= ARM_MODE_HANDLER
;
448 arm
->map
= armv7m_msp_reg_map
;
450 unsigned control
= buf_get_u32(arm
->core_cache
451 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
453 /* is this thread privileged? */
454 arm
->core_mode
= control
& 1
455 ? ARM_MODE_USER_THREAD
458 /* which stack is it using? */
460 arm
->map
= armv7m_psp_reg_map
;
462 arm
->map
= armv7m_msp_reg_map
;
464 armv7m
->exception_number
= 0;
467 if (armv7m
->exception_number
)
468 cortex_m_examine_exception_reason(target
);
470 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
471 arm_mode_name(arm
->core_mode
),
472 buf_get_u32(arm
->pc
->value
, 0, 32),
473 target_state_name(target
));
475 if (armv7m
->post_debug_entry
) {
476 retval
= armv7m
->post_debug_entry(target
);
477 if (retval
!= ERROR_OK
)
484 static int cortex_m_poll(struct target
*target
)
486 int detected_failure
= ERROR_OK
;
487 int retval
= ERROR_OK
;
488 enum target_state prev_target_state
= target
->state
;
489 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
490 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
492 /* Read from Debug Halting Control and Status Register */
493 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
494 if (retval
!= ERROR_OK
) {
495 target
->state
= TARGET_UNKNOWN
;
499 /* Recover from lockup. See ARMv7-M architecture spec,
500 * section B1.5.15 "Unrecoverable exception cases".
502 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
503 LOG_ERROR("%s -- clearing lockup after double fault",
504 target_name(target
));
505 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
506 target
->debug_reason
= DBG_REASON_DBGRQ
;
508 /* We have to execute the rest (the "finally" equivalent, but
509 * still throw this exception again).
511 detected_failure
= ERROR_FAIL
;
513 /* refresh status bits */
514 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
515 if (retval
!= ERROR_OK
)
519 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
520 target
->state
= TARGET_RESET
;
524 if (target
->state
== TARGET_RESET
) {
525 /* Cannot switch context while running so endreset is
526 * called with target->state == TARGET_RESET
528 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
529 cortex_m
->dcb_dhcsr
);
530 retval
= cortex_m_endreset_event(target
);
531 if (retval
!= ERROR_OK
) {
532 target
->state
= TARGET_UNKNOWN
;
535 target
->state
= TARGET_RUNNING
;
536 prev_target_state
= TARGET_RUNNING
;
539 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
540 target
->state
= TARGET_HALTED
;
542 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
543 retval
= cortex_m_debug_entry(target
);
544 if (retval
!= ERROR_OK
)
547 if (arm_semihosting(target
, &retval
) != 0)
550 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
552 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
554 retval
= cortex_m_debug_entry(target
);
555 if (retval
!= ERROR_OK
)
558 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
562 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
563 * How best to model low power modes?
566 if (target
->state
== TARGET_UNKNOWN
) {
567 /* check if processor is retiring instructions */
568 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
569 target
->state
= TARGET_RUNNING
;
574 /* Did we detect a failure condition that we cleared? */
575 if (detected_failure
!= ERROR_OK
)
576 retval
= detected_failure
;
580 static int cortex_m_halt(struct target
*target
)
582 LOG_DEBUG("target->state: %s",
583 target_state_name(target
));
585 if (target
->state
== TARGET_HALTED
) {
586 LOG_DEBUG("target was already halted");
590 if (target
->state
== TARGET_UNKNOWN
)
591 LOG_WARNING("target was in unknown state when halt was requested");
593 if (target
->state
== TARGET_RESET
) {
594 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
595 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
596 return ERROR_TARGET_FAILURE
;
598 /* we came here in a reset_halt or reset_init sequence
599 * debug entry was already prepared in cortex_m3_assert_reset()
601 target
->debug_reason
= DBG_REASON_DBGRQ
;
607 /* Write to Debug Halting Control and Status Register */
608 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
610 target
->debug_reason
= DBG_REASON_DBGRQ
;
615 static int cortex_m_soft_reset_halt(struct target
*target
)
617 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
618 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
619 uint32_t dcb_dhcsr
= 0;
620 int retval
, timeout
= 0;
622 /* soft_reset_halt is deprecated on cortex_m as the same functionality
623 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
624 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
625 * core, not the peripherals */
626 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
628 /* Enter debug state on reset; restore DEMCR in endreset_event() */
629 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
630 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
631 if (retval
!= ERROR_OK
)
634 /* Request a core-only reset */
635 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
636 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
637 if (retval
!= ERROR_OK
)
639 target
->state
= TARGET_RESET
;
641 /* registers are now invalid */
642 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
644 while (timeout
< 100) {
645 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
646 if (retval
== ERROR_OK
) {
647 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
648 &cortex_m
->nvic_dfsr
);
649 if (retval
!= ERROR_OK
)
651 if ((dcb_dhcsr
& S_HALT
)
652 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
653 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
655 (unsigned) dcb_dhcsr
,
656 (unsigned) cortex_m
->nvic_dfsr
);
657 cortex_m_poll(target
);
658 /* FIXME restore user's vector catch config */
661 LOG_DEBUG("waiting for system reset-halt, "
662 "DHCSR 0x%08x, %d ms",
663 (unsigned) dcb_dhcsr
, timeout
);
672 void cortex_m_enable_breakpoints(struct target
*target
)
674 struct breakpoint
*breakpoint
= target
->breakpoints
;
676 /* set any pending breakpoints */
678 if (!breakpoint
->set
)
679 cortex_m_set_breakpoint(target
, breakpoint
);
680 breakpoint
= breakpoint
->next
;
684 static int cortex_m_resume(struct target
*target
, int current
,
685 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
687 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
688 struct breakpoint
*breakpoint
= NULL
;
692 if (target
->state
!= TARGET_HALTED
) {
693 LOG_WARNING("target not halted");
694 return ERROR_TARGET_NOT_HALTED
;
697 if (!debug_execution
) {
698 target_free_all_working_areas(target
);
699 cortex_m_enable_breakpoints(target
);
700 cortex_m_enable_watchpoints(target
);
703 if (debug_execution
) {
704 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
706 /* Disable interrupts */
707 /* We disable interrupts in the PRIMASK register instead of
708 * masking with C_MASKINTS. This is probably the same issue
709 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
710 * in parallel with disabled interrupts can cause local faults
713 * REVISIT this clearly breaks non-debug execution, since the
714 * PRIMASK register state isn't saved/restored... workaround
715 * by never resuming app code after debug execution.
717 buf_set_u32(r
->value
, 0, 1, 1);
721 /* Make sure we are in Thumb mode */
722 r
= armv7m
->arm
.cpsr
;
723 buf_set_u32(r
->value
, 24, 1, 1);
728 /* current = 1: continue on current pc, otherwise continue at <address> */
731 buf_set_u32(r
->value
, 0, 32, address
);
736 /* if we halted last time due to a bkpt instruction
737 * then we have to manually step over it, otherwise
738 * the core will break again */
740 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
742 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
744 resume_pc
= buf_get_u32(r
->value
, 0, 32);
746 armv7m_restore_context(target
);
748 /* the front-end may request us not to handle breakpoints */
749 if (handle_breakpoints
) {
750 /* Single step past breakpoint at current address */
751 breakpoint
= breakpoint_find(target
, resume_pc
);
753 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
755 breakpoint
->unique_id
);
756 cortex_m_unset_breakpoint(target
, breakpoint
);
757 cortex_m_single_step_core(target
);
758 cortex_m_set_breakpoint(target
, breakpoint
);
763 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
765 target
->debug_reason
= DBG_REASON_NOTHALTED
;
767 /* registers are now invalid */
768 register_cache_invalidate(armv7m
->arm
.core_cache
);
770 if (!debug_execution
) {
771 target
->state
= TARGET_RUNNING
;
772 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
773 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
775 target
->state
= TARGET_DEBUG_RUNNING
;
776 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
777 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
783 /* int irqstepcount = 0; */
784 static int cortex_m_step(struct target
*target
, int current
,
785 target_addr_t address
, int handle_breakpoints
)
787 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
788 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
789 struct breakpoint
*breakpoint
= NULL
;
790 struct reg
*pc
= armv7m
->arm
.pc
;
791 bool bkpt_inst_found
= false;
793 bool isr_timed_out
= false;
795 if (target
->state
!= TARGET_HALTED
) {
796 LOG_WARNING("target not halted");
797 return ERROR_TARGET_NOT_HALTED
;
800 /* current = 1: continue on current pc, otherwise continue at <address> */
802 buf_set_u32(pc
->value
, 0, 32, address
);
804 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
806 /* the front-end may request us not to handle breakpoints */
807 if (handle_breakpoints
) {
808 breakpoint
= breakpoint_find(target
, pc_value
);
810 cortex_m_unset_breakpoint(target
, breakpoint
);
813 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
815 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
817 armv7m_restore_context(target
);
819 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
821 /* if no bkpt instruction is found at pc then we can perform
822 * a normal step, otherwise we have to manually step over the bkpt
823 * instruction - as such simulate a step */
824 if (bkpt_inst_found
== false) {
825 /* Automatic ISR masking mode off: Just step over the next instruction */
826 if ((cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
))
827 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
829 /* Process interrupts during stepping in a way they don't interfere
834 * Set a temporary break point at the current pc and let the core run
835 * with interrupts enabled. Pending interrupts get served and we run
836 * into the breakpoint again afterwards. Then we step over the next
837 * instruction with interrupts disabled.
839 * If the pending interrupts don't complete within time, we leave the
840 * core running. This may happen if the interrupts trigger faster
841 * than the core can process them or the handler doesn't return.
843 * If no more breakpoints are available we simply do a step with
844 * interrupts enabled.
850 * If a break point is already set on the lower half word then a break point on
851 * the upper half word will not break again when the core is restarted. So we
852 * just step over the instruction with interrupts disabled.
854 * The documentation has no information about this, it was found by observation
855 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
856 * suffer from this problem.
858 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
859 * address has it always cleared. The former is done to indicate thumb mode
863 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
864 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
865 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
866 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
867 /* Re-enable interrupts */
868 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
872 /* Set a temporary break point */
874 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
876 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
877 bool tmp_bp_set
= (retval
== ERROR_OK
);
879 /* No more breakpoints left, just do a step */
881 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
884 LOG_DEBUG("Starting core to serve pending interrupts");
885 int64_t t_start
= timeval_ms();
886 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
888 /* Wait for pending handlers to complete or timeout */
890 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
892 &cortex_m
->dcb_dhcsr
);
893 if (retval
!= ERROR_OK
) {
894 target
->state
= TARGET_UNKNOWN
;
897 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
898 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
900 /* only remove breakpoint if we created it */
902 cortex_m_unset_breakpoint(target
, breakpoint
);
904 /* Remove the temporary breakpoint */
905 breakpoint_remove(target
, pc_value
);
909 LOG_DEBUG("Interrupt handlers didn't complete within time, "
910 "leaving target running");
912 /* Step over next instruction with interrupts disabled */
913 cortex_m_write_debug_halt_mask(target
,
916 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
917 /* Re-enable interrupts */
918 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
925 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
926 if (retval
!= ERROR_OK
)
929 /* registers are now invalid */
930 register_cache_invalidate(armv7m
->arm
.core_cache
);
933 cortex_m_set_breakpoint(target
, breakpoint
);
936 /* Leave the core running. The user has to stop execution manually. */
937 target
->debug_reason
= DBG_REASON_NOTHALTED
;
938 target
->state
= TARGET_RUNNING
;
942 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
943 " nvic_icsr = 0x%" PRIx32
,
944 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
946 retval
= cortex_m_debug_entry(target
);
947 if (retval
!= ERROR_OK
)
949 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
951 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
952 " nvic_icsr = 0x%" PRIx32
,
953 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
958 static int cortex_m_assert_reset(struct target
*target
)
960 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
961 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
962 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
964 LOG_DEBUG("target->state: %s",
965 target_state_name(target
));
967 enum reset_types jtag_reset_config
= jtag_get_reset_config();
969 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
970 /* allow scripts to override the reset event */
972 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
973 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
974 target
->state
= TARGET_RESET
;
979 /* some cores support connecting while srst is asserted
980 * use that mode is it has been configured */
982 bool srst_asserted
= false;
984 if (!target_was_examined(target
)) {
985 if (jtag_reset_config
& RESET_HAS_SRST
) {
986 adapter_assert_reset();
987 if (target
->reset_halt
)
988 LOG_ERROR("Target not examined, will not halt after reset!");
991 LOG_ERROR("Target not examined, reset NOT asserted!");
996 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
997 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
998 adapter_assert_reset();
999 srst_asserted
= true;
1002 /* Enable debug requests */
1004 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1005 /* Store important errors instead of failing and proceed to reset assert */
1007 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1008 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1010 /* If the processor is sleeping in a WFI or WFE instruction, the
1011 * C_HALT bit must be asserted to regain control */
1012 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1013 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1015 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1016 /* Ignore less important errors */
1018 if (!target
->reset_halt
) {
1019 /* Set/Clear C_MASKINTS in a separate operation */
1020 if (cortex_m
->dcb_dhcsr
& C_MASKINTS
)
1021 cortex_m_write_debug_halt_mask(target
, 0, C_MASKINTS
);
1023 /* clear any debug flags before resuming */
1024 cortex_m_clear_halt(target
);
1026 /* clear C_HALT in dhcsr reg */
1027 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1029 /* Halt in debug on reset; endreset_event() restores DEMCR.
1031 * REVISIT catching BUSERR presumably helps to defend against
1032 * bad vector table entries. Should this include MMERR or
1036 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1037 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1038 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1039 LOG_INFO("AP write error, reset will not halt");
1042 if (jtag_reset_config
& RESET_HAS_SRST
) {
1043 /* default to asserting srst */
1045 adapter_assert_reset();
1047 /* srst is asserted, ignore AP access errors */
1050 /* Use a standard Cortex-M3 software reset mechanism.
1051 * We default to using VECRESET as it is supported on all current cores.
1052 * This has the disadvantage of not resetting the peripherals, so a
1053 * reset-init event handler is needed to perform any peripheral resets.
1055 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1056 ? "SYSRESETREQ" : "VECTRESET");
1058 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1059 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1060 "handler to reset any peripherals or configure hardware srst support.");
1064 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1065 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1066 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1067 if (retval3
!= ERROR_OK
)
1068 LOG_DEBUG("Ignoring AP write error right after reset");
1070 retval3
= dap_dp_init(armv7m
->debug_ap
->dap
);
1071 if (retval3
!= ERROR_OK
)
1072 LOG_ERROR("DP initialisation failed");
1075 /* I do not know why this is necessary, but it
1076 * fixes strange effects (step/resume cause NMI
1077 * after reset) on LM3S6918 -- Michael Schwingen
1080 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1084 target
->state
= TARGET_RESET
;
1085 jtag_add_sleep(50000);
1087 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1089 /* now return stored error code if any */
1090 if (retval
!= ERROR_OK
)
1093 if (target
->reset_halt
) {
1094 retval
= target_halt(target
);
1095 if (retval
!= ERROR_OK
)
1102 static int cortex_m_deassert_reset(struct target
*target
)
1104 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1106 LOG_DEBUG("target->state: %s",
1107 target_state_name(target
));
1109 /* deassert reset lines */
1110 adapter_deassert_reset();
1112 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1114 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1115 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1116 target_was_examined(target
)) {
1117 int retval
= dap_dp_init(armv7m
->debug_ap
->dap
);
1118 if (retval
!= ERROR_OK
) {
1119 LOG_ERROR("DP initialisation failed");
1127 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1131 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1132 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1134 if (breakpoint
->set
) {
1135 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1139 if (cortex_m
->auto_bp_type
)
1140 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1142 if (breakpoint
->type
== BKPT_HARD
) {
1143 uint32_t fpcr_value
;
1144 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1146 if (fp_num
>= cortex_m
->fp_num_code
) {
1147 LOG_ERROR("Can not find free FPB Comparator!");
1150 breakpoint
->set
= fp_num
+ 1;
1151 fpcr_value
= breakpoint
->address
| 1;
1152 if (cortex_m
->fp_rev
== 0) {
1154 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1155 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1156 } else if (cortex_m
->fp_rev
> 1) {
1157 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1160 comparator_list
[fp_num
].used
= 1;
1161 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1162 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1163 comparator_list
[fp_num
].fpcr_value
);
1164 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1166 comparator_list
[fp_num
].fpcr_value
);
1167 if (!cortex_m
->fpb_enabled
) {
1168 LOG_DEBUG("FPB wasn't enabled, do it now");
1169 retval
= cortex_m_enable_fpb(target
);
1170 if (retval
!= ERROR_OK
) {
1171 LOG_ERROR("Failed to enable the FPB");
1175 cortex_m
->fpb_enabled
= 1;
1177 } else if (breakpoint
->type
== BKPT_SOFT
) {
1180 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1181 * semihosting; don't use that. Otherwise the BKPT
1182 * parameter is arbitrary.
1184 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1185 retval
= target_read_memory(target
,
1186 breakpoint
->address
& 0xFFFFFFFE,
1187 breakpoint
->length
, 1,
1188 breakpoint
->orig_instr
);
1189 if (retval
!= ERROR_OK
)
1191 retval
= target_write_memory(target
,
1192 breakpoint
->address
& 0xFFFFFFFE,
1193 breakpoint
->length
, 1,
1195 if (retval
!= ERROR_OK
)
1197 breakpoint
->set
= true;
1200 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1201 breakpoint
->unique_id
,
1202 (int)(breakpoint
->type
),
1203 breakpoint
->address
,
1210 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1213 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1214 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1216 if (!breakpoint
->set
) {
1217 LOG_WARNING("breakpoint not set");
1221 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1222 breakpoint
->unique_id
,
1223 (int)(breakpoint
->type
),
1224 breakpoint
->address
,
1228 if (breakpoint
->type
== BKPT_HARD
) {
1229 int fp_num
= breakpoint
->set
- 1;
1230 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1231 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1234 comparator_list
[fp_num
].used
= 0;
1235 comparator_list
[fp_num
].fpcr_value
= 0;
1236 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1237 comparator_list
[fp_num
].fpcr_value
);
1239 /* restore original instruction (kept in target endianness) */
1240 if (breakpoint
->length
== 4) {
1241 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1242 breakpoint
->orig_instr
);
1243 if (retval
!= ERROR_OK
)
1246 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1247 breakpoint
->orig_instr
);
1248 if (retval
!= ERROR_OK
)
1252 breakpoint
->set
= false;
1257 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1259 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1261 if (cortex_m
->auto_bp_type
)
1262 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1264 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1265 if (breakpoint
->type
== BKPT_HARD
) {
1266 LOG_INFO("flash patch comparator requested outside code memory region");
1267 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1270 if (breakpoint
->type
== BKPT_SOFT
) {
1271 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1272 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1276 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m
->fp_code_available
< 1)) {
1277 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1278 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1281 if (breakpoint
->length
== 3) {
1282 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1283 breakpoint
->length
= 2;
1286 if ((breakpoint
->length
!= 2)) {
1287 LOG_INFO("only breakpoints of two bytes length supported");
1288 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1291 if (breakpoint
->type
== BKPT_HARD
)
1292 cortex_m
->fp_code_available
--;
1294 return cortex_m_set_breakpoint(target
, breakpoint
);
1297 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1299 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1301 /* REVISIT why check? FBP can be updated with core running ... */
1302 if (target
->state
!= TARGET_HALTED
) {
1303 LOG_WARNING("target not halted");
1304 return ERROR_TARGET_NOT_HALTED
;
1307 if (cortex_m
->auto_bp_type
)
1308 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1310 if (breakpoint
->set
)
1311 cortex_m_unset_breakpoint(target
, breakpoint
);
1313 if (breakpoint
->type
== BKPT_HARD
)
1314 cortex_m
->fp_code_available
++;
1319 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1322 uint32_t mask
, temp
;
1323 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1325 /* watchpoint params were validated earlier */
1327 temp
= watchpoint
->length
;
1334 /* REVISIT Don't fully trust these "not used" records ... users
1335 * may set up breakpoints by hand, e.g. dual-address data value
1336 * watchpoint using comparator #1; comparator #0 matching cycle
1337 * count; send data trace info through ITM and TPIU; etc
1339 struct cortex_m_dwt_comparator
*comparator
;
1341 for (comparator
= cortex_m
->dwt_comparator_list
;
1342 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1343 comparator
++, dwt_num
++)
1345 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1346 LOG_ERROR("Can not find free DWT Comparator");
1349 comparator
->used
= 1;
1350 watchpoint
->set
= dwt_num
+ 1;
1352 comparator
->comp
= watchpoint
->address
;
1353 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1356 comparator
->mask
= mask
;
1357 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1360 switch (watchpoint
->rw
) {
1362 comparator
->function
= 5;
1365 comparator
->function
= 6;
1368 comparator
->function
= 7;
1371 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1372 comparator
->function
);
1374 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1375 watchpoint
->unique_id
, dwt_num
,
1376 (unsigned) comparator
->comp
,
1377 (unsigned) comparator
->mask
,
1378 (unsigned) comparator
->function
);
1382 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1384 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1385 struct cortex_m_dwt_comparator
*comparator
;
1388 if (!watchpoint
->set
) {
1389 LOG_WARNING("watchpoint (wpid: %d) not set",
1390 watchpoint
->unique_id
);
1394 dwt_num
= watchpoint
->set
- 1;
1396 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1397 watchpoint
->unique_id
, dwt_num
,
1398 (unsigned) watchpoint
->address
);
1400 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1401 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1405 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1406 comparator
->used
= 0;
1407 comparator
->function
= 0;
1408 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1409 comparator
->function
);
1411 watchpoint
->set
= false;
1416 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1418 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1420 if (cortex_m
->dwt_comp_available
< 1) {
1421 LOG_DEBUG("no comparators?");
1422 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1425 /* hardware doesn't support data value masking */
1426 if (watchpoint
->mask
!= ~(uint32_t)0) {
1427 LOG_DEBUG("watchpoint value masks not supported");
1428 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1431 /* hardware allows address masks of up to 32K */
1434 for (mask
= 0; mask
< 16; mask
++) {
1435 if ((1u << mask
) == watchpoint
->length
)
1439 LOG_DEBUG("unsupported watchpoint length");
1440 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1442 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1443 LOG_DEBUG("watchpoint address is unaligned");
1444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1447 /* Caller doesn't seem to be able to describe watching for data
1448 * values of zero; that flags "no value".
1450 * REVISIT This DWT may well be able to watch for specific data
1451 * values. Requires comparator #1 to set DATAVMATCH and match
1452 * the data, and another comparator (DATAVADDR0) matching addr.
1454 if (watchpoint
->value
) {
1455 LOG_DEBUG("data value watchpoint not YET supported");
1456 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1459 cortex_m
->dwt_comp_available
--;
1460 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1465 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1467 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1469 /* REVISIT why check? DWT can be updated with core running ... */
1470 if (target
->state
!= TARGET_HALTED
) {
1471 LOG_WARNING("target not halted");
1472 return ERROR_TARGET_NOT_HALTED
;
1475 if (watchpoint
->set
)
1476 cortex_m_unset_watchpoint(target
, watchpoint
);
1478 cortex_m
->dwt_comp_available
++;
1479 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1484 void cortex_m_enable_watchpoints(struct target
*target
)
1486 struct watchpoint
*watchpoint
= target
->watchpoints
;
1488 /* set any pending watchpoints */
1489 while (watchpoint
) {
1490 if (!watchpoint
->set
)
1491 cortex_m_set_watchpoint(target
, watchpoint
);
1492 watchpoint
= watchpoint
->next
;
1496 static int cortex_m_load_core_reg_u32(struct target
*target
,
1497 uint32_t num
, uint32_t *value
)
1501 /* NOTE: we "know" here that the register identifiers used
1502 * in the v7m header match the Cortex-M3 Debug Core Register
1503 * Selector values for R0..R15, xPSR, MSP, and PSP.
1507 /* read a normal core register */
1508 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1510 if (retval
!= ERROR_OK
) {
1511 LOG_ERROR("JTAG failure %i", retval
);
1512 return ERROR_JTAG_DEVICE_ERROR
;
1514 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1518 /* Floating-point Status and Registers */
1519 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1520 if (retval
!= ERROR_OK
)
1522 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1523 if (retval
!= ERROR_OK
)
1525 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1528 case ARMV7M_S0
... ARMV7M_S31
:
1529 /* Floating-point Status and Registers */
1530 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1531 if (retval
!= ERROR_OK
)
1533 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1534 if (retval
!= ERROR_OK
)
1536 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1537 (int)(num
- ARMV7M_S0
), *value
);
1540 case ARMV7M_PRIMASK
:
1541 case ARMV7M_BASEPRI
:
1542 case ARMV7M_FAULTMASK
:
1543 case ARMV7M_CONTROL
:
1544 /* Cortex-M3 packages these four registers as bitfields
1545 * in one Debug Core register. So say r0 and r2 docs;
1546 * it was removed from r1 docs, but still works.
1548 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1551 case ARMV7M_PRIMASK
:
1552 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1555 case ARMV7M_BASEPRI
:
1556 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1559 case ARMV7M_FAULTMASK
:
1560 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1563 case ARMV7M_CONTROL
:
1564 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1568 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1572 return ERROR_COMMAND_SYNTAX_ERROR
;
1578 static int cortex_m_store_core_reg_u32(struct target
*target
,
1579 uint32_t num
, uint32_t value
)
1583 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1585 /* NOTE: we "know" here that the register identifiers used
1586 * in the v7m header match the Cortex-M3 Debug Core Register
1587 * Selector values for R0..R15, xPSR, MSP, and PSP.
1591 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1592 if (retval
!= ERROR_OK
) {
1595 LOG_ERROR("JTAG failure");
1596 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1597 r
->dirty
= r
->valid
;
1598 return ERROR_JTAG_DEVICE_ERROR
;
1600 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1604 /* Floating-point Status and Registers */
1605 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1606 if (retval
!= ERROR_OK
)
1608 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1609 if (retval
!= ERROR_OK
)
1611 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1614 case ARMV7M_S0
... ARMV7M_S31
:
1615 /* Floating-point Status and Registers */
1616 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1617 if (retval
!= ERROR_OK
)
1619 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1620 if (retval
!= ERROR_OK
)
1622 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1623 (int)(num
- ARMV7M_S0
), value
);
1626 case ARMV7M_PRIMASK
:
1627 case ARMV7M_BASEPRI
:
1628 case ARMV7M_FAULTMASK
:
1629 case ARMV7M_CONTROL
:
1630 /* Cortex-M3 packages these four registers as bitfields
1631 * in one Debug Core register. So say r0 and r2 docs;
1632 * it was removed from r1 docs, but still works.
1634 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1637 case ARMV7M_PRIMASK
:
1638 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1641 case ARMV7M_BASEPRI
:
1642 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1645 case ARMV7M_FAULTMASK
:
1646 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1649 case ARMV7M_CONTROL
:
1650 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1654 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1656 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1660 return ERROR_COMMAND_SYNTAX_ERROR
;
1666 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
1667 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1669 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1671 if (armv7m
->arm
.is_armv6m
) {
1672 /* armv6m does not handle unaligned memory access */
1673 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1674 return ERROR_TARGET_UNALIGNED_ACCESS
;
1677 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1680 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
1681 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1683 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1685 if (armv7m
->arm
.is_armv6m
) {
1686 /* armv6m does not handle unaligned memory access */
1687 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1688 return ERROR_TARGET_UNALIGNED_ACCESS
;
1691 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1694 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1695 struct target
*target
)
1697 armv7m_build_reg_cache(target
);
1698 arm_semihosting_init(target
);
1702 void cortex_m_deinit_target(struct target
*target
)
1704 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1706 free(cortex_m
->fp_comparator_list
);
1708 cortex_m_dwt_free(target
);
1709 armv7m_free_reg_cache(target
);
1711 free(target
->private_config
);
1715 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1716 * on r/w if the core is not running, and clear on resume or reset ... or
1717 * at least, in a post_restore_context() method.
1720 struct dwt_reg_state
{
1721 struct target
*target
;
1723 uint8_t value
[4]; /* scratch/cache */
1726 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1728 struct dwt_reg_state
*state
= reg
->arch_info
;
1731 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1732 if (retval
!= ERROR_OK
)
1735 buf_set_u32(state
->value
, 0, 32, tmp
);
1739 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1741 struct dwt_reg_state
*state
= reg
->arch_info
;
1743 return target_write_u32(state
->target
, state
->addr
,
1744 buf_get_u32(buf
, 0, reg
->size
));
1753 static struct dwt_reg dwt_base_regs
[] = {
1754 { DWT_CTRL
, "dwt_ctrl", 32, },
1755 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1756 * increments while the core is asleep.
1758 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1759 /* plus some 8 bit counters, useful for profiling with TPIU */
1762 static struct dwt_reg dwt_comp
[] = {
1763 #define DWT_COMPARATOR(i) \
1764 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1765 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1766 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1771 #undef DWT_COMPARATOR
1774 static const struct reg_arch_type dwt_reg_type
= {
1775 .get
= cortex_m_dwt_get_reg
,
1776 .set
= cortex_m_dwt_set_reg
,
1779 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1781 struct dwt_reg_state
*state
;
1783 state
= calloc(1, sizeof *state
);
1786 state
->addr
= d
->addr
;
1791 r
->value
= state
->value
;
1792 r
->arch_info
= state
;
1793 r
->type
= &dwt_reg_type
;
1796 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1799 struct reg_cache
*cache
;
1800 struct cortex_m_dwt_comparator
*comparator
;
1803 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1805 LOG_DEBUG("no DWT");
1809 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1810 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
1811 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
1812 sizeof(struct cortex_m_dwt_comparator
));
1813 if (!cm
->dwt_comparator_list
) {
1815 cm
->dwt_num_comp
= 0;
1816 LOG_ERROR("out of mem");
1820 cache
= calloc(1, sizeof *cache
);
1823 free(cm
->dwt_comparator_list
);
1826 cache
->name
= "Cortex-M DWT registers";
1827 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
1828 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1829 if (!cache
->reg_list
) {
1834 for (reg
= 0; reg
< 2; reg
++)
1835 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1836 dwt_base_regs
+ reg
);
1838 comparator
= cm
->dwt_comparator_list
;
1839 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
1842 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1843 for (j
= 0; j
< 3; j
++, reg
++)
1844 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1845 dwt_comp
+ 3 * i
+ j
);
1847 /* make sure we clear any watchpoints enabled on the target */
1848 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1851 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1852 cm
->dwt_cache
= cache
;
1854 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1855 dwtcr
, cm
->dwt_num_comp
,
1856 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1858 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1859 * implement single-address data value watchpoints ... so we
1860 * won't need to check it later, when asked to set one up.
1864 static void cortex_m_dwt_free(struct target
*target
)
1866 struct cortex_m_common
*cm
= target_to_cm(target
);
1867 struct reg_cache
*cache
= cm
->dwt_cache
;
1869 free(cm
->dwt_comparator_list
);
1870 cm
->dwt_comparator_list
= NULL
;
1871 cm
->dwt_num_comp
= 0;
1874 register_unlink_cache(&target
->reg_cache
, cache
);
1876 if (cache
->reg_list
) {
1877 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
1878 free(cache
->reg_list
[i
].arch_info
);
1879 free(cache
->reg_list
);
1883 cm
->dwt_cache
= NULL
;
1886 #define MVFR0 0xe000ef40
1887 #define MVFR1 0xe000ef44
1889 #define MVFR0_DEFAULT_M4 0x10110021
1890 #define MVFR1_DEFAULT_M4 0x11000011
1892 #define MVFR0_DEFAULT_M7_SP 0x10110021
1893 #define MVFR0_DEFAULT_M7_DP 0x10110221
1894 #define MVFR1_DEFAULT_M7_SP 0x11000011
1895 #define MVFR1_DEFAULT_M7_DP 0x12000011
1897 int cortex_m_examine(struct target
*target
)
1900 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1902 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1903 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
1904 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1906 /* stlink shares the examine handler but does not support
1908 if (!armv7m
->stlink
) {
1909 retval
= dap_dp_init(swjdp
);
1910 if (retval
!= ERROR_OK
) {
1911 LOG_ERROR("Could not initialize the debug port");
1915 if (cortex_m
->apsel
< 0) {
1916 /* Search for the MEM-AP */
1917 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7m
->debug_ap
);
1918 if (retval
!= ERROR_OK
) {
1919 LOG_ERROR("Could not find MEM-AP to control the core");
1923 armv7m
->debug_ap
= dap_ap(swjdp
, cortex_m
->apsel
);
1926 /* Leave (only) generic DAP stuff for debugport_init(); */
1927 armv7m
->debug_ap
->memaccess_tck
= 8;
1929 retval
= mem_ap_init(armv7m
->debug_ap
);
1930 if (retval
!= ERROR_OK
)
1934 if (!target_was_examined(target
)) {
1935 target_set_examined(target
);
1937 /* Read from Device Identification Registers */
1938 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1939 if (retval
!= ERROR_OK
)
1943 i
= (cpuid
>> 4) & 0xf;
1945 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1946 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1949 rev
= (cpuid
>> 20) & 0xf;
1950 patch
= (cpuid
>> 0) & 0xf;
1951 if ((rev
== 0) && (patch
< 2))
1952 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
1954 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1957 target_read_u32(target
, MVFR0
, &mvfr0
);
1958 target_read_u32(target
, MVFR1
, &mvfr1
);
1960 /* test for floating point feature on Cortex-M4 */
1961 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1962 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1963 armv7m
->fp_feature
= FPv4_SP
;
1965 } else if (i
== 7) {
1966 target_read_u32(target
, MVFR0
, &mvfr0
);
1967 target_read_u32(target
, MVFR1
, &mvfr1
);
1969 /* test for floating point features on Cortex-M7 */
1970 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
1971 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
1972 armv7m
->fp_feature
= FPv5_SP
;
1973 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
1974 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
1975 armv7m
->fp_feature
= FPv5_DP
;
1977 } else if (i
== 0) {
1978 /* Cortex-M0 does not support unaligned memory access */
1979 armv7m
->arm
.is_armv6m
= true;
1982 if (armv7m
->fp_feature
== FP_NONE
&&
1983 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
1984 /* free unavailable FPU registers */
1987 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
1988 idx
< armv7m
->arm
.core_cache
->num_regs
;
1990 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
1991 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
1992 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
1994 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
1997 if (!armv7m
->stlink
) {
1998 if (i
== 3 || i
== 4)
1999 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2000 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2001 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2003 /* Cortex-M7 has only 1024 bytes autoincrement range */
2004 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
2007 /* Configure trace modules */
2008 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2009 if (retval
!= ERROR_OK
)
2012 if (armv7m
->trace_config
.config_type
!= DISABLED
) {
2013 armv7m_trace_tpiu_config(target
);
2014 armv7m_trace_itm_config(target
);
2017 /* NOTE: FPB and DWT are both optional. */
2020 target_read_u32(target
, FP_CTRL
, &fpcr
);
2021 cortex_m
->auto_bp_type
= 1;
2022 /* bits [14:12] and [7:4] */
2023 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2024 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2025 cortex_m
->fp_code_available
= cortex_m
->fp_num_code
;
2026 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2027 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2028 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2029 free(cortex_m
->fp_comparator_list
);
2030 cortex_m
->fp_comparator_list
= calloc(
2031 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2032 sizeof(struct cortex_m_fp_comparator
));
2033 cortex_m
->fpb_enabled
= fpcr
& 1;
2034 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2035 cortex_m
->fp_comparator_list
[i
].type
=
2036 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2037 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2039 /* make sure we clear any breakpoints enabled on the target */
2040 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2042 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2044 cortex_m
->fp_num_code
,
2045 cortex_m
->fp_num_lit
);
2048 cortex_m_dwt_free(target
);
2049 cortex_m_dwt_setup(cortex_m
, target
);
2051 /* These hardware breakpoints only work for code in flash! */
2052 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2053 target_name(target
),
2054 cortex_m
->fp_num_code
,
2055 cortex_m
->dwt_num_comp
);
2061 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2063 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2068 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2069 if (retval
!= ERROR_OK
)
2072 dcrdr
= target_buffer_get_u16(target
, buf
);
2073 *ctrl
= (uint8_t)dcrdr
;
2074 *value
= (uint8_t)(dcrdr
>> 8);
2076 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2078 /* write ack back to software dcc register
2079 * signify we have read data */
2080 if (dcrdr
& (1 << 0)) {
2081 target_buffer_set_u16(target
, buf
, 0);
2082 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2083 if (retval
!= ERROR_OK
)
2090 static int cortex_m_target_request_data(struct target
*target
,
2091 uint32_t size
, uint8_t *buffer
)
2097 for (i
= 0; i
< (size
* 4); i
++) {
2098 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2099 if (retval
!= ERROR_OK
)
2107 static int cortex_m_handle_target_request(void *priv
)
2109 struct target
*target
= priv
;
2110 if (!target_was_examined(target
))
2113 if (!target
->dbg_msg_enabled
)
2116 if (target
->state
== TARGET_RUNNING
) {
2121 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2122 if (retval
!= ERROR_OK
)
2125 /* check if we have data */
2126 if (ctrl
& (1 << 0)) {
2129 /* we assume target is quick enough */
2131 for (int i
= 1; i
<= 3; i
++) {
2132 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2133 if (retval
!= ERROR_OK
)
2135 request
|= ((uint32_t)data
<< (i
* 8));
2137 target_request(target
, request
);
2144 static int cortex_m_init_arch_info(struct target
*target
,
2145 struct cortex_m_common
*cortex_m
, struct jtag_tap
*tap
)
2147 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2149 armv7m_init_arch_info(target
, armv7m
);
2151 /* tap has no dap initialized */
2153 tap
->dap
= dap_init();
2155 /* Leave (only) generic DAP stuff for debugport_init() */
2156 tap
->dap
->tap
= tap
;
2159 /* default reset mode is to use srst if fitted
2160 * if not it will use CORTEX_M3_RESET_VECTRESET */
2161 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2163 armv7m
->arm
.dap
= tap
->dap
;
2165 /* register arch-specific functions */
2166 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2168 armv7m
->post_debug_entry
= NULL
;
2170 armv7m
->pre_restore_context
= NULL
;
2172 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2173 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2175 target_register_timer_callback(cortex_m_handle_target_request
, 1, 1, target
);
2180 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2182 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2184 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2185 cortex_m_init_arch_info(target
, cortex_m
, target
->tap
);
2187 if (target
->private_config
!= NULL
) {
2188 struct adiv5_private_config
*pc
=
2189 (struct adiv5_private_config
*)target
->private_config
;
2190 cortex_m
->apsel
= pc
->ap_num
;
2192 cortex_m
->apsel
= -1;
2197 /*--------------------------------------------------------------------------*/
2199 static int cortex_m_verify_pointer(struct command_context
*cmd_ctx
,
2200 struct cortex_m_common
*cm
)
2202 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2203 command_print(cmd_ctx
, "target is not a Cortex-M");
2204 return ERROR_TARGET_INVALID
;
2210 * Only stuff below this line should need to verify that its target
2211 * is a Cortex-M3. Everything else should have indirected through the
2212 * cortexm3_target structure, which is only used with CM3 targets.
2215 static const struct {
2219 { "hard_err", VC_HARDERR
, },
2220 { "int_err", VC_INTERR
, },
2221 { "bus_err", VC_BUSERR
, },
2222 { "state_err", VC_STATERR
, },
2223 { "chk_err", VC_CHKERR
, },
2224 { "nocp_err", VC_NOCPERR
, },
2225 { "mm_err", VC_MMERR
, },
2226 { "reset", VC_CORERESET
, },
2229 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2231 struct target
*target
= get_current_target(CMD_CTX
);
2232 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2233 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2237 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2238 if (retval
!= ERROR_OK
)
2241 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2242 if (retval
!= ERROR_OK
)
2248 if (CMD_ARGC
== 1) {
2249 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2250 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2251 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2252 | VC_MMERR
| VC_CORERESET
;
2254 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2257 while (CMD_ARGC
-- > 0) {
2259 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2260 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2262 catch |= vec_ids
[i
].mask
;
2265 if (i
== ARRAY_SIZE(vec_ids
)) {
2266 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2267 return ERROR_COMMAND_SYNTAX_ERROR
;
2271 /* For now, armv7m->demcr only stores vector catch flags. */
2272 armv7m
->demcr
= catch;
2277 /* write, but don't assume it stuck (why not??) */
2278 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2279 if (retval
!= ERROR_OK
)
2281 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2282 if (retval
!= ERROR_OK
)
2285 /* FIXME be sure to clear DEMCR on clean server shutdown.
2286 * Otherwise the vector catch hardware could fire when there's
2287 * no debugger hooked up, causing much confusion...
2291 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2292 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2293 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2299 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2301 struct target
*target
= get_current_target(CMD_CTX
);
2302 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2305 static const Jim_Nvp nvp_maskisr_modes
[] = {
2306 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2307 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2308 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2309 { .name
= NULL
, .value
= -1 },
2314 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2315 if (retval
!= ERROR_OK
)
2318 if (target
->state
!= TARGET_HALTED
) {
2319 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2324 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2325 if (n
->name
== NULL
)
2326 return ERROR_COMMAND_SYNTAX_ERROR
;
2327 cortex_m
->isrmasking_mode
= n
->value
;
2330 if (cortex_m
->isrmasking_mode
== CORTEX_M_ISRMASK_ON
)
2331 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2333 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2336 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2337 command_print(CMD_CTX
, "cortex_m interrupt mask %s", n
->name
);
2342 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2344 struct target
*target
= get_current_target(CMD_CTX
);
2345 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2349 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2350 if (retval
!= ERROR_OK
)
2354 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2355 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2356 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2357 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2360 switch (cortex_m
->soft_reset_config
) {
2361 case CORTEX_M_RESET_SYSRESETREQ
:
2362 reset_config
= "sysresetreq";
2365 case CORTEX_M_RESET_VECTRESET
:
2366 reset_config
= "vectreset";
2370 reset_config
= "unknown";
2374 command_print(CMD_CTX
, "cortex_m reset_config %s", reset_config
);
2379 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2382 .handler
= handle_cortex_m_mask_interrupts_command
,
2383 .mode
= COMMAND_EXEC
,
2384 .help
= "mask cortex_m interrupts",
2385 .usage
= "['auto'|'on'|'off']",
2388 .name
= "vector_catch",
2389 .handler
= handle_cortex_m_vector_catch_command
,
2390 .mode
= COMMAND_EXEC
,
2391 .help
= "configure hardware vectors to trigger debug entry",
2392 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2395 .name
= "reset_config",
2396 .handler
= handle_cortex_m_reset_config_command
,
2397 .mode
= COMMAND_ANY
,
2398 .help
= "configure software reset handling",
2399 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2401 COMMAND_REGISTRATION_DONE
2403 static const struct command_registration cortex_m_command_handlers
[] = {
2405 .chain
= armv7m_command_handlers
,
2408 .chain
= armv7m_trace_command_handlers
,
2412 .mode
= COMMAND_EXEC
,
2413 .help
= "Cortex-M command group",
2415 .chain
= cortex_m_exec_command_handlers
,
2417 COMMAND_REGISTRATION_DONE
2420 struct target_type cortexm_target
= {
2422 .deprecated_name
= "cortex_m3",
2424 .poll
= cortex_m_poll
,
2425 .arch_state
= armv7m_arch_state
,
2427 .target_request_data
= cortex_m_target_request_data
,
2429 .halt
= cortex_m_halt
,
2430 .resume
= cortex_m_resume
,
2431 .step
= cortex_m_step
,
2433 .assert_reset
= cortex_m_assert_reset
,
2434 .deassert_reset
= cortex_m_deassert_reset
,
2435 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2437 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2439 .read_memory
= cortex_m_read_memory
,
2440 .write_memory
= cortex_m_write_memory
,
2441 .checksum_memory
= armv7m_checksum_memory
,
2442 .blank_check_memory
= armv7m_blank_check_memory
,
2444 .run_algorithm
= armv7m_run_algorithm
,
2445 .start_algorithm
= armv7m_start_algorithm
,
2446 .wait_algorithm
= armv7m_wait_algorithm
,
2448 .add_breakpoint
= cortex_m_add_breakpoint
,
2449 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2450 .add_watchpoint
= cortex_m_add_watchpoint
,
2451 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2453 .commands
= cortex_m_command_handlers
,
2454 .target_create
= cortex_m_target_create
,
2455 .target_jim_configure
= adiv5_jim_configure
,
2456 .init_target
= cortex_m_init_target
,
2457 .examine
= cortex_m_examine
,
2458 .deinit_target
= cortex_m_deinit_target
,
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