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target/cortex_m: Add support for AHB5-AP
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_set_maskints(struct target *target, bool mask)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
143 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
144 else
145 return ERROR_OK;
146 }
147
148 static int cortex_m_set_maskints_for_halt(struct target *target)
149 {
150 struct cortex_m_common *cortex_m = target_to_cm(target);
151 switch (cortex_m->isrmasking_mode) {
152 case CORTEX_M_ISRMASK_AUTO:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target, false);
155
156 case CORTEX_M_ISRMASK_OFF:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target, false);
159
160 case CORTEX_M_ISRMASK_ON:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target, true);
163
164 case CORTEX_M_ISRMASK_STEPONLY:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
168 }
169 return ERROR_OK;
170 }
171
172 static int cortex_m_set_maskints_for_run(struct target *target)
173 {
174 switch (target_to_cm(target)->isrmasking_mode) {
175 case CORTEX_M_ISRMASK_AUTO:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target, false);
178
179 case CORTEX_M_ISRMASK_OFF:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target, false);
182
183 case CORTEX_M_ISRMASK_ON:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target, true);
186
187 case CORTEX_M_ISRMASK_STEPONLY:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target, false);
190 }
191 return ERROR_OK;
192 }
193
194 static int cortex_m_set_maskints_for_step(struct target *target)
195 {
196 switch (target_to_cm(target)->isrmasking_mode) {
197 case CORTEX_M_ISRMASK_AUTO:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target, true);
200
201 case CORTEX_M_ISRMASK_OFF:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target, false);
204
205 case CORTEX_M_ISRMASK_ON:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target, true);
208
209 case CORTEX_M_ISRMASK_STEPONLY:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target, true);
212 }
213 return ERROR_OK;
214 }
215
216 static int cortex_m_clear_halt(struct target *target)
217 {
218 struct cortex_m_common *cortex_m = target_to_cm(target);
219 struct armv7m_common *armv7m = &cortex_m->armv7m;
220 int retval;
221
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
224
225 /* Read Debug Fault Status Register */
226 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Clear Debug Fault Status */
231 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
232 if (retval != ERROR_OK)
233 return retval;
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
235
236 return ERROR_OK;
237 }
238
239 static int cortex_m_single_step_core(struct target *target)
240 {
241 struct cortex_m_common *cortex_m = target_to_cm(target);
242 struct armv7m_common *armv7m = &cortex_m->armv7m;
243 int retval;
244
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
248 */
249 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
250 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
251 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
252 if (retval != ERROR_OK)
253 return retval;
254 }
255 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
256 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
257 if (retval != ERROR_OK)
258 return retval;
259 LOG_DEBUG(" ");
260
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target);
263
264 return ERROR_OK;
265 }
266
267 static int cortex_m_enable_fpb(struct target *target)
268 {
269 int retval = target_write_u32(target, FP_CTRL, 3);
270 if (retval != ERROR_OK)
271 return retval;
272
273 /* check the fpb is actually enabled */
274 uint32_t fpctrl;
275 retval = target_read_u32(target, FP_CTRL, &fpctrl);
276 if (retval != ERROR_OK)
277 return retval;
278
279 if (fpctrl & 1)
280 return ERROR_OK;
281
282 return ERROR_FAIL;
283 }
284
285 static int cortex_m_endreset_event(struct target *target)
286 {
287 int i;
288 int retval;
289 uint32_t dcb_demcr;
290 struct cortex_m_common *cortex_m = target_to_cm(target);
291 struct armv7m_common *armv7m = &cortex_m->armv7m;
292 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
293 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
294 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
295
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
298 if (retval != ERROR_OK)
299 return retval;
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
301
302 /* this register is used for emulated dcc channel */
303 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* Enable debug requests */
308 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
309 if (retval != ERROR_OK)
310 return retval;
311 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
312 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
313 if (retval != ERROR_OK)
314 return retval;
315 }
316
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target);
319
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
322 *
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
326 */
327 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
328 if (retval != ERROR_OK)
329 return retval;
330
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
333 */
334
335 /* Enable FPB */
336 retval = cortex_m_enable_fpb(target);
337 if (retval != ERROR_OK) {
338 LOG_ERROR("Failed to enable the FPB");
339 return retval;
340 }
341
342 cortex_m->fpb_enabled = true;
343
344 /* Restore FPB registers */
345 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
346 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350
351 /* Restore DWT registers */
352 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
353 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
354 dwt_list[i].comp);
355 if (retval != ERROR_OK)
356 return retval;
357 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
358 dwt_list[i].mask);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
362 dwt_list[i].function);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366 retval = dap_run(swjdp);
367 if (retval != ERROR_OK)
368 return retval;
369
370 register_cache_invalidate(armv7m->arm.core_cache);
371
372 /* make sure we have latest dhcsr flags */
373 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
374
375 return retval;
376 }
377
378 static int cortex_m_examine_debug_reason(struct target *target)
379 {
380 struct cortex_m_common *cortex_m = target_to_cm(target);
381
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
384
385 if ((target->debug_reason != DBG_REASON_DBGRQ)
386 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
387 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
388 target->debug_reason = DBG_REASON_BREAKPOINT;
389 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
390 target->debug_reason = DBG_REASON_WPTANDBKPT;
391 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
392 target->debug_reason = DBG_REASON_WATCHPOINT;
393 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
394 target->debug_reason = DBG_REASON_BREAKPOINT;
395 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
396 target->debug_reason = DBG_REASON_DBGRQ;
397 else /* HALTED */
398 target->debug_reason = DBG_REASON_UNDEFINED;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int cortex_m_examine_exception_reason(struct target *target)
405 {
406 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
407 struct armv7m_common *armv7m = target_to_armv7m(target);
408 struct adiv5_dap *swjdp = armv7m->arm.dap;
409 int retval;
410
411 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
412 if (retval != ERROR_OK)
413 return retval;
414 switch (armv7m->exception_number) {
415 case 2: /* NMI */
416 break;
417 case 3: /* Hard Fault */
418 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
419 if (retval != ERROR_OK)
420 return retval;
421 if (except_sr & 0x40000000) {
422 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
423 if (retval != ERROR_OK)
424 return retval;
425 }
426 break;
427 case 4: /* Memory Management */
428 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
432 if (retval != ERROR_OK)
433 return retval;
434 break;
435 case 5: /* Bus Fault */
436 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
440 if (retval != ERROR_OK)
441 return retval;
442 break;
443 case 6: /* Usage Fault */
444 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
445 if (retval != ERROR_OK)
446 return retval;
447 break;
448 case 11: /* SVCall */
449 break;
450 case 12: /* Debug Monitor */
451 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
452 if (retval != ERROR_OK)
453 return retval;
454 break;
455 case 14: /* PendSV */
456 break;
457 case 15: /* SysTick */
458 break;
459 default:
460 except_sr = 0;
461 break;
462 }
463 retval = dap_run(swjdp);
464 if (retval == ERROR_OK)
465 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
466 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
467 armv7m_exception_string(armv7m->exception_number),
468 shcsr, except_sr, cfsr, except_ar);
469 return retval;
470 }
471
472 static int cortex_m_debug_entry(struct target *target)
473 {
474 int i;
475 uint32_t xPSR;
476 int retval;
477 struct cortex_m_common *cortex_m = target_to_cm(target);
478 struct armv7m_common *armv7m = &cortex_m->armv7m;
479 struct arm *arm = &armv7m->arm;
480 struct reg *r;
481
482 LOG_DEBUG(" ");
483
484 /* Do this really early to minimize the window where the MASKINTS erratum
485 * can pile up pending interrupts. */
486 cortex_m_set_maskints_for_halt(target);
487
488 cortex_m_clear_halt(target);
489 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
490 if (retval != ERROR_OK)
491 return retval;
492
493 retval = armv7m->examine_debug_reason(target);
494 if (retval != ERROR_OK)
495 return retval;
496
497 /* Examine target state and mode
498 * First load register accessible through core debug port */
499 int num_regs = arm->core_cache->num_regs;
500
501 for (i = 0; i < num_regs; i++) {
502 r = &armv7m->arm.core_cache->reg_list[i];
503 if (!r->valid)
504 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
505 }
506
507 r = arm->cpsr;
508 xPSR = buf_get_u32(r->value, 0, 32);
509
510 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
511 if (xPSR & 0xf00) {
512 r->dirty = r->valid;
513 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
514 }
515
516 /* Are we in an exception handler */
517 if (xPSR & 0x1FF) {
518 armv7m->exception_number = (xPSR & 0x1FF);
519
520 arm->core_mode = ARM_MODE_HANDLER;
521 arm->map = armv7m_msp_reg_map;
522 } else {
523 unsigned control = buf_get_u32(arm->core_cache
524 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
525
526 /* is this thread privileged? */
527 arm->core_mode = control & 1
528 ? ARM_MODE_USER_THREAD
529 : ARM_MODE_THREAD;
530
531 /* which stack is it using? */
532 if (control & 2)
533 arm->map = armv7m_psp_reg_map;
534 else
535 arm->map = armv7m_msp_reg_map;
536
537 armv7m->exception_number = 0;
538 }
539
540 if (armv7m->exception_number)
541 cortex_m_examine_exception_reason(target);
542
543 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
544 arm_mode_name(arm->core_mode),
545 buf_get_u32(arm->pc->value, 0, 32),
546 target_state_name(target));
547
548 if (armv7m->post_debug_entry) {
549 retval = armv7m->post_debug_entry(target);
550 if (retval != ERROR_OK)
551 return retval;
552 }
553
554 return ERROR_OK;
555 }
556
557 static int cortex_m_poll(struct target *target)
558 {
559 int detected_failure = ERROR_OK;
560 int retval = ERROR_OK;
561 enum target_state prev_target_state = target->state;
562 struct cortex_m_common *cortex_m = target_to_cm(target);
563 struct armv7m_common *armv7m = &cortex_m->armv7m;
564
565 /* Read from Debug Halting Control and Status Register */
566 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
567 if (retval != ERROR_OK) {
568 target->state = TARGET_UNKNOWN;
569 return retval;
570 }
571
572 /* Recover from lockup. See ARMv7-M architecture spec,
573 * section B1.5.15 "Unrecoverable exception cases".
574 */
575 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
576 LOG_ERROR("%s -- clearing lockup after double fault",
577 target_name(target));
578 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
579 target->debug_reason = DBG_REASON_DBGRQ;
580
581 /* We have to execute the rest (the "finally" equivalent, but
582 * still throw this exception again).
583 */
584 detected_failure = ERROR_FAIL;
585
586 /* refresh status bits */
587 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
588 if (retval != ERROR_OK)
589 return retval;
590 }
591
592 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
593 if (target->state != TARGET_RESET) {
594 target->state = TARGET_RESET;
595 LOG_INFO("%s: external reset detected", target_name(target));
596 }
597 return ERROR_OK;
598 }
599
600 if (target->state == TARGET_RESET) {
601 /* Cannot switch context while running so endreset is
602 * called with target->state == TARGET_RESET
603 */
604 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
605 cortex_m->dcb_dhcsr);
606 retval = cortex_m_endreset_event(target);
607 if (retval != ERROR_OK) {
608 target->state = TARGET_UNKNOWN;
609 return retval;
610 }
611 target->state = TARGET_RUNNING;
612 prev_target_state = TARGET_RUNNING;
613 }
614
615 if (cortex_m->dcb_dhcsr & S_HALT) {
616 target->state = TARGET_HALTED;
617
618 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
619 retval = cortex_m_debug_entry(target);
620 if (retval != ERROR_OK)
621 return retval;
622
623 if (arm_semihosting(target, &retval) != 0)
624 return retval;
625
626 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
627 }
628 if (prev_target_state == TARGET_DEBUG_RUNNING) {
629 LOG_DEBUG(" ");
630 retval = cortex_m_debug_entry(target);
631 if (retval != ERROR_OK)
632 return retval;
633
634 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
635 }
636 }
637
638 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
639 * How best to model low power modes?
640 */
641
642 if (target->state == TARGET_UNKNOWN) {
643 /* check if processor is retiring instructions */
644 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
645 target->state = TARGET_RUNNING;
646 retval = ERROR_OK;
647 }
648 }
649
650 /* Check that target is truly halted, since the target could be resumed externally */
651 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
652 /* registers are now invalid */
653 register_cache_invalidate(armv7m->arm.core_cache);
654
655 target->state = TARGET_RUNNING;
656 LOG_WARNING("%s: external resume detected", target_name(target));
657 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
658 retval = ERROR_OK;
659 }
660
661 /* Did we detect a failure condition that we cleared? */
662 if (detected_failure != ERROR_OK)
663 retval = detected_failure;
664 return retval;
665 }
666
667 static int cortex_m_halt(struct target *target)
668 {
669 LOG_DEBUG("target->state: %s",
670 target_state_name(target));
671
672 if (target->state == TARGET_HALTED) {
673 LOG_DEBUG("target was already halted");
674 return ERROR_OK;
675 }
676
677 if (target->state == TARGET_UNKNOWN)
678 LOG_WARNING("target was in unknown state when halt was requested");
679
680 if (target->state == TARGET_RESET) {
681 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
682 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
683 return ERROR_TARGET_FAILURE;
684 } else {
685 /* we came here in a reset_halt or reset_init sequence
686 * debug entry was already prepared in cortex_m3_assert_reset()
687 */
688 target->debug_reason = DBG_REASON_DBGRQ;
689
690 return ERROR_OK;
691 }
692 }
693
694 /* Write to Debug Halting Control and Status Register */
695 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
696
697 /* Do this really early to minimize the window where the MASKINTS erratum
698 * can pile up pending interrupts. */
699 cortex_m_set_maskints_for_halt(target);
700
701 target->debug_reason = DBG_REASON_DBGRQ;
702
703 return ERROR_OK;
704 }
705
706 static int cortex_m_soft_reset_halt(struct target *target)
707 {
708 struct cortex_m_common *cortex_m = target_to_cm(target);
709 struct armv7m_common *armv7m = &cortex_m->armv7m;
710 uint32_t dcb_dhcsr = 0;
711 int retval, timeout = 0;
712
713 /* soft_reset_halt is deprecated on cortex_m as the same functionality
714 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
715 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
716 * core, not the peripherals */
717 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
718
719 /* Enter debug state on reset; restore DEMCR in endreset_event() */
720 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
721 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
722 if (retval != ERROR_OK)
723 return retval;
724
725 /* Request a core-only reset */
726 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
727 AIRCR_VECTKEY | AIRCR_VECTRESET);
728 if (retval != ERROR_OK)
729 return retval;
730 target->state = TARGET_RESET;
731
732 /* registers are now invalid */
733 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
734
735 while (timeout < 100) {
736 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
737 if (retval == ERROR_OK) {
738 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
739 &cortex_m->nvic_dfsr);
740 if (retval != ERROR_OK)
741 return retval;
742 if ((dcb_dhcsr & S_HALT)
743 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
744 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
745 "DFSR 0x%08x",
746 (unsigned) dcb_dhcsr,
747 (unsigned) cortex_m->nvic_dfsr);
748 cortex_m_poll(target);
749 /* FIXME restore user's vector catch config */
750 return ERROR_OK;
751 } else
752 LOG_DEBUG("waiting for system reset-halt, "
753 "DHCSR 0x%08x, %d ms",
754 (unsigned) dcb_dhcsr, timeout);
755 }
756 timeout++;
757 alive_sleep(1);
758 }
759
760 return ERROR_OK;
761 }
762
763 void cortex_m_enable_breakpoints(struct target *target)
764 {
765 struct breakpoint *breakpoint = target->breakpoints;
766
767 /* set any pending breakpoints */
768 while (breakpoint) {
769 if (!breakpoint->set)
770 cortex_m_set_breakpoint(target, breakpoint);
771 breakpoint = breakpoint->next;
772 }
773 }
774
775 static int cortex_m_resume(struct target *target, int current,
776 target_addr_t address, int handle_breakpoints, int debug_execution)
777 {
778 struct armv7m_common *armv7m = target_to_armv7m(target);
779 struct breakpoint *breakpoint = NULL;
780 uint32_t resume_pc;
781 struct reg *r;
782
783 if (target->state != TARGET_HALTED) {
784 LOG_WARNING("target not halted");
785 return ERROR_TARGET_NOT_HALTED;
786 }
787
788 if (!debug_execution) {
789 target_free_all_working_areas(target);
790 cortex_m_enable_breakpoints(target);
791 cortex_m_enable_watchpoints(target);
792 }
793
794 if (debug_execution) {
795 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
796
797 /* Disable interrupts */
798 /* We disable interrupts in the PRIMASK register instead of
799 * masking with C_MASKINTS. This is probably the same issue
800 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
801 * in parallel with disabled interrupts can cause local faults
802 * to not be taken.
803 *
804 * REVISIT this clearly breaks non-debug execution, since the
805 * PRIMASK register state isn't saved/restored... workaround
806 * by never resuming app code after debug execution.
807 */
808 buf_set_u32(r->value, 0, 1, 1);
809 r->dirty = true;
810 r->valid = true;
811
812 /* Make sure we are in Thumb mode */
813 r = armv7m->arm.cpsr;
814 buf_set_u32(r->value, 24, 1, 1);
815 r->dirty = true;
816 r->valid = true;
817 }
818
819 /* current = 1: continue on current pc, otherwise continue at <address> */
820 r = armv7m->arm.pc;
821 if (!current) {
822 buf_set_u32(r->value, 0, 32, address);
823 r->dirty = true;
824 r->valid = true;
825 }
826
827 /* if we halted last time due to a bkpt instruction
828 * then we have to manually step over it, otherwise
829 * the core will break again */
830
831 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
832 && !debug_execution)
833 armv7m_maybe_skip_bkpt_inst(target, NULL);
834
835 resume_pc = buf_get_u32(r->value, 0, 32);
836
837 armv7m_restore_context(target);
838
839 /* the front-end may request us not to handle breakpoints */
840 if (handle_breakpoints) {
841 /* Single step past breakpoint at current address */
842 breakpoint = breakpoint_find(target, resume_pc);
843 if (breakpoint) {
844 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
845 breakpoint->address,
846 breakpoint->unique_id);
847 cortex_m_unset_breakpoint(target, breakpoint);
848 cortex_m_single_step_core(target);
849 cortex_m_set_breakpoint(target, breakpoint);
850 }
851 }
852
853 /* Restart core */
854 cortex_m_set_maskints_for_run(target);
855 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
856
857 target->debug_reason = DBG_REASON_NOTHALTED;
858
859 /* registers are now invalid */
860 register_cache_invalidate(armv7m->arm.core_cache);
861
862 if (!debug_execution) {
863 target->state = TARGET_RUNNING;
864 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
865 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
866 } else {
867 target->state = TARGET_DEBUG_RUNNING;
868 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
869 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
870 }
871
872 return ERROR_OK;
873 }
874
875 /* int irqstepcount = 0; */
876 static int cortex_m_step(struct target *target, int current,
877 target_addr_t address, int handle_breakpoints)
878 {
879 struct cortex_m_common *cortex_m = target_to_cm(target);
880 struct armv7m_common *armv7m = &cortex_m->armv7m;
881 struct breakpoint *breakpoint = NULL;
882 struct reg *pc = armv7m->arm.pc;
883 bool bkpt_inst_found = false;
884 int retval;
885 bool isr_timed_out = false;
886
887 if (target->state != TARGET_HALTED) {
888 LOG_WARNING("target not halted");
889 return ERROR_TARGET_NOT_HALTED;
890 }
891
892 /* current = 1: continue on current pc, otherwise continue at <address> */
893 if (!current)
894 buf_set_u32(pc->value, 0, 32, address);
895
896 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
897
898 /* the front-end may request us not to handle breakpoints */
899 if (handle_breakpoints) {
900 breakpoint = breakpoint_find(target, pc_value);
901 if (breakpoint)
902 cortex_m_unset_breakpoint(target, breakpoint);
903 }
904
905 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
906
907 target->debug_reason = DBG_REASON_SINGLESTEP;
908
909 armv7m_restore_context(target);
910
911 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
912
913 /* if no bkpt instruction is found at pc then we can perform
914 * a normal step, otherwise we have to manually step over the bkpt
915 * instruction - as such simulate a step */
916 if (bkpt_inst_found == false) {
917 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO)) {
918 /* Automatic ISR masking mode off: Just step over the next
919 * instruction, with interrupts on or off as appropriate. */
920 cortex_m_set_maskints_for_step(target);
921 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
922 } else {
923 /* Process interrupts during stepping in a way they don't interfere
924 * debugging.
925 *
926 * Principle:
927 *
928 * Set a temporary break point at the current pc and let the core run
929 * with interrupts enabled. Pending interrupts get served and we run
930 * into the breakpoint again afterwards. Then we step over the next
931 * instruction with interrupts disabled.
932 *
933 * If the pending interrupts don't complete within time, we leave the
934 * core running. This may happen if the interrupts trigger faster
935 * than the core can process them or the handler doesn't return.
936 *
937 * If no more breakpoints are available we simply do a step with
938 * interrupts enabled.
939 *
940 */
941
942 /* 2012-09-29 ph
943 *
944 * If a break point is already set on the lower half word then a break point on
945 * the upper half word will not break again when the core is restarted. So we
946 * just step over the instruction with interrupts disabled.
947 *
948 * The documentation has no information about this, it was found by observation
949 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
950 * suffer from this problem.
951 *
952 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
953 * address has it always cleared. The former is done to indicate thumb mode
954 * to gdb.
955 *
956 */
957 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
958 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
959 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
960 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
961 /* Re-enable interrupts if appropriate */
962 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
963 cortex_m_set_maskints_for_halt(target);
964 }
965 else {
966
967 /* Set a temporary break point */
968 if (breakpoint) {
969 retval = cortex_m_set_breakpoint(target, breakpoint);
970 } else {
971 enum breakpoint_type type = BKPT_HARD;
972 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
973 /* FPB rev.1 cannot handle such addr, try BKPT instr */
974 type = BKPT_SOFT;
975 }
976 retval = breakpoint_add(target, pc_value, 2, type);
977 }
978
979 bool tmp_bp_set = (retval == ERROR_OK);
980
981 /* No more breakpoints left, just do a step */
982 if (!tmp_bp_set) {
983 cortex_m_set_maskints_for_step(target);
984 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
985 /* Re-enable interrupts if appropriate */
986 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
987 cortex_m_set_maskints_for_halt(target);
988 } else {
989 /* Start the core */
990 LOG_DEBUG("Starting core to serve pending interrupts");
991 int64_t t_start = timeval_ms();
992 cortex_m_set_maskints_for_run(target);
993 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
994
995 /* Wait for pending handlers to complete or timeout */
996 do {
997 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
998 DCB_DHCSR,
999 &cortex_m->dcb_dhcsr);
1000 if (retval != ERROR_OK) {
1001 target->state = TARGET_UNKNOWN;
1002 return retval;
1003 }
1004 isr_timed_out = ((timeval_ms() - t_start) > 500);
1005 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1006
1007 /* only remove breakpoint if we created it */
1008 if (breakpoint)
1009 cortex_m_unset_breakpoint(target, breakpoint);
1010 else {
1011 /* Remove the temporary breakpoint */
1012 breakpoint_remove(target, pc_value);
1013 }
1014
1015 if (isr_timed_out) {
1016 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1017 "leaving target running");
1018 } else {
1019 /* Step over next instruction with interrupts disabled */
1020 cortex_m_set_maskints_for_step(target);
1021 cortex_m_write_debug_halt_mask(target,
1022 C_HALT | C_MASKINTS,
1023 0);
1024 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1025 /* Re-enable interrupts if appropriate */
1026 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1027 cortex_m_set_maskints_for_halt(target);
1028 }
1029 }
1030 }
1031 }
1032 }
1033
1034 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1035 if (retval != ERROR_OK)
1036 return retval;
1037
1038 /* registers are now invalid */
1039 register_cache_invalidate(armv7m->arm.core_cache);
1040
1041 if (breakpoint)
1042 cortex_m_set_breakpoint(target, breakpoint);
1043
1044 if (isr_timed_out) {
1045 /* Leave the core running. The user has to stop execution manually. */
1046 target->debug_reason = DBG_REASON_NOTHALTED;
1047 target->state = TARGET_RUNNING;
1048 return ERROR_OK;
1049 }
1050
1051 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1052 " nvic_icsr = 0x%" PRIx32,
1053 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1054
1055 retval = cortex_m_debug_entry(target);
1056 if (retval != ERROR_OK)
1057 return retval;
1058 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1059
1060 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1061 " nvic_icsr = 0x%" PRIx32,
1062 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1063
1064 return ERROR_OK;
1065 }
1066
1067 static int cortex_m_assert_reset(struct target *target)
1068 {
1069 struct cortex_m_common *cortex_m = target_to_cm(target);
1070 struct armv7m_common *armv7m = &cortex_m->armv7m;
1071 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1072
1073 LOG_DEBUG("target->state: %s",
1074 target_state_name(target));
1075
1076 enum reset_types jtag_reset_config = jtag_get_reset_config();
1077
1078 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1079 /* allow scripts to override the reset event */
1080
1081 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1082 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1083 target->state = TARGET_RESET;
1084
1085 return ERROR_OK;
1086 }
1087
1088 /* some cores support connecting while srst is asserted
1089 * use that mode is it has been configured */
1090
1091 bool srst_asserted = false;
1092
1093 if (!target_was_examined(target)) {
1094 if (jtag_reset_config & RESET_HAS_SRST) {
1095 adapter_assert_reset();
1096 if (target->reset_halt)
1097 LOG_ERROR("Target not examined, will not halt after reset!");
1098 return ERROR_OK;
1099 } else {
1100 LOG_ERROR("Target not examined, reset NOT asserted!");
1101 return ERROR_FAIL;
1102 }
1103 }
1104
1105 if ((jtag_reset_config & RESET_HAS_SRST) &&
1106 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1107 adapter_assert_reset();
1108 srst_asserted = true;
1109 }
1110
1111 /* Enable debug requests */
1112 int retval;
1113 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1114 /* Store important errors instead of failing and proceed to reset assert */
1115
1116 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1117 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1118
1119 /* If the processor is sleeping in a WFI or WFE instruction, the
1120 * C_HALT bit must be asserted to regain control */
1121 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1122 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1123
1124 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1125 /* Ignore less important errors */
1126
1127 if (!target->reset_halt) {
1128 /* Set/Clear C_MASKINTS in a separate operation */
1129 cortex_m_set_maskints_for_run(target);
1130
1131 /* clear any debug flags before resuming */
1132 cortex_m_clear_halt(target);
1133
1134 /* clear C_HALT in dhcsr reg */
1135 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1136 } else {
1137 /* Halt in debug on reset; endreset_event() restores DEMCR.
1138 *
1139 * REVISIT catching BUSERR presumably helps to defend against
1140 * bad vector table entries. Should this include MMERR or
1141 * other flags too?
1142 */
1143 int retval2;
1144 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1145 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1146 if (retval != ERROR_OK || retval2 != ERROR_OK)
1147 LOG_INFO("AP write error, reset will not halt");
1148 }
1149
1150 if (jtag_reset_config & RESET_HAS_SRST) {
1151 /* default to asserting srst */
1152 if (!srst_asserted)
1153 adapter_assert_reset();
1154
1155 /* srst is asserted, ignore AP access errors */
1156 retval = ERROR_OK;
1157 } else {
1158 /* Use a standard Cortex-M3 software reset mechanism.
1159 * We default to using VECRESET as it is supported on all current cores
1160 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1161 * This has the disadvantage of not resetting the peripherals, so a
1162 * reset-init event handler is needed to perform any peripheral resets.
1163 */
1164 if (!cortex_m->vectreset_supported
1165 && reset_config == CORTEX_M_RESET_VECTRESET) {
1166 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1167 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1168 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1169 }
1170
1171 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1172 ? "SYSRESETREQ" : "VECTRESET");
1173
1174 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1175 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1176 "handler to reset any peripherals or configure hardware srst support.");
1177 }
1178
1179 int retval3;
1180 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1181 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1182 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1183 if (retval3 != ERROR_OK)
1184 LOG_DEBUG("Ignoring AP write error right after reset");
1185
1186 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1187 if (retval3 != ERROR_OK)
1188 LOG_ERROR("DP initialisation failed");
1189
1190 else {
1191 /* I do not know why this is necessary, but it
1192 * fixes strange effects (step/resume cause NMI
1193 * after reset) on LM3S6918 -- Michael Schwingen
1194 */
1195 uint32_t tmp;
1196 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1197 }
1198 }
1199
1200 target->state = TARGET_RESET;
1201 jtag_sleep(50000);
1202
1203 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1204
1205 /* now return stored error code if any */
1206 if (retval != ERROR_OK)
1207 return retval;
1208
1209 if (target->reset_halt) {
1210 retval = target_halt(target);
1211 if (retval != ERROR_OK)
1212 return retval;
1213 }
1214
1215 return ERROR_OK;
1216 }
1217
1218 static int cortex_m_deassert_reset(struct target *target)
1219 {
1220 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1221
1222 LOG_DEBUG("target->state: %s",
1223 target_state_name(target));
1224
1225 /* deassert reset lines */
1226 adapter_deassert_reset();
1227
1228 enum reset_types jtag_reset_config = jtag_get_reset_config();
1229
1230 if ((jtag_reset_config & RESET_HAS_SRST) &&
1231 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1232 target_was_examined(target)) {
1233 int retval = dap_dp_init(armv7m->debug_ap->dap);
1234 if (retval != ERROR_OK) {
1235 LOG_ERROR("DP initialisation failed");
1236 return retval;
1237 }
1238 }
1239
1240 return ERROR_OK;
1241 }
1242
1243 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1244 {
1245 int retval;
1246 int fp_num = 0;
1247 struct cortex_m_common *cortex_m = target_to_cm(target);
1248 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1249
1250 if (breakpoint->set) {
1251 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1252 return ERROR_OK;
1253 }
1254
1255 if (breakpoint->type == BKPT_HARD) {
1256 uint32_t fpcr_value;
1257 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1258 fp_num++;
1259 if (fp_num >= cortex_m->fp_num_code) {
1260 LOG_ERROR("Can not find free FPB Comparator!");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1262 }
1263 breakpoint->set = fp_num + 1;
1264 fpcr_value = breakpoint->address | 1;
1265 if (cortex_m->fp_rev == 0) {
1266 if (breakpoint->address > 0x1FFFFFFF) {
1267 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1268 return ERROR_FAIL;
1269 }
1270 uint32_t hilo;
1271 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1272 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1273 } else if (cortex_m->fp_rev > 1) {
1274 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1275 return ERROR_FAIL;
1276 }
1277 comparator_list[fp_num].used = true;
1278 comparator_list[fp_num].fpcr_value = fpcr_value;
1279 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1280 comparator_list[fp_num].fpcr_value);
1281 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1282 fp_num,
1283 comparator_list[fp_num].fpcr_value);
1284 if (!cortex_m->fpb_enabled) {
1285 LOG_DEBUG("FPB wasn't enabled, do it now");
1286 retval = cortex_m_enable_fpb(target);
1287 if (retval != ERROR_OK) {
1288 LOG_ERROR("Failed to enable the FPB");
1289 return retval;
1290 }
1291
1292 cortex_m->fpb_enabled = true;
1293 }
1294 } else if (breakpoint->type == BKPT_SOFT) {
1295 uint8_t code[4];
1296
1297 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1298 * semihosting; don't use that. Otherwise the BKPT
1299 * parameter is arbitrary.
1300 */
1301 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1302 retval = target_read_memory(target,
1303 breakpoint->address & 0xFFFFFFFE,
1304 breakpoint->length, 1,
1305 breakpoint->orig_instr);
1306 if (retval != ERROR_OK)
1307 return retval;
1308 retval = target_write_memory(target,
1309 breakpoint->address & 0xFFFFFFFE,
1310 breakpoint->length, 1,
1311 code);
1312 if (retval != ERROR_OK)
1313 return retval;
1314 breakpoint->set = true;
1315 }
1316
1317 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1318 breakpoint->unique_id,
1319 (int)(breakpoint->type),
1320 breakpoint->address,
1321 breakpoint->length,
1322 breakpoint->set);
1323
1324 return ERROR_OK;
1325 }
1326
1327 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1328 {
1329 int retval;
1330 struct cortex_m_common *cortex_m = target_to_cm(target);
1331 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1332
1333 if (!breakpoint->set) {
1334 LOG_WARNING("breakpoint not set");
1335 return ERROR_OK;
1336 }
1337
1338 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1339 breakpoint->unique_id,
1340 (int)(breakpoint->type),
1341 breakpoint->address,
1342 breakpoint->length,
1343 breakpoint->set);
1344
1345 if (breakpoint->type == BKPT_HARD) {
1346 int fp_num = breakpoint->set - 1;
1347 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1348 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1349 return ERROR_OK;
1350 }
1351 comparator_list[fp_num].used = false;
1352 comparator_list[fp_num].fpcr_value = 0;
1353 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1354 comparator_list[fp_num].fpcr_value);
1355 } else {
1356 /* restore original instruction (kept in target endianness) */
1357 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1358 breakpoint->length, 1,
1359 breakpoint->orig_instr);
1360 if (retval != ERROR_OK)
1361 return retval;
1362 }
1363 breakpoint->set = false;
1364
1365 return ERROR_OK;
1366 }
1367
1368 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1369 {
1370 if (breakpoint->length == 3) {
1371 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1372 breakpoint->length = 2;
1373 }
1374
1375 if ((breakpoint->length != 2)) {
1376 LOG_INFO("only breakpoints of two bytes length supported");
1377 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1378 }
1379
1380 return cortex_m_set_breakpoint(target, breakpoint);
1381 }
1382
1383 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1384 {
1385 if (!breakpoint->set)
1386 return ERROR_OK;
1387
1388 return cortex_m_unset_breakpoint(target, breakpoint);
1389 }
1390
1391 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1392 {
1393 int dwt_num = 0;
1394 struct cortex_m_common *cortex_m = target_to_cm(target);
1395
1396 /* REVISIT Don't fully trust these "not used" records ... users
1397 * may set up breakpoints by hand, e.g. dual-address data value
1398 * watchpoint using comparator #1; comparator #0 matching cycle
1399 * count; send data trace info through ITM and TPIU; etc
1400 */
1401 struct cortex_m_dwt_comparator *comparator;
1402
1403 for (comparator = cortex_m->dwt_comparator_list;
1404 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1405 comparator++, dwt_num++)
1406 continue;
1407 if (dwt_num >= cortex_m->dwt_num_comp) {
1408 LOG_ERROR("Can not find free DWT Comparator");
1409 return ERROR_FAIL;
1410 }
1411 comparator->used = true;
1412 watchpoint->set = dwt_num + 1;
1413
1414 comparator->comp = watchpoint->address;
1415 target_write_u32(target, comparator->dwt_comparator_address + 0,
1416 comparator->comp);
1417
1418 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1419 uint32_t mask = 0, temp;
1420
1421 /* watchpoint params were validated earlier */
1422 temp = watchpoint->length;
1423 while (temp) {
1424 temp >>= 1;
1425 mask++;
1426 }
1427 mask--;
1428
1429 comparator->mask = mask;
1430 target_write_u32(target, comparator->dwt_comparator_address + 4,
1431 comparator->mask);
1432
1433 switch (watchpoint->rw) {
1434 case WPT_READ:
1435 comparator->function = 5;
1436 break;
1437 case WPT_WRITE:
1438 comparator->function = 6;
1439 break;
1440 case WPT_ACCESS:
1441 comparator->function = 7;
1442 break;
1443 }
1444 } else {
1445 uint32_t data_size = watchpoint->length >> 1;
1446 comparator->mask = (watchpoint->length >> 1) | 1;
1447
1448 switch (watchpoint->rw) {
1449 case WPT_ACCESS:
1450 comparator->function = 4;
1451 break;
1452 case WPT_WRITE:
1453 comparator->function = 5;
1454 break;
1455 case WPT_READ:
1456 comparator->function = 6;
1457 break;
1458 }
1459 comparator->function = comparator->function | (1 << 4) |
1460 (data_size << 10);
1461 }
1462
1463 target_write_u32(target, comparator->dwt_comparator_address + 8,
1464 comparator->function);
1465
1466 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1467 watchpoint->unique_id, dwt_num,
1468 (unsigned) comparator->comp,
1469 (unsigned) comparator->mask,
1470 (unsigned) comparator->function);
1471 return ERROR_OK;
1472 }
1473
1474 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1475 {
1476 struct cortex_m_common *cortex_m = target_to_cm(target);
1477 struct cortex_m_dwt_comparator *comparator;
1478 int dwt_num;
1479
1480 if (!watchpoint->set) {
1481 LOG_WARNING("watchpoint (wpid: %d) not set",
1482 watchpoint->unique_id);
1483 return ERROR_OK;
1484 }
1485
1486 dwt_num = watchpoint->set - 1;
1487
1488 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1489 watchpoint->unique_id, dwt_num,
1490 (unsigned) watchpoint->address);
1491
1492 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1493 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1494 return ERROR_OK;
1495 }
1496
1497 comparator = cortex_m->dwt_comparator_list + dwt_num;
1498 comparator->used = false;
1499 comparator->function = 0;
1500 target_write_u32(target, comparator->dwt_comparator_address + 8,
1501 comparator->function);
1502
1503 watchpoint->set = false;
1504
1505 return ERROR_OK;
1506 }
1507
1508 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1509 {
1510 struct cortex_m_common *cortex_m = target_to_cm(target);
1511
1512 if (cortex_m->dwt_comp_available < 1) {
1513 LOG_DEBUG("no comparators?");
1514 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1515 }
1516
1517 /* hardware doesn't support data value masking */
1518 if (watchpoint->mask != ~(uint32_t)0) {
1519 LOG_DEBUG("watchpoint value masks not supported");
1520 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1521 }
1522
1523 /* hardware allows address masks of up to 32K */
1524 unsigned mask;
1525
1526 for (mask = 0; mask < 16; mask++) {
1527 if ((1u << mask) == watchpoint->length)
1528 break;
1529 }
1530 if (mask == 16) {
1531 LOG_DEBUG("unsupported watchpoint length");
1532 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1533 }
1534 if (watchpoint->address & ((1 << mask) - 1)) {
1535 LOG_DEBUG("watchpoint address is unaligned");
1536 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1537 }
1538
1539 /* Caller doesn't seem to be able to describe watching for data
1540 * values of zero; that flags "no value".
1541 *
1542 * REVISIT This DWT may well be able to watch for specific data
1543 * values. Requires comparator #1 to set DATAVMATCH and match
1544 * the data, and another comparator (DATAVADDR0) matching addr.
1545 */
1546 if (watchpoint->value) {
1547 LOG_DEBUG("data value watchpoint not YET supported");
1548 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1549 }
1550
1551 cortex_m->dwt_comp_available--;
1552 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1553
1554 return ERROR_OK;
1555 }
1556
1557 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1558 {
1559 struct cortex_m_common *cortex_m = target_to_cm(target);
1560
1561 /* REVISIT why check? DWT can be updated with core running ... */
1562 if (target->state != TARGET_HALTED) {
1563 LOG_WARNING("target not halted");
1564 return ERROR_TARGET_NOT_HALTED;
1565 }
1566
1567 if (watchpoint->set)
1568 cortex_m_unset_watchpoint(target, watchpoint);
1569
1570 cortex_m->dwt_comp_available++;
1571 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1572
1573 return ERROR_OK;
1574 }
1575
1576 void cortex_m_enable_watchpoints(struct target *target)
1577 {
1578 struct watchpoint *watchpoint = target->watchpoints;
1579
1580 /* set any pending watchpoints */
1581 while (watchpoint) {
1582 if (!watchpoint->set)
1583 cortex_m_set_watchpoint(target, watchpoint);
1584 watchpoint = watchpoint->next;
1585 }
1586 }
1587
1588 static int cortex_m_load_core_reg_u32(struct target *target,
1589 uint32_t num, uint32_t *value)
1590 {
1591 int retval;
1592
1593 /* NOTE: we "know" here that the register identifiers used
1594 * in the v7m header match the Cortex-M3 Debug Core Register
1595 * Selector values for R0..R15, xPSR, MSP, and PSP.
1596 */
1597 switch (num) {
1598 case 0 ... 18:
1599 /* read a normal core register */
1600 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1601
1602 if (retval != ERROR_OK) {
1603 LOG_ERROR("JTAG failure %i", retval);
1604 return ERROR_JTAG_DEVICE_ERROR;
1605 }
1606 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1607 break;
1608
1609 case ARMV7M_FPSCR:
1610 /* Floating-point Status and Registers */
1611 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1612 if (retval != ERROR_OK)
1613 return retval;
1614 retval = target_read_u32(target, DCB_DCRDR, value);
1615 if (retval != ERROR_OK)
1616 return retval;
1617 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1618 break;
1619
1620 case ARMV7M_S0 ... ARMV7M_S31:
1621 /* Floating-point Status and Registers */
1622 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1623 if (retval != ERROR_OK)
1624 return retval;
1625 retval = target_read_u32(target, DCB_DCRDR, value);
1626 if (retval != ERROR_OK)
1627 return retval;
1628 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1629 (int)(num - ARMV7M_S0), *value);
1630 break;
1631
1632 case ARMV7M_PRIMASK:
1633 case ARMV7M_BASEPRI:
1634 case ARMV7M_FAULTMASK:
1635 case ARMV7M_CONTROL:
1636 /* Cortex-M3 packages these four registers as bitfields
1637 * in one Debug Core register. So say r0 and r2 docs;
1638 * it was removed from r1 docs, but still works.
1639 */
1640 cortexm_dap_read_coreregister_u32(target, value, 20);
1641
1642 switch (num) {
1643 case ARMV7M_PRIMASK:
1644 *value = buf_get_u32((uint8_t *)value, 0, 1);
1645 break;
1646
1647 case ARMV7M_BASEPRI:
1648 *value = buf_get_u32((uint8_t *)value, 8, 8);
1649 break;
1650
1651 case ARMV7M_FAULTMASK:
1652 *value = buf_get_u32((uint8_t *)value, 16, 1);
1653 break;
1654
1655 case ARMV7M_CONTROL:
1656 *value = buf_get_u32((uint8_t *)value, 24, 2);
1657 break;
1658 }
1659
1660 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1661 break;
1662
1663 default:
1664 return ERROR_COMMAND_SYNTAX_ERROR;
1665 }
1666
1667 return ERROR_OK;
1668 }
1669
1670 static int cortex_m_store_core_reg_u32(struct target *target,
1671 uint32_t num, uint32_t value)
1672 {
1673 int retval;
1674 uint32_t reg;
1675 struct armv7m_common *armv7m = target_to_armv7m(target);
1676
1677 /* NOTE: we "know" here that the register identifiers used
1678 * in the v7m header match the Cortex-M3 Debug Core Register
1679 * Selector values for R0..R15, xPSR, MSP, and PSP.
1680 */
1681 switch (num) {
1682 case 0 ... 18:
1683 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1684 if (retval != ERROR_OK) {
1685 struct reg *r;
1686
1687 LOG_ERROR("JTAG failure");
1688 r = armv7m->arm.core_cache->reg_list + num;
1689 r->dirty = r->valid;
1690 return ERROR_JTAG_DEVICE_ERROR;
1691 }
1692 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1693 break;
1694
1695 case ARMV7M_FPSCR:
1696 /* Floating-point Status and Registers */
1697 retval = target_write_u32(target, DCB_DCRDR, value);
1698 if (retval != ERROR_OK)
1699 return retval;
1700 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1701 if (retval != ERROR_OK)
1702 return retval;
1703 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1704 break;
1705
1706 case ARMV7M_S0 ... ARMV7M_S31:
1707 /* Floating-point Status and Registers */
1708 retval = target_write_u32(target, DCB_DCRDR, value);
1709 if (retval != ERROR_OK)
1710 return retval;
1711 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1712 if (retval != ERROR_OK)
1713 return retval;
1714 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1715 (int)(num - ARMV7M_S0), value);
1716 break;
1717
1718 case ARMV7M_PRIMASK:
1719 case ARMV7M_BASEPRI:
1720 case ARMV7M_FAULTMASK:
1721 case ARMV7M_CONTROL:
1722 /* Cortex-M3 packages these four registers as bitfields
1723 * in one Debug Core register. So say r0 and r2 docs;
1724 * it was removed from r1 docs, but still works.
1725 */
1726 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1727
1728 switch (num) {
1729 case ARMV7M_PRIMASK:
1730 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1731 break;
1732
1733 case ARMV7M_BASEPRI:
1734 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1735 break;
1736
1737 case ARMV7M_FAULTMASK:
1738 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1739 break;
1740
1741 case ARMV7M_CONTROL:
1742 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1743 break;
1744 }
1745
1746 cortexm_dap_write_coreregister_u32(target, reg, 20);
1747
1748 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1749 break;
1750
1751 default:
1752 return ERROR_COMMAND_SYNTAX_ERROR;
1753 }
1754
1755 return ERROR_OK;
1756 }
1757
1758 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1759 uint32_t size, uint32_t count, uint8_t *buffer)
1760 {
1761 struct armv7m_common *armv7m = target_to_armv7m(target);
1762
1763 if (armv7m->arm.is_armv6m) {
1764 /* armv6m does not handle unaligned memory access */
1765 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1766 return ERROR_TARGET_UNALIGNED_ACCESS;
1767 }
1768
1769 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1770 }
1771
1772 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1773 uint32_t size, uint32_t count, const uint8_t *buffer)
1774 {
1775 struct armv7m_common *armv7m = target_to_armv7m(target);
1776
1777 if (armv7m->arm.is_armv6m) {
1778 /* armv6m does not handle unaligned memory access */
1779 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1780 return ERROR_TARGET_UNALIGNED_ACCESS;
1781 }
1782
1783 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1784 }
1785
1786 static int cortex_m_init_target(struct command_context *cmd_ctx,
1787 struct target *target)
1788 {
1789 armv7m_build_reg_cache(target);
1790 arm_semihosting_init(target);
1791 return ERROR_OK;
1792 }
1793
1794 void cortex_m_deinit_target(struct target *target)
1795 {
1796 struct cortex_m_common *cortex_m = target_to_cm(target);
1797
1798 free(cortex_m->fp_comparator_list);
1799
1800 cortex_m_dwt_free(target);
1801 armv7m_free_reg_cache(target);
1802
1803 free(target->private_config);
1804 free(cortex_m);
1805 }
1806
1807 int cortex_m_profiling(struct target *target, uint32_t *samples,
1808 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1809 {
1810 struct timeval timeout, now;
1811 struct armv7m_common *armv7m = target_to_armv7m(target);
1812 uint32_t reg_value;
1813 bool use_pcsr = false;
1814 int retval = ERROR_OK;
1815 struct reg *reg;
1816
1817 gettimeofday(&timeout, NULL);
1818 timeval_add_time(&timeout, seconds, 0);
1819
1820 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1821 if (retval != ERROR_OK) {
1822 LOG_ERROR("Error while reading PCSR");
1823 return retval;
1824 }
1825
1826 if (reg_value != 0) {
1827 use_pcsr = true;
1828 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1829 } else {
1830 LOG_INFO("Starting profiling. Halting and resuming the"
1831 " target as often as we can...");
1832 reg = register_get_by_name(target->reg_cache, "pc", 1);
1833 }
1834
1835 /* Make sure the target is running */
1836 target_poll(target);
1837 if (target->state == TARGET_HALTED)
1838 retval = target_resume(target, 1, 0, 0, 0);
1839
1840 if (retval != ERROR_OK) {
1841 LOG_ERROR("Error while resuming target");
1842 return retval;
1843 }
1844
1845 uint32_t sample_count = 0;
1846
1847 for (;;) {
1848 if (use_pcsr) {
1849 if (armv7m && armv7m->debug_ap) {
1850 uint32_t read_count = max_num_samples - sample_count;
1851 if (read_count > 1024)
1852 read_count = 1024;
1853
1854 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1855 (void *)&samples[sample_count],
1856 4, read_count, DWT_PCSR);
1857 sample_count += read_count;
1858 } else {
1859 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1860 }
1861 } else {
1862 target_poll(target);
1863 if (target->state == TARGET_HALTED) {
1864 reg_value = buf_get_u32(reg->value, 0, 32);
1865 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1866 retval = target_resume(target, 1, 0, 0, 0);
1867 samples[sample_count++] = reg_value;
1868 target_poll(target);
1869 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1870 } else if (target->state == TARGET_RUNNING) {
1871 /* We want to quickly sample the PC. */
1872 retval = target_halt(target);
1873 } else {
1874 LOG_INFO("Target not halted or running");
1875 retval = ERROR_OK;
1876 break;
1877 }
1878 }
1879
1880 if (retval != ERROR_OK) {
1881 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1882 return retval;
1883 }
1884
1885
1886 gettimeofday(&now, NULL);
1887 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1888 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1889 break;
1890 }
1891 }
1892
1893 *num_samples = sample_count;
1894 return retval;
1895 }
1896
1897
1898 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1899 * on r/w if the core is not running, and clear on resume or reset ... or
1900 * at least, in a post_restore_context() method.
1901 */
1902
1903 struct dwt_reg_state {
1904 struct target *target;
1905 uint32_t addr;
1906 uint8_t value[4]; /* scratch/cache */
1907 };
1908
1909 static int cortex_m_dwt_get_reg(struct reg *reg)
1910 {
1911 struct dwt_reg_state *state = reg->arch_info;
1912
1913 uint32_t tmp;
1914 int retval = target_read_u32(state->target, state->addr, &tmp);
1915 if (retval != ERROR_OK)
1916 return retval;
1917
1918 buf_set_u32(state->value, 0, 32, tmp);
1919 return ERROR_OK;
1920 }
1921
1922 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1923 {
1924 struct dwt_reg_state *state = reg->arch_info;
1925
1926 return target_write_u32(state->target, state->addr,
1927 buf_get_u32(buf, 0, reg->size));
1928 }
1929
1930 struct dwt_reg {
1931 uint32_t addr;
1932 const char *name;
1933 unsigned size;
1934 };
1935
1936 static const struct dwt_reg dwt_base_regs[] = {
1937 { DWT_CTRL, "dwt_ctrl", 32, },
1938 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1939 * increments while the core is asleep.
1940 */
1941 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1942 /* plus some 8 bit counters, useful for profiling with TPIU */
1943 };
1944
1945 static const struct dwt_reg dwt_comp[] = {
1946 #define DWT_COMPARATOR(i) \
1947 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1948 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1949 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1950 DWT_COMPARATOR(0),
1951 DWT_COMPARATOR(1),
1952 DWT_COMPARATOR(2),
1953 DWT_COMPARATOR(3),
1954 DWT_COMPARATOR(4),
1955 DWT_COMPARATOR(5),
1956 DWT_COMPARATOR(6),
1957 DWT_COMPARATOR(7),
1958 DWT_COMPARATOR(8),
1959 DWT_COMPARATOR(9),
1960 DWT_COMPARATOR(10),
1961 DWT_COMPARATOR(11),
1962 DWT_COMPARATOR(12),
1963 DWT_COMPARATOR(13),
1964 DWT_COMPARATOR(14),
1965 DWT_COMPARATOR(15),
1966 #undef DWT_COMPARATOR
1967 };
1968
1969 static const struct reg_arch_type dwt_reg_type = {
1970 .get = cortex_m_dwt_get_reg,
1971 .set = cortex_m_dwt_set_reg,
1972 };
1973
1974 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1975 {
1976 struct dwt_reg_state *state;
1977
1978 state = calloc(1, sizeof *state);
1979 if (!state)
1980 return;
1981 state->addr = d->addr;
1982 state->target = t;
1983
1984 r->name = d->name;
1985 r->size = d->size;
1986 r->value = state->value;
1987 r->arch_info = state;
1988 r->type = &dwt_reg_type;
1989 }
1990
1991 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1992 {
1993 uint32_t dwtcr;
1994 struct reg_cache *cache;
1995 struct cortex_m_dwt_comparator *comparator;
1996 int reg, i;
1997
1998 target_read_u32(target, DWT_CTRL, &dwtcr);
1999 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
2000 if (!dwtcr) {
2001 LOG_DEBUG("no DWT");
2002 return;
2003 }
2004
2005 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
2006 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
2007
2008 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
2009 cm->dwt_comp_available = cm->dwt_num_comp;
2010 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
2011 sizeof(struct cortex_m_dwt_comparator));
2012 if (!cm->dwt_comparator_list) {
2013 fail0:
2014 cm->dwt_num_comp = 0;
2015 LOG_ERROR("out of mem");
2016 return;
2017 }
2018
2019 cache = calloc(1, sizeof *cache);
2020 if (!cache) {
2021 fail1:
2022 free(cm->dwt_comparator_list);
2023 goto fail0;
2024 }
2025 cache->name = "Cortex-M DWT registers";
2026 cache->num_regs = 2 + cm->dwt_num_comp * 3;
2027 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
2028 if (!cache->reg_list) {
2029 free(cache);
2030 goto fail1;
2031 }
2032
2033 for (reg = 0; reg < 2; reg++)
2034 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2035 dwt_base_regs + reg);
2036
2037 comparator = cm->dwt_comparator_list;
2038 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
2039 int j;
2040
2041 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
2042 for (j = 0; j < 3; j++, reg++)
2043 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2044 dwt_comp + 3 * i + j);
2045
2046 /* make sure we clear any watchpoints enabled on the target */
2047 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
2048 }
2049
2050 *register_get_last_cache_p(&target->reg_cache) = cache;
2051 cm->dwt_cache = cache;
2052
2053 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
2054 dwtcr, cm->dwt_num_comp,
2055 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
2056
2057 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2058 * implement single-address data value watchpoints ... so we
2059 * won't need to check it later, when asked to set one up.
2060 */
2061 }
2062
2063 static void cortex_m_dwt_free(struct target *target)
2064 {
2065 struct cortex_m_common *cm = target_to_cm(target);
2066 struct reg_cache *cache = cm->dwt_cache;
2067
2068 free(cm->dwt_comparator_list);
2069 cm->dwt_comparator_list = NULL;
2070 cm->dwt_num_comp = 0;
2071
2072 if (cache) {
2073 register_unlink_cache(&target->reg_cache, cache);
2074
2075 if (cache->reg_list) {
2076 for (size_t i = 0; i < cache->num_regs; i++)
2077 free(cache->reg_list[i].arch_info);
2078 free(cache->reg_list);
2079 }
2080 free(cache);
2081 }
2082 cm->dwt_cache = NULL;
2083 }
2084
2085 #define MVFR0 0xe000ef40
2086 #define MVFR1 0xe000ef44
2087
2088 #define MVFR0_DEFAULT_M4 0x10110021
2089 #define MVFR1_DEFAULT_M4 0x11000011
2090
2091 #define MVFR0_DEFAULT_M7_SP 0x10110021
2092 #define MVFR0_DEFAULT_M7_DP 0x10110221
2093 #define MVFR1_DEFAULT_M7_SP 0x11000011
2094 #define MVFR1_DEFAULT_M7_DP 0x12000011
2095
2096 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2097 struct adiv5_ap **debug_ap)
2098 {
2099 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2100 return ERROR_OK;
2101
2102 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2103 }
2104
2105 int cortex_m_examine(struct target *target)
2106 {
2107 int retval;
2108 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2109 int i;
2110 struct cortex_m_common *cortex_m = target_to_cm(target);
2111 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2112 struct armv7m_common *armv7m = target_to_armv7m(target);
2113
2114 /* stlink shares the examine handler but does not support
2115 * all its calls */
2116 if (!armv7m->stlink) {
2117 if (cortex_m->apsel == DP_APSEL_INVALID) {
2118 /* Search for the MEM-AP */
2119 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2120 if (retval != ERROR_OK) {
2121 LOG_ERROR("Could not find MEM-AP to control the core");
2122 return retval;
2123 }
2124 } else {
2125 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2126 }
2127
2128 /* Leave (only) generic DAP stuff for debugport_init(); */
2129 armv7m->debug_ap->memaccess_tck = 8;
2130
2131 retval = mem_ap_init(armv7m->debug_ap);
2132 if (retval != ERROR_OK)
2133 return retval;
2134 }
2135
2136 if (!target_was_examined(target)) {
2137 target_set_examined(target);
2138
2139 /* Read from Device Identification Registers */
2140 retval = target_read_u32(target, CPUID, &cpuid);
2141 if (retval != ERROR_OK)
2142 return retval;
2143
2144 /* Get CPU Type */
2145 i = (cpuid >> 4) & 0xf;
2146
2147 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
2148 case CORTEX_M23_PARTNO:
2149 i = 23;
2150 break;
2151
2152 case CORTEX_M33_PARTNO:
2153 i = 33;
2154 break;
2155
2156 default:
2157 break;
2158 }
2159
2160
2161 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2162 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2163 cortex_m->maskints_erratum = false;
2164 if (i == 7) {
2165 uint8_t rev, patch;
2166 rev = (cpuid >> 20) & 0xf;
2167 patch = (cpuid >> 0) & 0xf;
2168 if ((rev == 0) && (patch < 2)) {
2169 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2170 cortex_m->maskints_erratum = true;
2171 }
2172 }
2173 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2174
2175 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2176 cortex_m->vectreset_supported = i > 1;
2177
2178 if (i == 4) {
2179 target_read_u32(target, MVFR0, &mvfr0);
2180 target_read_u32(target, MVFR1, &mvfr1);
2181
2182 /* test for floating point feature on Cortex-M4 */
2183 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2184 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2185 armv7m->fp_feature = FPv4_SP;
2186 }
2187 } else if (i == 7 || i == 33) {
2188 target_read_u32(target, MVFR0, &mvfr0);
2189 target_read_u32(target, MVFR1, &mvfr1);
2190
2191 /* test for floating point features on Cortex-M7 */
2192 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2193 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2194 armv7m->fp_feature = FPv5_SP;
2195 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2196 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2197 armv7m->fp_feature = FPv5_DP;
2198 }
2199 } else if (i == 0) {
2200 /* Cortex-M0 does not support unaligned memory access */
2201 armv7m->arm.is_armv6m = true;
2202 }
2203
2204 if (armv7m->fp_feature == FP_NONE &&
2205 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2206 /* free unavailable FPU registers */
2207 size_t idx;
2208
2209 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2210 idx < armv7m->arm.core_cache->num_regs;
2211 idx++) {
2212 free(armv7m->arm.core_cache->reg_list[idx].value);
2213 free(armv7m->arm.core_cache->reg_list[idx].feature);
2214 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2215 }
2216 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2217 }
2218
2219 if (!armv7m->stlink) {
2220 if (i == 3 || i == 4)
2221 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2222 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2223 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2224 else if (i == 7)
2225 /* Cortex-M7 has only 1024 bytes autoincrement range */
2226 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2227 }
2228
2229 /* Configure trace modules */
2230 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2231 if (retval != ERROR_OK)
2232 return retval;
2233
2234 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2235 armv7m_trace_tpiu_config(target);
2236 armv7m_trace_itm_config(target);
2237 }
2238
2239 /* NOTE: FPB and DWT are both optional. */
2240
2241 /* Setup FPB */
2242 target_read_u32(target, FP_CTRL, &fpcr);
2243 /* bits [14:12] and [7:4] */
2244 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2245 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2246 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2247 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2248 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2249 free(cortex_m->fp_comparator_list);
2250 cortex_m->fp_comparator_list = calloc(
2251 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2252 sizeof(struct cortex_m_fp_comparator));
2253 cortex_m->fpb_enabled = fpcr & 1;
2254 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2255 cortex_m->fp_comparator_list[i].type =
2256 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2257 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2258
2259 /* make sure we clear any breakpoints enabled on the target */
2260 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2261 }
2262 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2263 fpcr,
2264 cortex_m->fp_num_code,
2265 cortex_m->fp_num_lit);
2266
2267 /* Setup DWT */
2268 cortex_m_dwt_free(target);
2269 cortex_m_dwt_setup(cortex_m, target);
2270
2271 /* These hardware breakpoints only work for code in flash! */
2272 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2273 target_name(target),
2274 cortex_m->fp_num_code,
2275 cortex_m->dwt_num_comp);
2276 }
2277
2278 return ERROR_OK;
2279 }
2280
2281 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2282 {
2283 struct armv7m_common *armv7m = target_to_armv7m(target);
2284 uint16_t dcrdr;
2285 uint8_t buf[2];
2286 int retval;
2287
2288 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2289 if (retval != ERROR_OK)
2290 return retval;
2291
2292 dcrdr = target_buffer_get_u16(target, buf);
2293 *ctrl = (uint8_t)dcrdr;
2294 *value = (uint8_t)(dcrdr >> 8);
2295
2296 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2297
2298 /* write ack back to software dcc register
2299 * signify we have read data */
2300 if (dcrdr & (1 << 0)) {
2301 target_buffer_set_u16(target, buf, 0);
2302 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2303 if (retval != ERROR_OK)
2304 return retval;
2305 }
2306
2307 return ERROR_OK;
2308 }
2309
2310 static int cortex_m_target_request_data(struct target *target,
2311 uint32_t size, uint8_t *buffer)
2312 {
2313 uint8_t data;
2314 uint8_t ctrl;
2315 uint32_t i;
2316
2317 for (i = 0; i < (size * 4); i++) {
2318 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2319 if (retval != ERROR_OK)
2320 return retval;
2321 buffer[i] = data;
2322 }
2323
2324 return ERROR_OK;
2325 }
2326
2327 static int cortex_m_handle_target_request(void *priv)
2328 {
2329 struct target *target = priv;
2330 if (!target_was_examined(target))
2331 return ERROR_OK;
2332
2333 if (!target->dbg_msg_enabled)
2334 return ERROR_OK;
2335
2336 if (target->state == TARGET_RUNNING) {
2337 uint8_t data;
2338 uint8_t ctrl;
2339 int retval;
2340
2341 retval = cortex_m_dcc_read(target, &data, &ctrl);
2342 if (retval != ERROR_OK)
2343 return retval;
2344
2345 /* check if we have data */
2346 if (ctrl & (1 << 0)) {
2347 uint32_t request;
2348
2349 /* we assume target is quick enough */
2350 request = data;
2351 for (int i = 1; i <= 3; i++) {
2352 retval = cortex_m_dcc_read(target, &data, &ctrl);
2353 if (retval != ERROR_OK)
2354 return retval;
2355 request |= ((uint32_t)data << (i * 8));
2356 }
2357 target_request(target, request);
2358 }
2359 }
2360
2361 return ERROR_OK;
2362 }
2363
2364 static int cortex_m_init_arch_info(struct target *target,
2365 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2366 {
2367 struct armv7m_common *armv7m = &cortex_m->armv7m;
2368
2369 armv7m_init_arch_info(target, armv7m);
2370
2371 /* default reset mode is to use srst if fitted
2372 * if not it will use CORTEX_M3_RESET_VECTRESET */
2373 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2374
2375 armv7m->arm.dap = dap;
2376
2377 /* register arch-specific functions */
2378 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2379
2380 armv7m->post_debug_entry = NULL;
2381
2382 armv7m->pre_restore_context = NULL;
2383
2384 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2385 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2386
2387 target_register_timer_callback(cortex_m_handle_target_request, 1,
2388 TARGET_TIMER_TYPE_PERIODIC, target);
2389
2390 return ERROR_OK;
2391 }
2392
2393 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2394 {
2395 struct adiv5_private_config *pc;
2396
2397 pc = (struct adiv5_private_config *)target->private_config;
2398 if (adiv5_verify_config(pc) != ERROR_OK)
2399 return ERROR_FAIL;
2400
2401 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2402 if (cortex_m == NULL) {
2403 LOG_ERROR("No memory creating target");
2404 return ERROR_FAIL;
2405 }
2406
2407 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2408 cortex_m->apsel = pc->ap_num;
2409
2410 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2411
2412 return ERROR_OK;
2413 }
2414
2415 /*--------------------------------------------------------------------------*/
2416
2417 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2418 struct cortex_m_common *cm)
2419 {
2420 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2421 command_print(cmd, "target is not a Cortex-M");
2422 return ERROR_TARGET_INVALID;
2423 }
2424 return ERROR_OK;
2425 }
2426
2427 /*
2428 * Only stuff below this line should need to verify that its target
2429 * is a Cortex-M3. Everything else should have indirected through the
2430 * cortexm3_target structure, which is only used with CM3 targets.
2431 */
2432
2433 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2434 {
2435 struct target *target = get_current_target(CMD_CTX);
2436 struct cortex_m_common *cortex_m = target_to_cm(target);
2437 struct armv7m_common *armv7m = &cortex_m->armv7m;
2438 uint32_t demcr = 0;
2439 int retval;
2440
2441 static const struct {
2442 char name[10];
2443 unsigned mask;
2444 } vec_ids[] = {
2445 { "hard_err", VC_HARDERR, },
2446 { "int_err", VC_INTERR, },
2447 { "bus_err", VC_BUSERR, },
2448 { "state_err", VC_STATERR, },
2449 { "chk_err", VC_CHKERR, },
2450 { "nocp_err", VC_NOCPERR, },
2451 { "mm_err", VC_MMERR, },
2452 { "reset", VC_CORERESET, },
2453 };
2454
2455 retval = cortex_m_verify_pointer(CMD, cortex_m);
2456 if (retval != ERROR_OK)
2457 return retval;
2458
2459 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2460 if (retval != ERROR_OK)
2461 return retval;
2462
2463 if (CMD_ARGC > 0) {
2464 unsigned catch = 0;
2465
2466 if (CMD_ARGC == 1) {
2467 if (strcmp(CMD_ARGV[0], "all") == 0) {
2468 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2469 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2470 | VC_MMERR | VC_CORERESET;
2471 goto write;
2472 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2473 goto write;
2474 }
2475 while (CMD_ARGC-- > 0) {
2476 unsigned i;
2477 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2478 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2479 continue;
2480 catch |= vec_ids[i].mask;
2481 break;
2482 }
2483 if (i == ARRAY_SIZE(vec_ids)) {
2484 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2485 return ERROR_COMMAND_SYNTAX_ERROR;
2486 }
2487 }
2488 write:
2489 /* For now, armv7m->demcr only stores vector catch flags. */
2490 armv7m->demcr = catch;
2491
2492 demcr &= ~0xffff;
2493 demcr |= catch;
2494
2495 /* write, but don't assume it stuck (why not??) */
2496 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2497 if (retval != ERROR_OK)
2498 return retval;
2499 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2500 if (retval != ERROR_OK)
2501 return retval;
2502
2503 /* FIXME be sure to clear DEMCR on clean server shutdown.
2504 * Otherwise the vector catch hardware could fire when there's
2505 * no debugger hooked up, causing much confusion...
2506 */
2507 }
2508
2509 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2510 command_print(CMD, "%9s: %s", vec_ids[i].name,
2511 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2512 }
2513
2514 return ERROR_OK;
2515 }
2516
2517 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2518 {
2519 struct target *target = get_current_target(CMD_CTX);
2520 struct cortex_m_common *cortex_m = target_to_cm(target);
2521 int retval;
2522
2523 static const Jim_Nvp nvp_maskisr_modes[] = {
2524 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2525 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2526 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2527 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2528 { .name = NULL, .value = -1 },
2529 };
2530 const Jim_Nvp *n;
2531
2532
2533 retval = cortex_m_verify_pointer(CMD, cortex_m);
2534 if (retval != ERROR_OK)
2535 return retval;
2536
2537 if (target->state != TARGET_HALTED) {
2538 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2539 return ERROR_OK;
2540 }
2541
2542 if (CMD_ARGC > 0) {
2543 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2544 if (n->name == NULL)
2545 return ERROR_COMMAND_SYNTAX_ERROR;
2546 cortex_m->isrmasking_mode = n->value;
2547 cortex_m_set_maskints_for_halt(target);
2548 }
2549
2550 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2551 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2552
2553 return ERROR_OK;
2554 }
2555
2556 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2557 {
2558 struct target *target = get_current_target(CMD_CTX);
2559 struct cortex_m_common *cortex_m = target_to_cm(target);
2560 int retval;
2561 char *reset_config;
2562
2563 retval = cortex_m_verify_pointer(CMD, cortex_m);
2564 if (retval != ERROR_OK)
2565 return retval;
2566
2567 if (CMD_ARGC > 0) {
2568 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2569 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2570
2571 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2572 if (target_was_examined(target)
2573 && !cortex_m->vectreset_supported)
2574 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2575 else
2576 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2577
2578 } else
2579 return ERROR_COMMAND_SYNTAX_ERROR;
2580 }
2581
2582 switch (cortex_m->soft_reset_config) {
2583 case CORTEX_M_RESET_SYSRESETREQ:
2584 reset_config = "sysresetreq";
2585 break;
2586
2587 case CORTEX_M_RESET_VECTRESET:
2588 reset_config = "vectreset";
2589 break;
2590
2591 default:
2592 reset_config = "unknown";
2593 break;
2594 }
2595
2596 command_print(CMD, "cortex_m reset_config %s", reset_config);
2597
2598 return ERROR_OK;
2599 }
2600
2601 static const struct command_registration cortex_m_exec_command_handlers[] = {
2602 {
2603 .name = "maskisr",
2604 .handler = handle_cortex_m_mask_interrupts_command,
2605 .mode = COMMAND_EXEC,
2606 .help = "mask cortex_m interrupts",
2607 .usage = "['auto'|'on'|'off'|'steponly']",
2608 },
2609 {
2610 .name = "vector_catch",
2611 .handler = handle_cortex_m_vector_catch_command,
2612 .mode = COMMAND_EXEC,
2613 .help = "configure hardware vectors to trigger debug entry",
2614 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2615 },
2616 {
2617 .name = "reset_config",
2618 .handler = handle_cortex_m_reset_config_command,
2619 .mode = COMMAND_ANY,
2620 .help = "configure software reset handling",
2621 .usage = "['sysresetreq'|'vectreset']",
2622 },
2623 COMMAND_REGISTRATION_DONE
2624 };
2625 static const struct command_registration cortex_m_command_handlers[] = {
2626 {
2627 .chain = armv7m_command_handlers,
2628 },
2629 {
2630 .chain = armv7m_trace_command_handlers,
2631 },
2632 {
2633 .name = "cortex_m",
2634 .mode = COMMAND_EXEC,
2635 .help = "Cortex-M command group",
2636 .usage = "",
2637 .chain = cortex_m_exec_command_handlers,
2638 },
2639 COMMAND_REGISTRATION_DONE
2640 };
2641
2642 struct target_type cortexm_target = {
2643 .name = "cortex_m",
2644 .deprecated_name = "cortex_m3",
2645
2646 .poll = cortex_m_poll,
2647 .arch_state = armv7m_arch_state,
2648
2649 .target_request_data = cortex_m_target_request_data,
2650
2651 .halt = cortex_m_halt,
2652 .resume = cortex_m_resume,
2653 .step = cortex_m_step,
2654
2655 .assert_reset = cortex_m_assert_reset,
2656 .deassert_reset = cortex_m_deassert_reset,
2657 .soft_reset_halt = cortex_m_soft_reset_halt,
2658
2659 .get_gdb_arch = arm_get_gdb_arch,
2660 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2661
2662 .read_memory = cortex_m_read_memory,
2663 .write_memory = cortex_m_write_memory,
2664 .checksum_memory = armv7m_checksum_memory,
2665 .blank_check_memory = armv7m_blank_check_memory,
2666
2667 .run_algorithm = armv7m_run_algorithm,
2668 .start_algorithm = armv7m_start_algorithm,
2669 .wait_algorithm = armv7m_wait_algorithm,
2670
2671 .add_breakpoint = cortex_m_add_breakpoint,
2672 .remove_breakpoint = cortex_m_remove_breakpoint,
2673 .add_watchpoint = cortex_m_add_watchpoint,
2674 .remove_watchpoint = cortex_m_remove_watchpoint,
2675
2676 .commands = cortex_m_command_handlers,
2677 .target_create = cortex_m_target_create,
2678 .target_jim_configure = adiv5_jim_configure,
2679 .init_target = cortex_m_init_target,
2680 .examine = cortex_m_examine,
2681 .deinit_target = cortex_m_deinit_target,
2682
2683 .profiling = cortex_m_profiling,
2684 };
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