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target/cortex_m: simplify cortex_m_unset_breakpoint()
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_clear_halt(struct target *target)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 struct armv7m_common *armv7m = &cortex_m->armv7m;
143 int retval;
144
145 /* clear step if any */
146 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
147
148 /* Read Debug Fault Status Register */
149 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
150 if (retval != ERROR_OK)
151 return retval;
152
153 /* Clear Debug Fault Status */
154 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
155 if (retval != ERROR_OK)
156 return retval;
157 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
158
159 return ERROR_OK;
160 }
161
162 static int cortex_m_single_step_core(struct target *target)
163 {
164 struct cortex_m_common *cortex_m = target_to_cm(target);
165 struct armv7m_common *armv7m = &cortex_m->armv7m;
166 int retval;
167
168 /* Mask interrupts before clearing halt, if not done already. This avoids
169 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
170 * HALT can put the core into an unknown state.
171 */
172 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
174 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
175 if (retval != ERROR_OK)
176 return retval;
177 }
178 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
179 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
180 if (retval != ERROR_OK)
181 return retval;
182 LOG_DEBUG(" ");
183
184 /* restore dhcsr reg */
185 cortex_m_clear_halt(target);
186
187 return ERROR_OK;
188 }
189
190 static int cortex_m_enable_fpb(struct target *target)
191 {
192 int retval = target_write_u32(target, FP_CTRL, 3);
193 if (retval != ERROR_OK)
194 return retval;
195
196 /* check the fpb is actually enabled */
197 uint32_t fpctrl;
198 retval = target_read_u32(target, FP_CTRL, &fpctrl);
199 if (retval != ERROR_OK)
200 return retval;
201
202 if (fpctrl & 1)
203 return ERROR_OK;
204
205 return ERROR_FAIL;
206 }
207
208 static int cortex_m_endreset_event(struct target *target)
209 {
210 int i;
211 int retval;
212 uint32_t dcb_demcr;
213 struct cortex_m_common *cortex_m = target_to_cm(target);
214 struct armv7m_common *armv7m = &cortex_m->armv7m;
215 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
216 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
217 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
218
219 /* REVISIT The four debug monitor bits are currently ignored... */
220 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
221 if (retval != ERROR_OK)
222 return retval;
223 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
224
225 /* this register is used for emulated dcc channel */
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enable debug requests */
231 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
232 if (retval != ERROR_OK)
233 return retval;
234 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
235 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 /* Restore proper interrupt masking setting. */
241 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
242 cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
243 else
244 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
245
246 /* Enable features controlled by ITM and DWT blocks, and catch only
247 * the vectors we were told to pay attention to.
248 *
249 * Target firmware is responsible for all fault handling policy
250 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
251 * or manual updates to the NVIC SHCSR and CCR registers.
252 */
253 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
254 if (retval != ERROR_OK)
255 return retval;
256
257 /* Paranoia: evidently some (early?) chips don't preserve all the
258 * debug state (including FPB, DWT, etc) across reset...
259 */
260
261 /* Enable FPB */
262 retval = cortex_m_enable_fpb(target);
263 if (retval != ERROR_OK) {
264 LOG_ERROR("Failed to enable the FPB");
265 return retval;
266 }
267
268 cortex_m->fpb_enabled = true;
269
270 /* Restore FPB registers */
271 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
272 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
273 if (retval != ERROR_OK)
274 return retval;
275 }
276
277 /* Restore DWT registers */
278 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
279 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
280 dwt_list[i].comp);
281 if (retval != ERROR_OK)
282 return retval;
283 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
284 dwt_list[i].mask);
285 if (retval != ERROR_OK)
286 return retval;
287 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
288 dwt_list[i].function);
289 if (retval != ERROR_OK)
290 return retval;
291 }
292 retval = dap_run(swjdp);
293 if (retval != ERROR_OK)
294 return retval;
295
296 register_cache_invalidate(armv7m->arm.core_cache);
297
298 /* make sure we have latest dhcsr flags */
299 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
300
301 return retval;
302 }
303
304 static int cortex_m_examine_debug_reason(struct target *target)
305 {
306 struct cortex_m_common *cortex_m = target_to_cm(target);
307
308 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
309 * only check the debug reason if we don't know it already */
310
311 if ((target->debug_reason != DBG_REASON_DBGRQ)
312 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
313 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
314 target->debug_reason = DBG_REASON_BREAKPOINT;
315 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
316 target->debug_reason = DBG_REASON_WPTANDBKPT;
317 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
318 target->debug_reason = DBG_REASON_WATCHPOINT;
319 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
320 target->debug_reason = DBG_REASON_BREAKPOINT;
321 else /* EXTERNAL, HALTED */
322 target->debug_reason = DBG_REASON_UNDEFINED;
323 }
324
325 return ERROR_OK;
326 }
327
328 static int cortex_m_examine_exception_reason(struct target *target)
329 {
330 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
331 struct armv7m_common *armv7m = target_to_armv7m(target);
332 struct adiv5_dap *swjdp = armv7m->arm.dap;
333 int retval;
334
335 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
336 if (retval != ERROR_OK)
337 return retval;
338 switch (armv7m->exception_number) {
339 case 2: /* NMI */
340 break;
341 case 3: /* Hard Fault */
342 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
343 if (retval != ERROR_OK)
344 return retval;
345 if (except_sr & 0x40000000) {
346 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350 break;
351 case 4: /* Memory Management */
352 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
353 if (retval != ERROR_OK)
354 return retval;
355 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
356 if (retval != ERROR_OK)
357 return retval;
358 break;
359 case 5: /* Bus Fault */
360 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
361 if (retval != ERROR_OK)
362 return retval;
363 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
364 if (retval != ERROR_OK)
365 return retval;
366 break;
367 case 6: /* Usage Fault */
368 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
369 if (retval != ERROR_OK)
370 return retval;
371 break;
372 case 11: /* SVCall */
373 break;
374 case 12: /* Debug Monitor */
375 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
376 if (retval != ERROR_OK)
377 return retval;
378 break;
379 case 14: /* PendSV */
380 break;
381 case 15: /* SysTick */
382 break;
383 default:
384 except_sr = 0;
385 break;
386 }
387 retval = dap_run(swjdp);
388 if (retval == ERROR_OK)
389 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
390 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
391 armv7m_exception_string(armv7m->exception_number),
392 shcsr, except_sr, cfsr, except_ar);
393 return retval;
394 }
395
396 static int cortex_m_debug_entry(struct target *target)
397 {
398 int i;
399 uint32_t xPSR;
400 int retval;
401 struct cortex_m_common *cortex_m = target_to_cm(target);
402 struct armv7m_common *armv7m = &cortex_m->armv7m;
403 struct arm *arm = &armv7m->arm;
404 struct reg *r;
405
406 LOG_DEBUG(" ");
407
408 cortex_m_clear_halt(target);
409 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
410 if (retval != ERROR_OK)
411 return retval;
412
413 retval = armv7m->examine_debug_reason(target);
414 if (retval != ERROR_OK)
415 return retval;
416
417 /* Examine target state and mode
418 * First load register accessible through core debug port */
419 int num_regs = arm->core_cache->num_regs;
420
421 for (i = 0; i < num_regs; i++) {
422 r = &armv7m->arm.core_cache->reg_list[i];
423 if (!r->valid)
424 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
425 }
426
427 r = arm->cpsr;
428 xPSR = buf_get_u32(r->value, 0, 32);
429
430 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
431 if (xPSR & 0xf00) {
432 r->dirty = r->valid;
433 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
434 }
435
436 /* Are we in an exception handler */
437 if (xPSR & 0x1FF) {
438 armv7m->exception_number = (xPSR & 0x1FF);
439
440 arm->core_mode = ARM_MODE_HANDLER;
441 arm->map = armv7m_msp_reg_map;
442 } else {
443 unsigned control = buf_get_u32(arm->core_cache
444 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
445
446 /* is this thread privileged? */
447 arm->core_mode = control & 1
448 ? ARM_MODE_USER_THREAD
449 : ARM_MODE_THREAD;
450
451 /* which stack is it using? */
452 if (control & 2)
453 arm->map = armv7m_psp_reg_map;
454 else
455 arm->map = armv7m_msp_reg_map;
456
457 armv7m->exception_number = 0;
458 }
459
460 if (armv7m->exception_number)
461 cortex_m_examine_exception_reason(target);
462
463 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
464 arm_mode_name(arm->core_mode),
465 buf_get_u32(arm->pc->value, 0, 32),
466 target_state_name(target));
467
468 if (armv7m->post_debug_entry) {
469 retval = armv7m->post_debug_entry(target);
470 if (retval != ERROR_OK)
471 return retval;
472 }
473
474 return ERROR_OK;
475 }
476
477 static int cortex_m_poll(struct target *target)
478 {
479 int detected_failure = ERROR_OK;
480 int retval = ERROR_OK;
481 enum target_state prev_target_state = target->state;
482 struct cortex_m_common *cortex_m = target_to_cm(target);
483 struct armv7m_common *armv7m = &cortex_m->armv7m;
484
485 /* Read from Debug Halting Control and Status Register */
486 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
487 if (retval != ERROR_OK) {
488 target->state = TARGET_UNKNOWN;
489 return retval;
490 }
491
492 /* Recover from lockup. See ARMv7-M architecture spec,
493 * section B1.5.15 "Unrecoverable exception cases".
494 */
495 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
496 LOG_ERROR("%s -- clearing lockup after double fault",
497 target_name(target));
498 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
499 target->debug_reason = DBG_REASON_DBGRQ;
500
501 /* We have to execute the rest (the "finally" equivalent, but
502 * still throw this exception again).
503 */
504 detected_failure = ERROR_FAIL;
505
506 /* refresh status bits */
507 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
508 if (retval != ERROR_OK)
509 return retval;
510 }
511
512 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
513 if (target->state != TARGET_RESET) {
514 target->state = TARGET_RESET;
515 LOG_INFO("%s: external reset detected", target_name(target));
516 }
517 return ERROR_OK;
518 }
519
520 if (target->state == TARGET_RESET) {
521 /* Cannot switch context while running so endreset is
522 * called with target->state == TARGET_RESET
523 */
524 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
525 cortex_m->dcb_dhcsr);
526 retval = cortex_m_endreset_event(target);
527 if (retval != ERROR_OK) {
528 target->state = TARGET_UNKNOWN;
529 return retval;
530 }
531 target->state = TARGET_RUNNING;
532 prev_target_state = TARGET_RUNNING;
533 }
534
535 if (cortex_m->dcb_dhcsr & S_HALT) {
536 target->state = TARGET_HALTED;
537
538 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
539 retval = cortex_m_debug_entry(target);
540 if (retval != ERROR_OK)
541 return retval;
542
543 if (arm_semihosting(target, &retval) != 0)
544 return retval;
545
546 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
547 }
548 if (prev_target_state == TARGET_DEBUG_RUNNING) {
549 LOG_DEBUG(" ");
550 retval = cortex_m_debug_entry(target);
551 if (retval != ERROR_OK)
552 return retval;
553
554 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
555 }
556 }
557
558 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
559 * How best to model low power modes?
560 */
561
562 if (target->state == TARGET_UNKNOWN) {
563 /* check if processor is retiring instructions */
564 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
565 target->state = TARGET_RUNNING;
566 retval = ERROR_OK;
567 }
568 }
569
570 /* Check that target is truly halted, since the target could be resumed externally */
571 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
572 /* registers are now invalid */
573 register_cache_invalidate(armv7m->arm.core_cache);
574
575 target->state = TARGET_RUNNING;
576 LOG_WARNING("%s: external resume detected", target_name(target));
577 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
578 retval = ERROR_OK;
579 }
580
581 /* Did we detect a failure condition that we cleared? */
582 if (detected_failure != ERROR_OK)
583 retval = detected_failure;
584 return retval;
585 }
586
587 static int cortex_m_halt(struct target *target)
588 {
589 LOG_DEBUG("target->state: %s",
590 target_state_name(target));
591
592 if (target->state == TARGET_HALTED) {
593 LOG_DEBUG("target was already halted");
594 return ERROR_OK;
595 }
596
597 if (target->state == TARGET_UNKNOWN)
598 LOG_WARNING("target was in unknown state when halt was requested");
599
600 if (target->state == TARGET_RESET) {
601 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
602 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
603 return ERROR_TARGET_FAILURE;
604 } else {
605 /* we came here in a reset_halt or reset_init sequence
606 * debug entry was already prepared in cortex_m3_assert_reset()
607 */
608 target->debug_reason = DBG_REASON_DBGRQ;
609
610 return ERROR_OK;
611 }
612 }
613
614 /* Write to Debug Halting Control and Status Register */
615 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
616
617 target->debug_reason = DBG_REASON_DBGRQ;
618
619 return ERROR_OK;
620 }
621
622 static int cortex_m_soft_reset_halt(struct target *target)
623 {
624 struct cortex_m_common *cortex_m = target_to_cm(target);
625 struct armv7m_common *armv7m = &cortex_m->armv7m;
626 uint32_t dcb_dhcsr = 0;
627 int retval, timeout = 0;
628
629 /* soft_reset_halt is deprecated on cortex_m as the same functionality
630 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
631 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
632 * core, not the peripherals */
633 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
634
635 /* Enter debug state on reset; restore DEMCR in endreset_event() */
636 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
637 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
638 if (retval != ERROR_OK)
639 return retval;
640
641 /* Request a core-only reset */
642 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
643 AIRCR_VECTKEY | AIRCR_VECTRESET);
644 if (retval != ERROR_OK)
645 return retval;
646 target->state = TARGET_RESET;
647
648 /* registers are now invalid */
649 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
650
651 while (timeout < 100) {
652 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
653 if (retval == ERROR_OK) {
654 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
655 &cortex_m->nvic_dfsr);
656 if (retval != ERROR_OK)
657 return retval;
658 if ((dcb_dhcsr & S_HALT)
659 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
660 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
661 "DFSR 0x%08x",
662 (unsigned) dcb_dhcsr,
663 (unsigned) cortex_m->nvic_dfsr);
664 cortex_m_poll(target);
665 /* FIXME restore user's vector catch config */
666 return ERROR_OK;
667 } else
668 LOG_DEBUG("waiting for system reset-halt, "
669 "DHCSR 0x%08x, %d ms",
670 (unsigned) dcb_dhcsr, timeout);
671 }
672 timeout++;
673 alive_sleep(1);
674 }
675
676 return ERROR_OK;
677 }
678
679 void cortex_m_enable_breakpoints(struct target *target)
680 {
681 struct breakpoint *breakpoint = target->breakpoints;
682
683 /* set any pending breakpoints */
684 while (breakpoint) {
685 if (!breakpoint->set)
686 cortex_m_set_breakpoint(target, breakpoint);
687 breakpoint = breakpoint->next;
688 }
689 }
690
691 static int cortex_m_resume(struct target *target, int current,
692 target_addr_t address, int handle_breakpoints, int debug_execution)
693 {
694 struct armv7m_common *armv7m = target_to_armv7m(target);
695 struct breakpoint *breakpoint = NULL;
696 uint32_t resume_pc;
697 struct reg *r;
698
699 if (target->state != TARGET_HALTED) {
700 LOG_WARNING("target not halted");
701 return ERROR_TARGET_NOT_HALTED;
702 }
703
704 if (!debug_execution) {
705 target_free_all_working_areas(target);
706 cortex_m_enable_breakpoints(target);
707 cortex_m_enable_watchpoints(target);
708 }
709
710 if (debug_execution) {
711 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
712
713 /* Disable interrupts */
714 /* We disable interrupts in the PRIMASK register instead of
715 * masking with C_MASKINTS. This is probably the same issue
716 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
717 * in parallel with disabled interrupts can cause local faults
718 * to not be taken.
719 *
720 * REVISIT this clearly breaks non-debug execution, since the
721 * PRIMASK register state isn't saved/restored... workaround
722 * by never resuming app code after debug execution.
723 */
724 buf_set_u32(r->value, 0, 1, 1);
725 r->dirty = true;
726 r->valid = true;
727
728 /* Make sure we are in Thumb mode */
729 r = armv7m->arm.cpsr;
730 buf_set_u32(r->value, 24, 1, 1);
731 r->dirty = true;
732 r->valid = true;
733 }
734
735 /* current = 1: continue on current pc, otherwise continue at <address> */
736 r = armv7m->arm.pc;
737 if (!current) {
738 buf_set_u32(r->value, 0, 32, address);
739 r->dirty = true;
740 r->valid = true;
741 }
742
743 /* if we halted last time due to a bkpt instruction
744 * then we have to manually step over it, otherwise
745 * the core will break again */
746
747 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
748 && !debug_execution)
749 armv7m_maybe_skip_bkpt_inst(target, NULL);
750
751 resume_pc = buf_get_u32(r->value, 0, 32);
752
753 armv7m_restore_context(target);
754
755 /* the front-end may request us not to handle breakpoints */
756 if (handle_breakpoints) {
757 /* Single step past breakpoint at current address */
758 breakpoint = breakpoint_find(target, resume_pc);
759 if (breakpoint) {
760 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
761 breakpoint->address,
762 breakpoint->unique_id);
763 cortex_m_unset_breakpoint(target, breakpoint);
764 cortex_m_single_step_core(target);
765 cortex_m_set_breakpoint(target, breakpoint);
766 }
767 }
768
769 /* Restart core */
770 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
771
772 target->debug_reason = DBG_REASON_NOTHALTED;
773
774 /* registers are now invalid */
775 register_cache_invalidate(armv7m->arm.core_cache);
776
777 if (!debug_execution) {
778 target->state = TARGET_RUNNING;
779 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
780 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
781 } else {
782 target->state = TARGET_DEBUG_RUNNING;
783 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
784 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
785 }
786
787 return ERROR_OK;
788 }
789
790 /* int irqstepcount = 0; */
791 static int cortex_m_step(struct target *target, int current,
792 target_addr_t address, int handle_breakpoints)
793 {
794 struct cortex_m_common *cortex_m = target_to_cm(target);
795 struct armv7m_common *armv7m = &cortex_m->armv7m;
796 struct breakpoint *breakpoint = NULL;
797 struct reg *pc = armv7m->arm.pc;
798 bool bkpt_inst_found = false;
799 int retval;
800 bool isr_timed_out = false;
801
802 if (target->state != TARGET_HALTED) {
803 LOG_WARNING("target not halted");
804 return ERROR_TARGET_NOT_HALTED;
805 }
806
807 /* current = 1: continue on current pc, otherwise continue at <address> */
808 if (!current)
809 buf_set_u32(pc->value, 0, 32, address);
810
811 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
812
813 /* the front-end may request us not to handle breakpoints */
814 if (handle_breakpoints) {
815 breakpoint = breakpoint_find(target, pc_value);
816 if (breakpoint)
817 cortex_m_unset_breakpoint(target, breakpoint);
818 }
819
820 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
821
822 target->debug_reason = DBG_REASON_SINGLESTEP;
823
824 armv7m_restore_context(target);
825
826 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
827
828 /* if no bkpt instruction is found at pc then we can perform
829 * a normal step, otherwise we have to manually step over the bkpt
830 * instruction - as such simulate a step */
831 if (bkpt_inst_found == false) {
832 /* Automatic ISR masking mode off: Just step over the next instruction */
833 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
834 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
835 else {
836 /* Process interrupts during stepping in a way they don't interfere
837 * debugging.
838 *
839 * Principle:
840 *
841 * Set a temporary break point at the current pc and let the core run
842 * with interrupts enabled. Pending interrupts get served and we run
843 * into the breakpoint again afterwards. Then we step over the next
844 * instruction with interrupts disabled.
845 *
846 * If the pending interrupts don't complete within time, we leave the
847 * core running. This may happen if the interrupts trigger faster
848 * than the core can process them or the handler doesn't return.
849 *
850 * If no more breakpoints are available we simply do a step with
851 * interrupts enabled.
852 *
853 */
854
855 /* 2012-09-29 ph
856 *
857 * If a break point is already set on the lower half word then a break point on
858 * the upper half word will not break again when the core is restarted. So we
859 * just step over the instruction with interrupts disabled.
860 *
861 * The documentation has no information about this, it was found by observation
862 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
863 * suffer from this problem.
864 *
865 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
866 * address has it always cleared. The former is done to indicate thumb mode
867 * to gdb.
868 *
869 */
870 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
871 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
872 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
873 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
874 /* Re-enable interrupts */
875 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
876 }
877 else {
878
879 /* Set a temporary break point */
880 if (breakpoint) {
881 retval = cortex_m_set_breakpoint(target, breakpoint);
882 } else {
883 enum breakpoint_type type = BKPT_HARD;
884 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
885 /* FPB rev.1 cannot handle such addr, try BKPT instr */
886 type = BKPT_SOFT;
887 }
888 retval = breakpoint_add(target, pc_value, 2, type);
889 }
890
891 bool tmp_bp_set = (retval == ERROR_OK);
892
893 /* No more breakpoints left, just do a step */
894 if (!tmp_bp_set)
895 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
896 else {
897 /* Start the core */
898 LOG_DEBUG("Starting core to serve pending interrupts");
899 int64_t t_start = timeval_ms();
900 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
901
902 /* Wait for pending handlers to complete or timeout */
903 do {
904 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
905 DCB_DHCSR,
906 &cortex_m->dcb_dhcsr);
907 if (retval != ERROR_OK) {
908 target->state = TARGET_UNKNOWN;
909 return retval;
910 }
911 isr_timed_out = ((timeval_ms() - t_start) > 500);
912 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
913
914 /* only remove breakpoint if we created it */
915 if (breakpoint)
916 cortex_m_unset_breakpoint(target, breakpoint);
917 else {
918 /* Remove the temporary breakpoint */
919 breakpoint_remove(target, pc_value);
920 }
921
922 if (isr_timed_out) {
923 LOG_DEBUG("Interrupt handlers didn't complete within time, "
924 "leaving target running");
925 } else {
926 /* Step over next instruction with interrupts disabled */
927 cortex_m_write_debug_halt_mask(target,
928 C_HALT | C_MASKINTS,
929 0);
930 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
931 /* Re-enable interrupts */
932 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
933 }
934 }
935 }
936 }
937 }
938
939 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
940 if (retval != ERROR_OK)
941 return retval;
942
943 /* registers are now invalid */
944 register_cache_invalidate(armv7m->arm.core_cache);
945
946 if (breakpoint)
947 cortex_m_set_breakpoint(target, breakpoint);
948
949 if (isr_timed_out) {
950 /* Leave the core running. The user has to stop execution manually. */
951 target->debug_reason = DBG_REASON_NOTHALTED;
952 target->state = TARGET_RUNNING;
953 return ERROR_OK;
954 }
955
956 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
957 " nvic_icsr = 0x%" PRIx32,
958 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
959
960 retval = cortex_m_debug_entry(target);
961 if (retval != ERROR_OK)
962 return retval;
963 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
964
965 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
966 " nvic_icsr = 0x%" PRIx32,
967 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
968
969 return ERROR_OK;
970 }
971
972 static int cortex_m_assert_reset(struct target *target)
973 {
974 struct cortex_m_common *cortex_m = target_to_cm(target);
975 struct armv7m_common *armv7m = &cortex_m->armv7m;
976 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
977
978 LOG_DEBUG("target->state: %s",
979 target_state_name(target));
980
981 enum reset_types jtag_reset_config = jtag_get_reset_config();
982
983 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
984 /* allow scripts to override the reset event */
985
986 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
987 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
988 target->state = TARGET_RESET;
989
990 return ERROR_OK;
991 }
992
993 /* some cores support connecting while srst is asserted
994 * use that mode is it has been configured */
995
996 bool srst_asserted = false;
997
998 if (!target_was_examined(target)) {
999 if (jtag_reset_config & RESET_HAS_SRST) {
1000 adapter_assert_reset();
1001 if (target->reset_halt)
1002 LOG_ERROR("Target not examined, will not halt after reset!");
1003 return ERROR_OK;
1004 } else {
1005 LOG_ERROR("Target not examined, reset NOT asserted!");
1006 return ERROR_FAIL;
1007 }
1008 }
1009
1010 if ((jtag_reset_config & RESET_HAS_SRST) &&
1011 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1012 adapter_assert_reset();
1013 srst_asserted = true;
1014 }
1015
1016 /* Enable debug requests */
1017 int retval;
1018 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1019 /* Store important errors instead of failing and proceed to reset assert */
1020
1021 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1022 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1023
1024 /* If the processor is sleeping in a WFI or WFE instruction, the
1025 * C_HALT bit must be asserted to regain control */
1026 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1027 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1028
1029 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1030 /* Ignore less important errors */
1031
1032 if (!target->reset_halt) {
1033 /* Set/Clear C_MASKINTS in a separate operation */
1034 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1035 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1036
1037 /* clear any debug flags before resuming */
1038 cortex_m_clear_halt(target);
1039
1040 /* clear C_HALT in dhcsr reg */
1041 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1042 } else {
1043 /* Halt in debug on reset; endreset_event() restores DEMCR.
1044 *
1045 * REVISIT catching BUSERR presumably helps to defend against
1046 * bad vector table entries. Should this include MMERR or
1047 * other flags too?
1048 */
1049 int retval2;
1050 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1051 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1052 if (retval != ERROR_OK || retval2 != ERROR_OK)
1053 LOG_INFO("AP write error, reset will not halt");
1054 }
1055
1056 if (jtag_reset_config & RESET_HAS_SRST) {
1057 /* default to asserting srst */
1058 if (!srst_asserted)
1059 adapter_assert_reset();
1060
1061 /* srst is asserted, ignore AP access errors */
1062 retval = ERROR_OK;
1063 } else {
1064 /* Use a standard Cortex-M3 software reset mechanism.
1065 * We default to using VECRESET as it is supported on all current cores
1066 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1067 * This has the disadvantage of not resetting the peripherals, so a
1068 * reset-init event handler is needed to perform any peripheral resets.
1069 */
1070 if (!cortex_m->vectreset_supported
1071 && reset_config == CORTEX_M_RESET_VECTRESET) {
1072 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1073 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1074 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1075 }
1076
1077 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1078 ? "SYSRESETREQ" : "VECTRESET");
1079
1080 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1081 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1082 "handler to reset any peripherals or configure hardware srst support.");
1083 }
1084
1085 int retval3;
1086 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1087 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1088 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1089 if (retval3 != ERROR_OK)
1090 LOG_DEBUG("Ignoring AP write error right after reset");
1091
1092 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1093 if (retval3 != ERROR_OK)
1094 LOG_ERROR("DP initialisation failed");
1095
1096 else {
1097 /* I do not know why this is necessary, but it
1098 * fixes strange effects (step/resume cause NMI
1099 * after reset) on LM3S6918 -- Michael Schwingen
1100 */
1101 uint32_t tmp;
1102 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1103 }
1104 }
1105
1106 target->state = TARGET_RESET;
1107 jtag_add_sleep(50000);
1108
1109 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1110
1111 /* now return stored error code if any */
1112 if (retval != ERROR_OK)
1113 return retval;
1114
1115 if (target->reset_halt) {
1116 retval = target_halt(target);
1117 if (retval != ERROR_OK)
1118 return retval;
1119 }
1120
1121 return ERROR_OK;
1122 }
1123
1124 static int cortex_m_deassert_reset(struct target *target)
1125 {
1126 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1127
1128 LOG_DEBUG("target->state: %s",
1129 target_state_name(target));
1130
1131 /* deassert reset lines */
1132 adapter_deassert_reset();
1133
1134 enum reset_types jtag_reset_config = jtag_get_reset_config();
1135
1136 if ((jtag_reset_config & RESET_HAS_SRST) &&
1137 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1138 target_was_examined(target)) {
1139 int retval = dap_dp_init(armv7m->debug_ap->dap);
1140 if (retval != ERROR_OK) {
1141 LOG_ERROR("DP initialisation failed");
1142 return retval;
1143 }
1144 }
1145
1146 return ERROR_OK;
1147 }
1148
1149 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1150 {
1151 int retval;
1152 int fp_num = 0;
1153 struct cortex_m_common *cortex_m = target_to_cm(target);
1154 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1155
1156 if (breakpoint->set) {
1157 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1158 return ERROR_OK;
1159 }
1160
1161 if (breakpoint->type == BKPT_HARD) {
1162 uint32_t fpcr_value;
1163 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1164 fp_num++;
1165 if (fp_num >= cortex_m->fp_num_code) {
1166 LOG_ERROR("Can not find free FPB Comparator!");
1167 return ERROR_FAIL;
1168 }
1169 breakpoint->set = fp_num + 1;
1170 fpcr_value = breakpoint->address | 1;
1171 if (cortex_m->fp_rev == 0) {
1172 if (breakpoint->address > 0x1FFFFFFF) {
1173 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1174 return ERROR_FAIL;
1175 }
1176 uint32_t hilo;
1177 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1178 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1179 } else if (cortex_m->fp_rev > 1) {
1180 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1181 return ERROR_FAIL;
1182 }
1183 comparator_list[fp_num].used = true;
1184 comparator_list[fp_num].fpcr_value = fpcr_value;
1185 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1186 comparator_list[fp_num].fpcr_value);
1187 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1188 fp_num,
1189 comparator_list[fp_num].fpcr_value);
1190 if (!cortex_m->fpb_enabled) {
1191 LOG_DEBUG("FPB wasn't enabled, do it now");
1192 retval = cortex_m_enable_fpb(target);
1193 if (retval != ERROR_OK) {
1194 LOG_ERROR("Failed to enable the FPB");
1195 return retval;
1196 }
1197
1198 cortex_m->fpb_enabled = true;
1199 }
1200 } else if (breakpoint->type == BKPT_SOFT) {
1201 uint8_t code[4];
1202
1203 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1204 * semihosting; don't use that. Otherwise the BKPT
1205 * parameter is arbitrary.
1206 */
1207 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1208 retval = target_read_memory(target,
1209 breakpoint->address & 0xFFFFFFFE,
1210 breakpoint->length, 1,
1211 breakpoint->orig_instr);
1212 if (retval != ERROR_OK)
1213 return retval;
1214 retval = target_write_memory(target,
1215 breakpoint->address & 0xFFFFFFFE,
1216 breakpoint->length, 1,
1217 code);
1218 if (retval != ERROR_OK)
1219 return retval;
1220 breakpoint->set = true;
1221 }
1222
1223 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1224 breakpoint->unique_id,
1225 (int)(breakpoint->type),
1226 breakpoint->address,
1227 breakpoint->length,
1228 breakpoint->set);
1229
1230 return ERROR_OK;
1231 }
1232
1233 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1234 {
1235 int retval;
1236 struct cortex_m_common *cortex_m = target_to_cm(target);
1237 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1238
1239 if (!breakpoint->set) {
1240 LOG_WARNING("breakpoint not set");
1241 return ERROR_OK;
1242 }
1243
1244 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1245 breakpoint->unique_id,
1246 (int)(breakpoint->type),
1247 breakpoint->address,
1248 breakpoint->length,
1249 breakpoint->set);
1250
1251 if (breakpoint->type == BKPT_HARD) {
1252 int fp_num = breakpoint->set - 1;
1253 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1254 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1255 return ERROR_OK;
1256 }
1257 comparator_list[fp_num].used = false;
1258 comparator_list[fp_num].fpcr_value = 0;
1259 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1260 comparator_list[fp_num].fpcr_value);
1261 } else {
1262 /* restore original instruction (kept in target endianness) */
1263 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1264 breakpoint->length, 1,
1265 breakpoint->orig_instr);
1266 if (retval != ERROR_OK)
1267 return retval;
1268 }
1269 breakpoint->set = false;
1270
1271 return ERROR_OK;
1272 }
1273
1274 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1275 {
1276 struct cortex_m_common *cortex_m = target_to_cm(target);
1277
1278 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1279 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1280 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1281 }
1282
1283 if (breakpoint->length == 3) {
1284 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1285 breakpoint->length = 2;
1286 }
1287
1288 if ((breakpoint->length != 2)) {
1289 LOG_INFO("only breakpoints of two bytes length supported");
1290 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1291 }
1292
1293 if (breakpoint->type == BKPT_HARD)
1294 cortex_m->fp_code_available--;
1295
1296 return cortex_m_set_breakpoint(target, breakpoint);
1297 }
1298
1299 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1300 {
1301 struct cortex_m_common *cortex_m = target_to_cm(target);
1302
1303 /* REVISIT why check? FPB can be updated with core running ... */
1304 if (target->state != TARGET_HALTED) {
1305 LOG_WARNING("target not halted");
1306 return ERROR_TARGET_NOT_HALTED;
1307 }
1308
1309 if (breakpoint->set)
1310 cortex_m_unset_breakpoint(target, breakpoint);
1311
1312 if (breakpoint->type == BKPT_HARD)
1313 cortex_m->fp_code_available++;
1314
1315 return ERROR_OK;
1316 }
1317
1318 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1319 {
1320 int dwt_num = 0;
1321 uint32_t mask, temp;
1322 struct cortex_m_common *cortex_m = target_to_cm(target);
1323
1324 /* watchpoint params were validated earlier */
1325 mask = 0;
1326 temp = watchpoint->length;
1327 while (temp) {
1328 temp >>= 1;
1329 mask++;
1330 }
1331 mask--;
1332
1333 /* REVISIT Don't fully trust these "not used" records ... users
1334 * may set up breakpoints by hand, e.g. dual-address data value
1335 * watchpoint using comparator #1; comparator #0 matching cycle
1336 * count; send data trace info through ITM and TPIU; etc
1337 */
1338 struct cortex_m_dwt_comparator *comparator;
1339
1340 for (comparator = cortex_m->dwt_comparator_list;
1341 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1342 comparator++, dwt_num++)
1343 continue;
1344 if (dwt_num >= cortex_m->dwt_num_comp) {
1345 LOG_ERROR("Can not find free DWT Comparator");
1346 return ERROR_FAIL;
1347 }
1348 comparator->used = true;
1349 watchpoint->set = dwt_num + 1;
1350
1351 comparator->comp = watchpoint->address;
1352 target_write_u32(target, comparator->dwt_comparator_address + 0,
1353 comparator->comp);
1354
1355 comparator->mask = mask;
1356 target_write_u32(target, comparator->dwt_comparator_address + 4,
1357 comparator->mask);
1358
1359 switch (watchpoint->rw) {
1360 case WPT_READ:
1361 comparator->function = 5;
1362 break;
1363 case WPT_WRITE:
1364 comparator->function = 6;
1365 break;
1366 case WPT_ACCESS:
1367 comparator->function = 7;
1368 break;
1369 }
1370 target_write_u32(target, comparator->dwt_comparator_address + 8,
1371 comparator->function);
1372
1373 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1374 watchpoint->unique_id, dwt_num,
1375 (unsigned) comparator->comp,
1376 (unsigned) comparator->mask,
1377 (unsigned) comparator->function);
1378 return ERROR_OK;
1379 }
1380
1381 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1382 {
1383 struct cortex_m_common *cortex_m = target_to_cm(target);
1384 struct cortex_m_dwt_comparator *comparator;
1385 int dwt_num;
1386
1387 if (!watchpoint->set) {
1388 LOG_WARNING("watchpoint (wpid: %d) not set",
1389 watchpoint->unique_id);
1390 return ERROR_OK;
1391 }
1392
1393 dwt_num = watchpoint->set - 1;
1394
1395 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1396 watchpoint->unique_id, dwt_num,
1397 (unsigned) watchpoint->address);
1398
1399 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1400 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1401 return ERROR_OK;
1402 }
1403
1404 comparator = cortex_m->dwt_comparator_list + dwt_num;
1405 comparator->used = false;
1406 comparator->function = 0;
1407 target_write_u32(target, comparator->dwt_comparator_address + 8,
1408 comparator->function);
1409
1410 watchpoint->set = false;
1411
1412 return ERROR_OK;
1413 }
1414
1415 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1416 {
1417 struct cortex_m_common *cortex_m = target_to_cm(target);
1418
1419 if (cortex_m->dwt_comp_available < 1) {
1420 LOG_DEBUG("no comparators?");
1421 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1422 }
1423
1424 /* hardware doesn't support data value masking */
1425 if (watchpoint->mask != ~(uint32_t)0) {
1426 LOG_DEBUG("watchpoint value masks not supported");
1427 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1428 }
1429
1430 /* hardware allows address masks of up to 32K */
1431 unsigned mask;
1432
1433 for (mask = 0; mask < 16; mask++) {
1434 if ((1u << mask) == watchpoint->length)
1435 break;
1436 }
1437 if (mask == 16) {
1438 LOG_DEBUG("unsupported watchpoint length");
1439 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1440 }
1441 if (watchpoint->address & ((1 << mask) - 1)) {
1442 LOG_DEBUG("watchpoint address is unaligned");
1443 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1444 }
1445
1446 /* Caller doesn't seem to be able to describe watching for data
1447 * values of zero; that flags "no value".
1448 *
1449 * REVISIT This DWT may well be able to watch for specific data
1450 * values. Requires comparator #1 to set DATAVMATCH and match
1451 * the data, and another comparator (DATAVADDR0) matching addr.
1452 */
1453 if (watchpoint->value) {
1454 LOG_DEBUG("data value watchpoint not YET supported");
1455 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1456 }
1457
1458 cortex_m->dwt_comp_available--;
1459 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1460
1461 return ERROR_OK;
1462 }
1463
1464 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1465 {
1466 struct cortex_m_common *cortex_m = target_to_cm(target);
1467
1468 /* REVISIT why check? DWT can be updated with core running ... */
1469 if (target->state != TARGET_HALTED) {
1470 LOG_WARNING("target not halted");
1471 return ERROR_TARGET_NOT_HALTED;
1472 }
1473
1474 if (watchpoint->set)
1475 cortex_m_unset_watchpoint(target, watchpoint);
1476
1477 cortex_m->dwt_comp_available++;
1478 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1479
1480 return ERROR_OK;
1481 }
1482
1483 void cortex_m_enable_watchpoints(struct target *target)
1484 {
1485 struct watchpoint *watchpoint = target->watchpoints;
1486
1487 /* set any pending watchpoints */
1488 while (watchpoint) {
1489 if (!watchpoint->set)
1490 cortex_m_set_watchpoint(target, watchpoint);
1491 watchpoint = watchpoint->next;
1492 }
1493 }
1494
1495 static int cortex_m_load_core_reg_u32(struct target *target,
1496 uint32_t num, uint32_t *value)
1497 {
1498 int retval;
1499
1500 /* NOTE: we "know" here that the register identifiers used
1501 * in the v7m header match the Cortex-M3 Debug Core Register
1502 * Selector values for R0..R15, xPSR, MSP, and PSP.
1503 */
1504 switch (num) {
1505 case 0 ... 18:
1506 /* read a normal core register */
1507 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1508
1509 if (retval != ERROR_OK) {
1510 LOG_ERROR("JTAG failure %i", retval);
1511 return ERROR_JTAG_DEVICE_ERROR;
1512 }
1513 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1514 break;
1515
1516 case ARMV7M_FPSCR:
1517 /* Floating-point Status and Registers */
1518 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1519 if (retval != ERROR_OK)
1520 return retval;
1521 retval = target_read_u32(target, DCB_DCRDR, value);
1522 if (retval != ERROR_OK)
1523 return retval;
1524 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1525 break;
1526
1527 case ARMV7M_S0 ... ARMV7M_S31:
1528 /* Floating-point Status and Registers */
1529 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1530 if (retval != ERROR_OK)
1531 return retval;
1532 retval = target_read_u32(target, DCB_DCRDR, value);
1533 if (retval != ERROR_OK)
1534 return retval;
1535 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1536 (int)(num - ARMV7M_S0), *value);
1537 break;
1538
1539 case ARMV7M_PRIMASK:
1540 case ARMV7M_BASEPRI:
1541 case ARMV7M_FAULTMASK:
1542 case ARMV7M_CONTROL:
1543 /* Cortex-M3 packages these four registers as bitfields
1544 * in one Debug Core register. So say r0 and r2 docs;
1545 * it was removed from r1 docs, but still works.
1546 */
1547 cortexm_dap_read_coreregister_u32(target, value, 20);
1548
1549 switch (num) {
1550 case ARMV7M_PRIMASK:
1551 *value = buf_get_u32((uint8_t *)value, 0, 1);
1552 break;
1553
1554 case ARMV7M_BASEPRI:
1555 *value = buf_get_u32((uint8_t *)value, 8, 8);
1556 break;
1557
1558 case ARMV7M_FAULTMASK:
1559 *value = buf_get_u32((uint8_t *)value, 16, 1);
1560 break;
1561
1562 case ARMV7M_CONTROL:
1563 *value = buf_get_u32((uint8_t *)value, 24, 2);
1564 break;
1565 }
1566
1567 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1568 break;
1569
1570 default:
1571 return ERROR_COMMAND_SYNTAX_ERROR;
1572 }
1573
1574 return ERROR_OK;
1575 }
1576
1577 static int cortex_m_store_core_reg_u32(struct target *target,
1578 uint32_t num, uint32_t value)
1579 {
1580 int retval;
1581 uint32_t reg;
1582 struct armv7m_common *armv7m = target_to_armv7m(target);
1583
1584 /* NOTE: we "know" here that the register identifiers used
1585 * in the v7m header match the Cortex-M3 Debug Core Register
1586 * Selector values for R0..R15, xPSR, MSP, and PSP.
1587 */
1588 switch (num) {
1589 case 0 ... 18:
1590 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1591 if (retval != ERROR_OK) {
1592 struct reg *r;
1593
1594 LOG_ERROR("JTAG failure");
1595 r = armv7m->arm.core_cache->reg_list + num;
1596 r->dirty = r->valid;
1597 return ERROR_JTAG_DEVICE_ERROR;
1598 }
1599 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1600 break;
1601
1602 case ARMV7M_FPSCR:
1603 /* Floating-point Status and Registers */
1604 retval = target_write_u32(target, DCB_DCRDR, value);
1605 if (retval != ERROR_OK)
1606 return retval;
1607 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1608 if (retval != ERROR_OK)
1609 return retval;
1610 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1611 break;
1612
1613 case ARMV7M_S0 ... ARMV7M_S31:
1614 /* Floating-point Status and Registers */
1615 retval = target_write_u32(target, DCB_DCRDR, value);
1616 if (retval != ERROR_OK)
1617 return retval;
1618 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1619 if (retval != ERROR_OK)
1620 return retval;
1621 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1622 (int)(num - ARMV7M_S0), value);
1623 break;
1624
1625 case ARMV7M_PRIMASK:
1626 case ARMV7M_BASEPRI:
1627 case ARMV7M_FAULTMASK:
1628 case ARMV7M_CONTROL:
1629 /* Cortex-M3 packages these four registers as bitfields
1630 * in one Debug Core register. So say r0 and r2 docs;
1631 * it was removed from r1 docs, but still works.
1632 */
1633 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1634
1635 switch (num) {
1636 case ARMV7M_PRIMASK:
1637 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1638 break;
1639
1640 case ARMV7M_BASEPRI:
1641 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1642 break;
1643
1644 case ARMV7M_FAULTMASK:
1645 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1646 break;
1647
1648 case ARMV7M_CONTROL:
1649 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1650 break;
1651 }
1652
1653 cortexm_dap_write_coreregister_u32(target, reg, 20);
1654
1655 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1656 break;
1657
1658 default:
1659 return ERROR_COMMAND_SYNTAX_ERROR;
1660 }
1661
1662 return ERROR_OK;
1663 }
1664
1665 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1666 uint32_t size, uint32_t count, uint8_t *buffer)
1667 {
1668 struct armv7m_common *armv7m = target_to_armv7m(target);
1669
1670 if (armv7m->arm.is_armv6m) {
1671 /* armv6m does not handle unaligned memory access */
1672 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1673 return ERROR_TARGET_UNALIGNED_ACCESS;
1674 }
1675
1676 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1677 }
1678
1679 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1680 uint32_t size, uint32_t count, const uint8_t *buffer)
1681 {
1682 struct armv7m_common *armv7m = target_to_armv7m(target);
1683
1684 if (armv7m->arm.is_armv6m) {
1685 /* armv6m does not handle unaligned memory access */
1686 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1687 return ERROR_TARGET_UNALIGNED_ACCESS;
1688 }
1689
1690 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1691 }
1692
1693 static int cortex_m_init_target(struct command_context *cmd_ctx,
1694 struct target *target)
1695 {
1696 armv7m_build_reg_cache(target);
1697 arm_semihosting_init(target);
1698 return ERROR_OK;
1699 }
1700
1701 void cortex_m_deinit_target(struct target *target)
1702 {
1703 struct cortex_m_common *cortex_m = target_to_cm(target);
1704
1705 free(cortex_m->fp_comparator_list);
1706
1707 cortex_m_dwt_free(target);
1708 armv7m_free_reg_cache(target);
1709
1710 free(target->private_config);
1711 free(cortex_m);
1712 }
1713
1714 int cortex_m_profiling(struct target *target, uint32_t *samples,
1715 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1716 {
1717 struct timeval timeout, now;
1718 struct armv7m_common *armv7m = target_to_armv7m(target);
1719 uint32_t reg_value;
1720 bool use_pcsr = false;
1721 int retval = ERROR_OK;
1722 struct reg *reg;
1723
1724 gettimeofday(&timeout, NULL);
1725 timeval_add_time(&timeout, seconds, 0);
1726
1727 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1728 if (retval != ERROR_OK) {
1729 LOG_ERROR("Error while reading PCSR");
1730 return retval;
1731 }
1732
1733 if (reg_value != 0) {
1734 use_pcsr = true;
1735 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1736 } else {
1737 LOG_INFO("Starting profiling. Halting and resuming the"
1738 " target as often as we can...");
1739 reg = register_get_by_name(target->reg_cache, "pc", 1);
1740 }
1741
1742 /* Make sure the target is running */
1743 target_poll(target);
1744 if (target->state == TARGET_HALTED)
1745 retval = target_resume(target, 1, 0, 0, 0);
1746
1747 if (retval != ERROR_OK) {
1748 LOG_ERROR("Error while resuming target");
1749 return retval;
1750 }
1751
1752 uint32_t sample_count = 0;
1753
1754 for (;;) {
1755 if (use_pcsr) {
1756 if (armv7m && armv7m->debug_ap) {
1757 uint32_t read_count = max_num_samples - sample_count;
1758 if (read_count > 1024)
1759 read_count = 1024;
1760
1761 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1762 (void *)&samples[sample_count],
1763 4, read_count, DWT_PCSR);
1764 sample_count += read_count;
1765 } else {
1766 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1767 }
1768 } else {
1769 target_poll(target);
1770 if (target->state == TARGET_HALTED) {
1771 reg_value = buf_get_u32(reg->value, 0, 32);
1772 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1773 retval = target_resume(target, 1, 0, 0, 0);
1774 samples[sample_count++] = reg_value;
1775 target_poll(target);
1776 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1777 } else if (target->state == TARGET_RUNNING) {
1778 /* We want to quickly sample the PC. */
1779 retval = target_halt(target);
1780 } else {
1781 LOG_INFO("Target not halted or running");
1782 retval = ERROR_OK;
1783 break;
1784 }
1785 }
1786
1787 if (retval != ERROR_OK) {
1788 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1789 return retval;
1790 }
1791
1792
1793 gettimeofday(&now, NULL);
1794 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1795 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1796 break;
1797 }
1798 }
1799
1800 *num_samples = sample_count;
1801 return retval;
1802 }
1803
1804
1805 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1806 * on r/w if the core is not running, and clear on resume or reset ... or
1807 * at least, in a post_restore_context() method.
1808 */
1809
1810 struct dwt_reg_state {
1811 struct target *target;
1812 uint32_t addr;
1813 uint8_t value[4]; /* scratch/cache */
1814 };
1815
1816 static int cortex_m_dwt_get_reg(struct reg *reg)
1817 {
1818 struct dwt_reg_state *state = reg->arch_info;
1819
1820 uint32_t tmp;
1821 int retval = target_read_u32(state->target, state->addr, &tmp);
1822 if (retval != ERROR_OK)
1823 return retval;
1824
1825 buf_set_u32(state->value, 0, 32, tmp);
1826 return ERROR_OK;
1827 }
1828
1829 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1830 {
1831 struct dwt_reg_state *state = reg->arch_info;
1832
1833 return target_write_u32(state->target, state->addr,
1834 buf_get_u32(buf, 0, reg->size));
1835 }
1836
1837 struct dwt_reg {
1838 uint32_t addr;
1839 const char *name;
1840 unsigned size;
1841 };
1842
1843 static const struct dwt_reg dwt_base_regs[] = {
1844 { DWT_CTRL, "dwt_ctrl", 32, },
1845 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1846 * increments while the core is asleep.
1847 */
1848 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1849 /* plus some 8 bit counters, useful for profiling with TPIU */
1850 };
1851
1852 static const struct dwt_reg dwt_comp[] = {
1853 #define DWT_COMPARATOR(i) \
1854 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1855 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1856 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1857 DWT_COMPARATOR(0),
1858 DWT_COMPARATOR(1),
1859 DWT_COMPARATOR(2),
1860 DWT_COMPARATOR(3),
1861 DWT_COMPARATOR(4),
1862 DWT_COMPARATOR(5),
1863 DWT_COMPARATOR(6),
1864 DWT_COMPARATOR(7),
1865 DWT_COMPARATOR(8),
1866 DWT_COMPARATOR(9),
1867 DWT_COMPARATOR(10),
1868 DWT_COMPARATOR(11),
1869 DWT_COMPARATOR(12),
1870 DWT_COMPARATOR(13),
1871 DWT_COMPARATOR(14),
1872 DWT_COMPARATOR(15),
1873 #undef DWT_COMPARATOR
1874 };
1875
1876 static const struct reg_arch_type dwt_reg_type = {
1877 .get = cortex_m_dwt_get_reg,
1878 .set = cortex_m_dwt_set_reg,
1879 };
1880
1881 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1882 {
1883 struct dwt_reg_state *state;
1884
1885 state = calloc(1, sizeof *state);
1886 if (!state)
1887 return;
1888 state->addr = d->addr;
1889 state->target = t;
1890
1891 r->name = d->name;
1892 r->size = d->size;
1893 r->value = state->value;
1894 r->arch_info = state;
1895 r->type = &dwt_reg_type;
1896 }
1897
1898 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1899 {
1900 uint32_t dwtcr;
1901 struct reg_cache *cache;
1902 struct cortex_m_dwt_comparator *comparator;
1903 int reg, i;
1904
1905 target_read_u32(target, DWT_CTRL, &dwtcr);
1906 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1907 if (!dwtcr) {
1908 LOG_DEBUG("no DWT");
1909 return;
1910 }
1911
1912 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1913 cm->dwt_comp_available = cm->dwt_num_comp;
1914 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1915 sizeof(struct cortex_m_dwt_comparator));
1916 if (!cm->dwt_comparator_list) {
1917 fail0:
1918 cm->dwt_num_comp = 0;
1919 LOG_ERROR("out of mem");
1920 return;
1921 }
1922
1923 cache = calloc(1, sizeof *cache);
1924 if (!cache) {
1925 fail1:
1926 free(cm->dwt_comparator_list);
1927 goto fail0;
1928 }
1929 cache->name = "Cortex-M DWT registers";
1930 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1931 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1932 if (!cache->reg_list) {
1933 free(cache);
1934 goto fail1;
1935 }
1936
1937 for (reg = 0; reg < 2; reg++)
1938 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1939 dwt_base_regs + reg);
1940
1941 comparator = cm->dwt_comparator_list;
1942 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1943 int j;
1944
1945 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1946 for (j = 0; j < 3; j++, reg++)
1947 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1948 dwt_comp + 3 * i + j);
1949
1950 /* make sure we clear any watchpoints enabled on the target */
1951 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1952 }
1953
1954 *register_get_last_cache_p(&target->reg_cache) = cache;
1955 cm->dwt_cache = cache;
1956
1957 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1958 dwtcr, cm->dwt_num_comp,
1959 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1960
1961 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1962 * implement single-address data value watchpoints ... so we
1963 * won't need to check it later, when asked to set one up.
1964 */
1965 }
1966
1967 static void cortex_m_dwt_free(struct target *target)
1968 {
1969 struct cortex_m_common *cm = target_to_cm(target);
1970 struct reg_cache *cache = cm->dwt_cache;
1971
1972 free(cm->dwt_comparator_list);
1973 cm->dwt_comparator_list = NULL;
1974 cm->dwt_num_comp = 0;
1975
1976 if (cache) {
1977 register_unlink_cache(&target->reg_cache, cache);
1978
1979 if (cache->reg_list) {
1980 for (size_t i = 0; i < cache->num_regs; i++)
1981 free(cache->reg_list[i].arch_info);
1982 free(cache->reg_list);
1983 }
1984 free(cache);
1985 }
1986 cm->dwt_cache = NULL;
1987 }
1988
1989 #define MVFR0 0xe000ef40
1990 #define MVFR1 0xe000ef44
1991
1992 #define MVFR0_DEFAULT_M4 0x10110021
1993 #define MVFR1_DEFAULT_M4 0x11000011
1994
1995 #define MVFR0_DEFAULT_M7_SP 0x10110021
1996 #define MVFR0_DEFAULT_M7_DP 0x10110221
1997 #define MVFR1_DEFAULT_M7_SP 0x11000011
1998 #define MVFR1_DEFAULT_M7_DP 0x12000011
1999
2000 int cortex_m_examine(struct target *target)
2001 {
2002 int retval;
2003 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2004 int i;
2005 struct cortex_m_common *cortex_m = target_to_cm(target);
2006 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2007 struct armv7m_common *armv7m = target_to_armv7m(target);
2008
2009 /* stlink shares the examine handler but does not support
2010 * all its calls */
2011 if (!armv7m->stlink) {
2012 if (cortex_m->apsel == DP_APSEL_INVALID) {
2013 /* Search for the MEM-AP */
2014 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
2015 if (retval != ERROR_OK) {
2016 LOG_ERROR("Could not find MEM-AP to control the core");
2017 return retval;
2018 }
2019 } else {
2020 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2021 }
2022
2023 /* Leave (only) generic DAP stuff for debugport_init(); */
2024 armv7m->debug_ap->memaccess_tck = 8;
2025
2026 retval = mem_ap_init(armv7m->debug_ap);
2027 if (retval != ERROR_OK)
2028 return retval;
2029 }
2030
2031 if (!target_was_examined(target)) {
2032 target_set_examined(target);
2033
2034 /* Read from Device Identification Registers */
2035 retval = target_read_u32(target, CPUID, &cpuid);
2036 if (retval != ERROR_OK)
2037 return retval;
2038
2039 /* Get CPU Type */
2040 i = (cpuid >> 4) & 0xf;
2041
2042 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2043 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2044 if (i == 7) {
2045 uint8_t rev, patch;
2046 rev = (cpuid >> 20) & 0xf;
2047 patch = (cpuid >> 0) & 0xf;
2048 if ((rev == 0) && (patch < 2))
2049 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2050 }
2051 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2052
2053 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2054 cortex_m->vectreset_supported = i > 1;
2055
2056 if (i == 4) {
2057 target_read_u32(target, MVFR0, &mvfr0);
2058 target_read_u32(target, MVFR1, &mvfr1);
2059
2060 /* test for floating point feature on Cortex-M4 */
2061 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2062 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2063 armv7m->fp_feature = FPv4_SP;
2064 }
2065 } else if (i == 7) {
2066 target_read_u32(target, MVFR0, &mvfr0);
2067 target_read_u32(target, MVFR1, &mvfr1);
2068
2069 /* test for floating point features on Cortex-M7 */
2070 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2071 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2072 armv7m->fp_feature = FPv5_SP;
2073 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2074 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2075 armv7m->fp_feature = FPv5_DP;
2076 }
2077 } else if (i == 0) {
2078 /* Cortex-M0 does not support unaligned memory access */
2079 armv7m->arm.is_armv6m = true;
2080 }
2081
2082 if (armv7m->fp_feature == FP_NONE &&
2083 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2084 /* free unavailable FPU registers */
2085 size_t idx;
2086
2087 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2088 idx < armv7m->arm.core_cache->num_regs;
2089 idx++) {
2090 free(armv7m->arm.core_cache->reg_list[idx].value);
2091 free(armv7m->arm.core_cache->reg_list[idx].feature);
2092 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2093 }
2094 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2095 }
2096
2097 if (!armv7m->stlink) {
2098 if (i == 3 || i == 4)
2099 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2100 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2101 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2102 else if (i == 7)
2103 /* Cortex-M7 has only 1024 bytes autoincrement range */
2104 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2105 }
2106
2107 /* Configure trace modules */
2108 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2109 if (retval != ERROR_OK)
2110 return retval;
2111
2112 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2113 armv7m_trace_tpiu_config(target);
2114 armv7m_trace_itm_config(target);
2115 }
2116
2117 /* NOTE: FPB and DWT are both optional. */
2118
2119 /* Setup FPB */
2120 target_read_u32(target, FP_CTRL, &fpcr);
2121 /* bits [14:12] and [7:4] */
2122 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2123 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2124 cortex_m->fp_code_available = cortex_m->fp_num_code;
2125 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2126 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2127 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2128 free(cortex_m->fp_comparator_list);
2129 cortex_m->fp_comparator_list = calloc(
2130 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2131 sizeof(struct cortex_m_fp_comparator));
2132 cortex_m->fpb_enabled = fpcr & 1;
2133 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2134 cortex_m->fp_comparator_list[i].type =
2135 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2136 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2137
2138 /* make sure we clear any breakpoints enabled on the target */
2139 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2140 }
2141 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2142 fpcr,
2143 cortex_m->fp_num_code,
2144 cortex_m->fp_num_lit);
2145
2146 /* Setup DWT */
2147 cortex_m_dwt_free(target);
2148 cortex_m_dwt_setup(cortex_m, target);
2149
2150 /* These hardware breakpoints only work for code in flash! */
2151 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2152 target_name(target),
2153 cortex_m->fp_num_code,
2154 cortex_m->dwt_num_comp);
2155 }
2156
2157 return ERROR_OK;
2158 }
2159
2160 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2161 {
2162 struct armv7m_common *armv7m = target_to_armv7m(target);
2163 uint16_t dcrdr;
2164 uint8_t buf[2];
2165 int retval;
2166
2167 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2168 if (retval != ERROR_OK)
2169 return retval;
2170
2171 dcrdr = target_buffer_get_u16(target, buf);
2172 *ctrl = (uint8_t)dcrdr;
2173 *value = (uint8_t)(dcrdr >> 8);
2174
2175 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2176
2177 /* write ack back to software dcc register
2178 * signify we have read data */
2179 if (dcrdr & (1 << 0)) {
2180 target_buffer_set_u16(target, buf, 0);
2181 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2182 if (retval != ERROR_OK)
2183 return retval;
2184 }
2185
2186 return ERROR_OK;
2187 }
2188
2189 static int cortex_m_target_request_data(struct target *target,
2190 uint32_t size, uint8_t *buffer)
2191 {
2192 uint8_t data;
2193 uint8_t ctrl;
2194 uint32_t i;
2195
2196 for (i = 0; i < (size * 4); i++) {
2197 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2198 if (retval != ERROR_OK)
2199 return retval;
2200 buffer[i] = data;
2201 }
2202
2203 return ERROR_OK;
2204 }
2205
2206 static int cortex_m_handle_target_request(void *priv)
2207 {
2208 struct target *target = priv;
2209 if (!target_was_examined(target))
2210 return ERROR_OK;
2211
2212 if (!target->dbg_msg_enabled)
2213 return ERROR_OK;
2214
2215 if (target->state == TARGET_RUNNING) {
2216 uint8_t data;
2217 uint8_t ctrl;
2218 int retval;
2219
2220 retval = cortex_m_dcc_read(target, &data, &ctrl);
2221 if (retval != ERROR_OK)
2222 return retval;
2223
2224 /* check if we have data */
2225 if (ctrl & (1 << 0)) {
2226 uint32_t request;
2227
2228 /* we assume target is quick enough */
2229 request = data;
2230 for (int i = 1; i <= 3; i++) {
2231 retval = cortex_m_dcc_read(target, &data, &ctrl);
2232 if (retval != ERROR_OK)
2233 return retval;
2234 request |= ((uint32_t)data << (i * 8));
2235 }
2236 target_request(target, request);
2237 }
2238 }
2239
2240 return ERROR_OK;
2241 }
2242
2243 static int cortex_m_init_arch_info(struct target *target,
2244 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2245 {
2246 struct armv7m_common *armv7m = &cortex_m->armv7m;
2247
2248 armv7m_init_arch_info(target, armv7m);
2249
2250 /* default reset mode is to use srst if fitted
2251 * if not it will use CORTEX_M3_RESET_VECTRESET */
2252 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2253
2254 armv7m->arm.dap = dap;
2255
2256 /* register arch-specific functions */
2257 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2258
2259 armv7m->post_debug_entry = NULL;
2260
2261 armv7m->pre_restore_context = NULL;
2262
2263 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2264 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2265
2266 target_register_timer_callback(cortex_m_handle_target_request, 1,
2267 TARGET_TIMER_TYPE_PERIODIC, target);
2268
2269 return ERROR_OK;
2270 }
2271
2272 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2273 {
2274 struct adiv5_private_config *pc;
2275
2276 pc = (struct adiv5_private_config *)target->private_config;
2277 if (adiv5_verify_config(pc) != ERROR_OK)
2278 return ERROR_FAIL;
2279
2280 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2281 if (cortex_m == NULL) {
2282 LOG_ERROR("No memory creating target");
2283 return ERROR_FAIL;
2284 }
2285
2286 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2287 cortex_m->apsel = pc->ap_num;
2288
2289 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2290
2291 return ERROR_OK;
2292 }
2293
2294 /*--------------------------------------------------------------------------*/
2295
2296 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2297 struct cortex_m_common *cm)
2298 {
2299 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2300 command_print(cmd_ctx, "target is not a Cortex-M");
2301 return ERROR_TARGET_INVALID;
2302 }
2303 return ERROR_OK;
2304 }
2305
2306 /*
2307 * Only stuff below this line should need to verify that its target
2308 * is a Cortex-M3. Everything else should have indirected through the
2309 * cortexm3_target structure, which is only used with CM3 targets.
2310 */
2311
2312 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2313 {
2314 struct target *target = get_current_target(CMD_CTX);
2315 struct cortex_m_common *cortex_m = target_to_cm(target);
2316 struct armv7m_common *armv7m = &cortex_m->armv7m;
2317 uint32_t demcr = 0;
2318 int retval;
2319
2320 static const struct {
2321 char name[10];
2322 unsigned mask;
2323 } vec_ids[] = {
2324 { "hard_err", VC_HARDERR, },
2325 { "int_err", VC_INTERR, },
2326 { "bus_err", VC_BUSERR, },
2327 { "state_err", VC_STATERR, },
2328 { "chk_err", VC_CHKERR, },
2329 { "nocp_err", VC_NOCPERR, },
2330 { "mm_err", VC_MMERR, },
2331 { "reset", VC_CORERESET, },
2332 };
2333
2334 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2335 if (retval != ERROR_OK)
2336 return retval;
2337
2338 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2339 if (retval != ERROR_OK)
2340 return retval;
2341
2342 if (CMD_ARGC > 0) {
2343 unsigned catch = 0;
2344
2345 if (CMD_ARGC == 1) {
2346 if (strcmp(CMD_ARGV[0], "all") == 0) {
2347 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2348 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2349 | VC_MMERR | VC_CORERESET;
2350 goto write;
2351 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2352 goto write;
2353 }
2354 while (CMD_ARGC-- > 0) {
2355 unsigned i;
2356 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2357 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2358 continue;
2359 catch |= vec_ids[i].mask;
2360 break;
2361 }
2362 if (i == ARRAY_SIZE(vec_ids)) {
2363 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2364 return ERROR_COMMAND_SYNTAX_ERROR;
2365 }
2366 }
2367 write:
2368 /* For now, armv7m->demcr only stores vector catch flags. */
2369 armv7m->demcr = catch;
2370
2371 demcr &= ~0xffff;
2372 demcr |= catch;
2373
2374 /* write, but don't assume it stuck (why not??) */
2375 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2376 if (retval != ERROR_OK)
2377 return retval;
2378 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2379 if (retval != ERROR_OK)
2380 return retval;
2381
2382 /* FIXME be sure to clear DEMCR on clean server shutdown.
2383 * Otherwise the vector catch hardware could fire when there's
2384 * no debugger hooked up, causing much confusion...
2385 */
2386 }
2387
2388 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2389 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2390 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2391 }
2392
2393 return ERROR_OK;
2394 }
2395
2396 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2397 {
2398 struct target *target = get_current_target(CMD_CTX);
2399 struct cortex_m_common *cortex_m = target_to_cm(target);
2400 int retval;
2401
2402 static const Jim_Nvp nvp_maskisr_modes[] = {
2403 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2404 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2405 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2406 { .name = NULL, .value = -1 },
2407 };
2408 const Jim_Nvp *n;
2409
2410
2411 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2412 if (retval != ERROR_OK)
2413 return retval;
2414
2415 if (target->state != TARGET_HALTED) {
2416 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2417 return ERROR_OK;
2418 }
2419
2420 if (CMD_ARGC > 0) {
2421 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2422 if (n->name == NULL)
2423 return ERROR_COMMAND_SYNTAX_ERROR;
2424 cortex_m->isrmasking_mode = n->value;
2425
2426
2427 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2428 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2429 else
2430 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2431 }
2432
2433 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2434 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2435
2436 return ERROR_OK;
2437 }
2438
2439 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2440 {
2441 struct target *target = get_current_target(CMD_CTX);
2442 struct cortex_m_common *cortex_m = target_to_cm(target);
2443 int retval;
2444 char *reset_config;
2445
2446 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2447 if (retval != ERROR_OK)
2448 return retval;
2449
2450 if (CMD_ARGC > 0) {
2451 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2452 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2453
2454 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2455 if (target_was_examined(target)
2456 && !cortex_m->vectreset_supported)
2457 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2458 else
2459 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2460
2461 } else
2462 return ERROR_COMMAND_SYNTAX_ERROR;
2463 }
2464
2465 switch (cortex_m->soft_reset_config) {
2466 case CORTEX_M_RESET_SYSRESETREQ:
2467 reset_config = "sysresetreq";
2468 break;
2469
2470 case CORTEX_M_RESET_VECTRESET:
2471 reset_config = "vectreset";
2472 break;
2473
2474 default:
2475 reset_config = "unknown";
2476 break;
2477 }
2478
2479 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2480
2481 return ERROR_OK;
2482 }
2483
2484 static const struct command_registration cortex_m_exec_command_handlers[] = {
2485 {
2486 .name = "maskisr",
2487 .handler = handle_cortex_m_mask_interrupts_command,
2488 .mode = COMMAND_EXEC,
2489 .help = "mask cortex_m interrupts",
2490 .usage = "['auto'|'on'|'off']",
2491 },
2492 {
2493 .name = "vector_catch",
2494 .handler = handle_cortex_m_vector_catch_command,
2495 .mode = COMMAND_EXEC,
2496 .help = "configure hardware vectors to trigger debug entry",
2497 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2498 },
2499 {
2500 .name = "reset_config",
2501 .handler = handle_cortex_m_reset_config_command,
2502 .mode = COMMAND_ANY,
2503 .help = "configure software reset handling",
2504 .usage = "['sysresetreq'|'vectreset']",
2505 },
2506 COMMAND_REGISTRATION_DONE
2507 };
2508 static const struct command_registration cortex_m_command_handlers[] = {
2509 {
2510 .chain = armv7m_command_handlers,
2511 },
2512 {
2513 .chain = armv7m_trace_command_handlers,
2514 },
2515 {
2516 .name = "cortex_m",
2517 .mode = COMMAND_EXEC,
2518 .help = "Cortex-M command group",
2519 .usage = "",
2520 .chain = cortex_m_exec_command_handlers,
2521 },
2522 COMMAND_REGISTRATION_DONE
2523 };
2524
2525 struct target_type cortexm_target = {
2526 .name = "cortex_m",
2527 .deprecated_name = "cortex_m3",
2528
2529 .poll = cortex_m_poll,
2530 .arch_state = armv7m_arch_state,
2531
2532 .target_request_data = cortex_m_target_request_data,
2533
2534 .halt = cortex_m_halt,
2535 .resume = cortex_m_resume,
2536 .step = cortex_m_step,
2537
2538 .assert_reset = cortex_m_assert_reset,
2539 .deassert_reset = cortex_m_deassert_reset,
2540 .soft_reset_halt = cortex_m_soft_reset_halt,
2541
2542 .get_gdb_arch = arm_get_gdb_arch,
2543 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2544
2545 .read_memory = cortex_m_read_memory,
2546 .write_memory = cortex_m_write_memory,
2547 .checksum_memory = armv7m_checksum_memory,
2548 .blank_check_memory = armv7m_blank_check_memory,
2549
2550 .run_algorithm = armv7m_run_algorithm,
2551 .start_algorithm = armv7m_start_algorithm,
2552 .wait_algorithm = armv7m_wait_algorithm,
2553
2554 .add_breakpoint = cortex_m_add_breakpoint,
2555 .remove_breakpoint = cortex_m_remove_breakpoint,
2556 .add_watchpoint = cortex_m_add_watchpoint,
2557 .remove_watchpoint = cortex_m_remove_watchpoint,
2558
2559 .commands = cortex_m_command_handlers,
2560 .target_create = cortex_m_target_create,
2561 .target_jim_configure = adiv5_jim_configure,
2562 .init_target = cortex_m_init_target,
2563 .examine = cortex_m_examine,
2564 .deinit_target = cortex_m_deinit_target,
2565
2566 .profiling = cortex_m_profiling,
2567 };
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