1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target
*target
,
56 uint32_t num
, uint32_t value
);
57 static void cortex_m_dwt_free(struct target
*target
);
59 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
60 uint32_t *value
, int regnum
)
62 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target
->dbg_msg_enabled
) {
69 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
70 if (retval
!= ERROR_OK
)
74 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
);
75 if (retval
!= ERROR_OK
)
78 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
79 if (retval
!= ERROR_OK
)
82 if (target
->dbg_msg_enabled
) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval
== ERROR_OK
)
86 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
92 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
93 uint32_t value
, int regnum
)
95 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target
->dbg_msg_enabled
) {
102 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
103 if (retval
!= ERROR_OK
)
107 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
108 if (retval
!= ERROR_OK
)
111 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
112 if (retval
!= ERROR_OK
)
115 if (target
->dbg_msg_enabled
) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval
== ERROR_OK
)
119 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
125 static int cortex_m_write_debug_halt_mask(struct target
*target
,
126 uint32_t mask_on
, uint32_t mask_off
)
128 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
129 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
131 /* mask off status bits */
132 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
133 /* create new register mask */
134 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
136 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
139 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
141 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
142 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
143 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
148 static int cortex_m_set_maskints_for_halt(struct target
*target
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 switch (cortex_m
->isrmasking_mode
) {
152 case CORTEX_M_ISRMASK_AUTO
:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target
, false);
156 case CORTEX_M_ISRMASK_OFF
:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target
, false);
160 case CORTEX_M_ISRMASK_ON
:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target
, true);
164 case CORTEX_M_ISRMASK_STEPONLY
:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
172 static int cortex_m_set_maskints_for_run(struct target
*target
)
174 switch (target_to_cm(target
)->isrmasking_mode
) {
175 case CORTEX_M_ISRMASK_AUTO
:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target
, false);
179 case CORTEX_M_ISRMASK_OFF
:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target
, false);
183 case CORTEX_M_ISRMASK_ON
:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target
, true);
187 case CORTEX_M_ISRMASK_STEPONLY
:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target
, false);
194 static int cortex_m_set_maskints_for_step(struct target
*target
)
196 switch (target_to_cm(target
)->isrmasking_mode
) {
197 case CORTEX_M_ISRMASK_AUTO
:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target
, true);
201 case CORTEX_M_ISRMASK_OFF
:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target
, false);
205 case CORTEX_M_ISRMASK_ON
:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target
, true);
209 case CORTEX_M_ISRMASK_STEPONLY
:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target
, true);
216 static int cortex_m_clear_halt(struct target
*target
)
218 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
219 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
225 /* Read Debug Fault Status Register */
226 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
227 if (retval
!= ERROR_OK
)
230 /* Clear Debug Fault Status */
231 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
232 if (retval
!= ERROR_OK
)
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
239 static int cortex_m_single_step_core(struct target
*target
)
241 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
242 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
249 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
250 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
251 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
252 if (retval
!= ERROR_OK
)
255 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
256 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
257 if (retval
!= ERROR_OK
)
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target
);
267 static int cortex_m_enable_fpb(struct target
*target
)
269 int retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 /* check the fpb is actually enabled */
275 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
276 if (retval
!= ERROR_OK
)
285 static int cortex_m_endreset_event(struct target
*target
)
290 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
291 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
292 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
293 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
294 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
298 if (retval
!= ERROR_OK
)
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
302 /* this register is used for emulated dcc channel */
303 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
304 if (retval
!= ERROR_OK
)
307 /* Enable debug requests */
308 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
309 if (retval
!= ERROR_OK
)
311 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
312 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
313 if (retval
!= ERROR_OK
)
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target
);
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
327 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
328 if (retval
!= ERROR_OK
)
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
336 retval
= cortex_m_enable_fpb(target
);
337 if (retval
!= ERROR_OK
) {
338 LOG_ERROR("Failed to enable the FPB");
342 cortex_m
->fpb_enabled
= true;
344 /* Restore FPB registers */
345 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
346 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
347 if (retval
!= ERROR_OK
)
351 /* Restore DWT registers */
352 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
353 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
355 if (retval
!= ERROR_OK
)
357 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
359 if (retval
!= ERROR_OK
)
361 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
362 dwt_list
[i
].function
);
363 if (retval
!= ERROR_OK
)
366 retval
= dap_run(swjdp
);
367 if (retval
!= ERROR_OK
)
370 register_cache_invalidate(armv7m
->arm
.core_cache
);
372 /* make sure we have latest dhcsr flags */
373 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
378 static int cortex_m_examine_debug_reason(struct target
*target
)
380 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
385 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
386 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
387 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
388 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
389 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
390 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
391 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
392 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
393 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
394 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
395 else if (cortex_m
->nvic_dfsr
& DFSR_EXTERNAL
)
396 target
->debug_reason
= DBG_REASON_DBGRQ
;
398 target
->debug_reason
= DBG_REASON_UNDEFINED
;
404 static int cortex_m_examine_exception_reason(struct target
*target
)
406 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
407 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
408 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
411 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
412 if (retval
!= ERROR_OK
)
414 switch (armv7m
->exception_number
) {
417 case 3: /* Hard Fault */
418 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
419 if (retval
!= ERROR_OK
)
421 if (except_sr
& 0x40000000) {
422 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
423 if (retval
!= ERROR_OK
)
427 case 4: /* Memory Management */
428 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
429 if (retval
!= ERROR_OK
)
431 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
432 if (retval
!= ERROR_OK
)
435 case 5: /* Bus Fault */
436 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
437 if (retval
!= ERROR_OK
)
439 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
440 if (retval
!= ERROR_OK
)
443 case 6: /* Usage Fault */
444 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
445 if (retval
!= ERROR_OK
)
448 case 11: /* SVCall */
450 case 12: /* Debug Monitor */
451 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
452 if (retval
!= ERROR_OK
)
455 case 14: /* PendSV */
457 case 15: /* SysTick */
463 retval
= dap_run(swjdp
);
464 if (retval
== ERROR_OK
)
465 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
466 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
467 armv7m_exception_string(armv7m
->exception_number
),
468 shcsr
, except_sr
, cfsr
, except_ar
);
472 static int cortex_m_debug_entry(struct target
*target
)
477 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
478 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
479 struct arm
*arm
= &armv7m
->arm
;
484 /* Do this really early to minimize the window where the MASKINTS erratum
485 * can pile up pending interrupts. */
486 cortex_m_set_maskints_for_halt(target
);
488 cortex_m_clear_halt(target
);
489 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
490 if (retval
!= ERROR_OK
)
493 retval
= armv7m
->examine_debug_reason(target
);
494 if (retval
!= ERROR_OK
)
497 /* Examine target state and mode
498 * First load register accessible through core debug port */
499 int num_regs
= arm
->core_cache
->num_regs
;
501 for (i
= 0; i
< num_regs
; i
++) {
502 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
504 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
508 xPSR
= buf_get_u32(r
->value
, 0, 32);
510 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
513 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
516 /* Are we in an exception handler */
518 armv7m
->exception_number
= (xPSR
& 0x1FF);
520 arm
->core_mode
= ARM_MODE_HANDLER
;
521 arm
->map
= armv7m_msp_reg_map
;
523 unsigned control
= buf_get_u32(arm
->core_cache
524 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
526 /* is this thread privileged? */
527 arm
->core_mode
= control
& 1
528 ? ARM_MODE_USER_THREAD
531 /* which stack is it using? */
533 arm
->map
= armv7m_psp_reg_map
;
535 arm
->map
= armv7m_msp_reg_map
;
537 armv7m
->exception_number
= 0;
540 if (armv7m
->exception_number
)
541 cortex_m_examine_exception_reason(target
);
543 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
544 arm_mode_name(arm
->core_mode
),
545 buf_get_u32(arm
->pc
->value
, 0, 32),
546 target_state_name(target
));
548 if (armv7m
->post_debug_entry
) {
549 retval
= armv7m
->post_debug_entry(target
);
550 if (retval
!= ERROR_OK
)
557 static int cortex_m_poll(struct target
*target
)
559 int detected_failure
= ERROR_OK
;
560 int retval
= ERROR_OK
;
561 enum target_state prev_target_state
= target
->state
;
562 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
563 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
565 /* Read from Debug Halting Control and Status Register */
566 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
567 if (retval
!= ERROR_OK
) {
568 target
->state
= TARGET_UNKNOWN
;
572 /* Recover from lockup. See ARMv7-M architecture spec,
573 * section B1.5.15 "Unrecoverable exception cases".
575 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
576 LOG_ERROR("%s -- clearing lockup after double fault",
577 target_name(target
));
578 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
579 target
->debug_reason
= DBG_REASON_DBGRQ
;
581 /* We have to execute the rest (the "finally" equivalent, but
582 * still throw this exception again).
584 detected_failure
= ERROR_FAIL
;
586 /* refresh status bits */
587 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
588 if (retval
!= ERROR_OK
)
592 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
593 if (target
->state
!= TARGET_RESET
) {
594 target
->state
= TARGET_RESET
;
595 LOG_INFO("%s: external reset detected", target_name(target
));
600 if (target
->state
== TARGET_RESET
) {
601 /* Cannot switch context while running so endreset is
602 * called with target->state == TARGET_RESET
604 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
605 cortex_m
->dcb_dhcsr
);
606 retval
= cortex_m_endreset_event(target
);
607 if (retval
!= ERROR_OK
) {
608 target
->state
= TARGET_UNKNOWN
;
611 target
->state
= TARGET_RUNNING
;
612 prev_target_state
= TARGET_RUNNING
;
615 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
616 target
->state
= TARGET_HALTED
;
618 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
619 retval
= cortex_m_debug_entry(target
);
620 if (retval
!= ERROR_OK
)
623 if (arm_semihosting(target
, &retval
) != 0)
626 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
628 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
630 retval
= cortex_m_debug_entry(target
);
631 if (retval
!= ERROR_OK
)
634 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
638 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
639 * How best to model low power modes?
642 if (target
->state
== TARGET_UNKNOWN
) {
643 /* check if processor is retiring instructions */
644 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
645 target
->state
= TARGET_RUNNING
;
650 /* Check that target is truly halted, since the target could be resumed externally */
651 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
652 /* registers are now invalid */
653 register_cache_invalidate(armv7m
->arm
.core_cache
);
655 target
->state
= TARGET_RUNNING
;
656 LOG_WARNING("%s: external resume detected", target_name(target
));
657 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
661 /* Did we detect a failure condition that we cleared? */
662 if (detected_failure
!= ERROR_OK
)
663 retval
= detected_failure
;
667 static int cortex_m_halt(struct target
*target
)
669 LOG_DEBUG("target->state: %s",
670 target_state_name(target
));
672 if (target
->state
== TARGET_HALTED
) {
673 LOG_DEBUG("target was already halted");
677 if (target
->state
== TARGET_UNKNOWN
)
678 LOG_WARNING("target was in unknown state when halt was requested");
680 if (target
->state
== TARGET_RESET
) {
681 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
682 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
683 return ERROR_TARGET_FAILURE
;
685 /* we came here in a reset_halt or reset_init sequence
686 * debug entry was already prepared in cortex_m3_assert_reset()
688 target
->debug_reason
= DBG_REASON_DBGRQ
;
694 /* Write to Debug Halting Control and Status Register */
695 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
697 /* Do this really early to minimize the window where the MASKINTS erratum
698 * can pile up pending interrupts. */
699 cortex_m_set_maskints_for_halt(target
);
701 target
->debug_reason
= DBG_REASON_DBGRQ
;
706 static int cortex_m_soft_reset_halt(struct target
*target
)
708 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
709 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
710 uint32_t dcb_dhcsr
= 0;
711 int retval
, timeout
= 0;
713 /* soft_reset_halt is deprecated on cortex_m as the same functionality
714 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
715 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
716 * core, not the peripherals */
717 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
719 /* Enter debug state on reset; restore DEMCR in endreset_event() */
720 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
721 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
722 if (retval
!= ERROR_OK
)
725 /* Request a core-only reset */
726 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
727 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
728 if (retval
!= ERROR_OK
)
730 target
->state
= TARGET_RESET
;
732 /* registers are now invalid */
733 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
735 while (timeout
< 100) {
736 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
737 if (retval
== ERROR_OK
) {
738 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
739 &cortex_m
->nvic_dfsr
);
740 if (retval
!= ERROR_OK
)
742 if ((dcb_dhcsr
& S_HALT
)
743 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
744 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
746 (unsigned) dcb_dhcsr
,
747 (unsigned) cortex_m
->nvic_dfsr
);
748 cortex_m_poll(target
);
749 /* FIXME restore user's vector catch config */
752 LOG_DEBUG("waiting for system reset-halt, "
753 "DHCSR 0x%08x, %d ms",
754 (unsigned) dcb_dhcsr
, timeout
);
763 void cortex_m_enable_breakpoints(struct target
*target
)
765 struct breakpoint
*breakpoint
= target
->breakpoints
;
767 /* set any pending breakpoints */
769 if (!breakpoint
->set
)
770 cortex_m_set_breakpoint(target
, breakpoint
);
771 breakpoint
= breakpoint
->next
;
775 static int cortex_m_resume(struct target
*target
, int current
,
776 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
778 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
779 struct breakpoint
*breakpoint
= NULL
;
783 if (target
->state
!= TARGET_HALTED
) {
784 LOG_WARNING("target not halted");
785 return ERROR_TARGET_NOT_HALTED
;
788 if (!debug_execution
) {
789 target_free_all_working_areas(target
);
790 cortex_m_enable_breakpoints(target
);
791 cortex_m_enable_watchpoints(target
);
794 if (debug_execution
) {
795 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
797 /* Disable interrupts */
798 /* We disable interrupts in the PRIMASK register instead of
799 * masking with C_MASKINTS. This is probably the same issue
800 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
801 * in parallel with disabled interrupts can cause local faults
804 * REVISIT this clearly breaks non-debug execution, since the
805 * PRIMASK register state isn't saved/restored... workaround
806 * by never resuming app code after debug execution.
808 buf_set_u32(r
->value
, 0, 1, 1);
812 /* Make sure we are in Thumb mode */
813 r
= armv7m
->arm
.cpsr
;
814 buf_set_u32(r
->value
, 24, 1, 1);
819 /* current = 1: continue on current pc, otherwise continue at <address> */
822 buf_set_u32(r
->value
, 0, 32, address
);
827 /* if we halted last time due to a bkpt instruction
828 * then we have to manually step over it, otherwise
829 * the core will break again */
831 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
833 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
835 resume_pc
= buf_get_u32(r
->value
, 0, 32);
837 armv7m_restore_context(target
);
839 /* the front-end may request us not to handle breakpoints */
840 if (handle_breakpoints
) {
841 /* Single step past breakpoint at current address */
842 breakpoint
= breakpoint_find(target
, resume_pc
);
844 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
846 breakpoint
->unique_id
);
847 cortex_m_unset_breakpoint(target
, breakpoint
);
848 cortex_m_single_step_core(target
);
849 cortex_m_set_breakpoint(target
, breakpoint
);
854 cortex_m_set_maskints_for_run(target
);
855 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
857 target
->debug_reason
= DBG_REASON_NOTHALTED
;
859 /* registers are now invalid */
860 register_cache_invalidate(armv7m
->arm
.core_cache
);
862 if (!debug_execution
) {
863 target
->state
= TARGET_RUNNING
;
864 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
865 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
867 target
->state
= TARGET_DEBUG_RUNNING
;
868 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
869 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
875 /* int irqstepcount = 0; */
876 static int cortex_m_step(struct target
*target
, int current
,
877 target_addr_t address
, int handle_breakpoints
)
879 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
880 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
881 struct breakpoint
*breakpoint
= NULL
;
882 struct reg
*pc
= armv7m
->arm
.pc
;
883 bool bkpt_inst_found
= false;
885 bool isr_timed_out
= false;
887 if (target
->state
!= TARGET_HALTED
) {
888 LOG_WARNING("target not halted");
889 return ERROR_TARGET_NOT_HALTED
;
892 /* current = 1: continue on current pc, otherwise continue at <address> */
894 buf_set_u32(pc
->value
, 0, 32, address
);
896 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
898 /* the front-end may request us not to handle breakpoints */
899 if (handle_breakpoints
) {
900 breakpoint
= breakpoint_find(target
, pc_value
);
902 cortex_m_unset_breakpoint(target
, breakpoint
);
905 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
907 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
909 armv7m_restore_context(target
);
911 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
913 /* if no bkpt instruction is found at pc then we can perform
914 * a normal step, otherwise we have to manually step over the bkpt
915 * instruction - as such simulate a step */
916 if (bkpt_inst_found
== false) {
917 if ((cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
)) {
918 /* Automatic ISR masking mode off: Just step over the next
919 * instruction, with interrupts on or off as appropriate. */
920 cortex_m_set_maskints_for_step(target
);
921 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
923 /* Process interrupts during stepping in a way they don't interfere
928 * Set a temporary break point at the current pc and let the core run
929 * with interrupts enabled. Pending interrupts get served and we run
930 * into the breakpoint again afterwards. Then we step over the next
931 * instruction with interrupts disabled.
933 * If the pending interrupts don't complete within time, we leave the
934 * core running. This may happen if the interrupts trigger faster
935 * than the core can process them or the handler doesn't return.
937 * If no more breakpoints are available we simply do a step with
938 * interrupts enabled.
944 * If a break point is already set on the lower half word then a break point on
945 * the upper half word will not break again when the core is restarted. So we
946 * just step over the instruction with interrupts disabled.
948 * The documentation has no information about this, it was found by observation
949 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
950 * suffer from this problem.
952 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
953 * address has it always cleared. The former is done to indicate thumb mode
957 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
958 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
959 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
960 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
961 /* Re-enable interrupts if appropriate */
962 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
963 cortex_m_set_maskints_for_halt(target
);
967 /* Set a temporary break point */
969 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
971 enum breakpoint_type type
= BKPT_HARD
;
972 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
973 /* FPB rev.1 cannot handle such addr, try BKPT instr */
976 retval
= breakpoint_add(target
, pc_value
, 2, type
);
979 bool tmp_bp_set
= (retval
== ERROR_OK
);
981 /* No more breakpoints left, just do a step */
983 cortex_m_set_maskints_for_step(target
);
984 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
985 /* Re-enable interrupts if appropriate */
986 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
987 cortex_m_set_maskints_for_halt(target
);
990 LOG_DEBUG("Starting core to serve pending interrupts");
991 int64_t t_start
= timeval_ms();
992 cortex_m_set_maskints_for_run(target
);
993 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
995 /* Wait for pending handlers to complete or timeout */
997 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
999 &cortex_m
->dcb_dhcsr
);
1000 if (retval
!= ERROR_OK
) {
1001 target
->state
= TARGET_UNKNOWN
;
1004 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1005 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1007 /* only remove breakpoint if we created it */
1009 cortex_m_unset_breakpoint(target
, breakpoint
);
1011 /* Remove the temporary breakpoint */
1012 breakpoint_remove(target
, pc_value
);
1015 if (isr_timed_out
) {
1016 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1017 "leaving target running");
1019 /* Step over next instruction with interrupts disabled */
1020 cortex_m_set_maskints_for_step(target
);
1021 cortex_m_write_debug_halt_mask(target
,
1022 C_HALT
| C_MASKINTS
,
1024 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1025 /* Re-enable interrupts if appropriate */
1026 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1027 cortex_m_set_maskints_for_halt(target
);
1034 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1035 if (retval
!= ERROR_OK
)
1038 /* registers are now invalid */
1039 register_cache_invalidate(armv7m
->arm
.core_cache
);
1042 cortex_m_set_breakpoint(target
, breakpoint
);
1044 if (isr_timed_out
) {
1045 /* Leave the core running. The user has to stop execution manually. */
1046 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1047 target
->state
= TARGET_RUNNING
;
1051 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1052 " nvic_icsr = 0x%" PRIx32
,
1053 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1055 retval
= cortex_m_debug_entry(target
);
1056 if (retval
!= ERROR_OK
)
1058 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1060 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1061 " nvic_icsr = 0x%" PRIx32
,
1062 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1067 static int cortex_m_assert_reset(struct target
*target
)
1069 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1070 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1071 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1073 LOG_DEBUG("target->state: %s",
1074 target_state_name(target
));
1076 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1078 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1079 /* allow scripts to override the reset event */
1081 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1082 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1083 target
->state
= TARGET_RESET
;
1088 /* some cores support connecting while srst is asserted
1089 * use that mode is it has been configured */
1091 bool srst_asserted
= false;
1093 if (!target_was_examined(target
)) {
1094 if (jtag_reset_config
& RESET_HAS_SRST
) {
1095 adapter_assert_reset();
1096 if (target
->reset_halt
)
1097 LOG_ERROR("Target not examined, will not halt after reset!");
1100 LOG_ERROR("Target not examined, reset NOT asserted!");
1105 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1106 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1107 adapter_assert_reset();
1108 srst_asserted
= true;
1111 /* Enable debug requests */
1113 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1114 /* Store important errors instead of failing and proceed to reset assert */
1116 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1117 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1119 /* If the processor is sleeping in a WFI or WFE instruction, the
1120 * C_HALT bit must be asserted to regain control */
1121 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1122 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1124 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1125 /* Ignore less important errors */
1127 if (!target
->reset_halt
) {
1128 /* Set/Clear C_MASKINTS in a separate operation */
1129 cortex_m_set_maskints_for_run(target
);
1131 /* clear any debug flags before resuming */
1132 cortex_m_clear_halt(target
);
1134 /* clear C_HALT in dhcsr reg */
1135 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1137 /* Halt in debug on reset; endreset_event() restores DEMCR.
1139 * REVISIT catching BUSERR presumably helps to defend against
1140 * bad vector table entries. Should this include MMERR or
1144 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1145 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1146 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1147 LOG_INFO("AP write error, reset will not halt");
1150 if (jtag_reset_config
& RESET_HAS_SRST
) {
1151 /* default to asserting srst */
1153 adapter_assert_reset();
1155 /* srst is asserted, ignore AP access errors */
1158 /* Use a standard Cortex-M3 software reset mechanism.
1159 * We default to using VECRESET as it is supported on all current cores
1160 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1161 * This has the disadvantage of not resetting the peripherals, so a
1162 * reset-init event handler is needed to perform any peripheral resets.
1164 if (!cortex_m
->vectreset_supported
1165 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1166 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1167 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1168 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1171 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1172 ? "SYSRESETREQ" : "VECTRESET");
1174 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1175 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1176 "handler to reset any peripherals or configure hardware srst support.");
1180 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1181 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1182 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1183 if (retval3
!= ERROR_OK
)
1184 LOG_DEBUG("Ignoring AP write error right after reset");
1186 retval3
= dap_dp_init(armv7m
->debug_ap
->dap
);
1187 if (retval3
!= ERROR_OK
)
1188 LOG_ERROR("DP initialisation failed");
1191 /* I do not know why this is necessary, but it
1192 * fixes strange effects (step/resume cause NMI
1193 * after reset) on LM3S6918 -- Michael Schwingen
1196 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1200 target
->state
= TARGET_RESET
;
1203 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1205 /* now return stored error code if any */
1206 if (retval
!= ERROR_OK
)
1209 if (target
->reset_halt
) {
1210 retval
= target_halt(target
);
1211 if (retval
!= ERROR_OK
)
1218 static int cortex_m_deassert_reset(struct target
*target
)
1220 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1222 LOG_DEBUG("target->state: %s",
1223 target_state_name(target
));
1225 /* deassert reset lines */
1226 adapter_deassert_reset();
1228 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1230 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1231 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1232 target_was_examined(target
)) {
1233 int retval
= dap_dp_init(armv7m
->debug_ap
->dap
);
1234 if (retval
!= ERROR_OK
) {
1235 LOG_ERROR("DP initialisation failed");
1243 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1247 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1248 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1250 if (breakpoint
->set
) {
1251 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1255 if (breakpoint
->type
== BKPT_HARD
) {
1256 uint32_t fpcr_value
;
1257 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1259 if (fp_num
>= cortex_m
->fp_num_code
) {
1260 LOG_ERROR("Can not find free FPB Comparator!");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1263 breakpoint
->set
= fp_num
+ 1;
1264 fpcr_value
= breakpoint
->address
| 1;
1265 if (cortex_m
->fp_rev
== 0) {
1266 if (breakpoint
->address
> 0x1FFFFFFF) {
1267 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1271 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1272 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1273 } else if (cortex_m
->fp_rev
> 1) {
1274 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1277 comparator_list
[fp_num
].used
= true;
1278 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1279 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1280 comparator_list
[fp_num
].fpcr_value
);
1281 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1283 comparator_list
[fp_num
].fpcr_value
);
1284 if (!cortex_m
->fpb_enabled
) {
1285 LOG_DEBUG("FPB wasn't enabled, do it now");
1286 retval
= cortex_m_enable_fpb(target
);
1287 if (retval
!= ERROR_OK
) {
1288 LOG_ERROR("Failed to enable the FPB");
1292 cortex_m
->fpb_enabled
= true;
1294 } else if (breakpoint
->type
== BKPT_SOFT
) {
1297 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1298 * semihosting; don't use that. Otherwise the BKPT
1299 * parameter is arbitrary.
1301 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1302 retval
= target_read_memory(target
,
1303 breakpoint
->address
& 0xFFFFFFFE,
1304 breakpoint
->length
, 1,
1305 breakpoint
->orig_instr
);
1306 if (retval
!= ERROR_OK
)
1308 retval
= target_write_memory(target
,
1309 breakpoint
->address
& 0xFFFFFFFE,
1310 breakpoint
->length
, 1,
1312 if (retval
!= ERROR_OK
)
1314 breakpoint
->set
= true;
1317 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1318 breakpoint
->unique_id
,
1319 (int)(breakpoint
->type
),
1320 breakpoint
->address
,
1327 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1330 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1331 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1333 if (!breakpoint
->set
) {
1334 LOG_WARNING("breakpoint not set");
1338 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1339 breakpoint
->unique_id
,
1340 (int)(breakpoint
->type
),
1341 breakpoint
->address
,
1345 if (breakpoint
->type
== BKPT_HARD
) {
1346 int fp_num
= breakpoint
->set
- 1;
1347 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1348 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1351 comparator_list
[fp_num
].used
= false;
1352 comparator_list
[fp_num
].fpcr_value
= 0;
1353 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1354 comparator_list
[fp_num
].fpcr_value
);
1356 /* restore original instruction (kept in target endianness) */
1357 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1358 breakpoint
->length
, 1,
1359 breakpoint
->orig_instr
);
1360 if (retval
!= ERROR_OK
)
1363 breakpoint
->set
= false;
1368 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1370 if (breakpoint
->length
== 3) {
1371 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1372 breakpoint
->length
= 2;
1375 if ((breakpoint
->length
!= 2)) {
1376 LOG_INFO("only breakpoints of two bytes length supported");
1377 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1380 return cortex_m_set_breakpoint(target
, breakpoint
);
1383 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1385 if (!breakpoint
->set
)
1388 return cortex_m_unset_breakpoint(target
, breakpoint
);
1391 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1394 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1396 /* REVISIT Don't fully trust these "not used" records ... users
1397 * may set up breakpoints by hand, e.g. dual-address data value
1398 * watchpoint using comparator #1; comparator #0 matching cycle
1399 * count; send data trace info through ITM and TPIU; etc
1401 struct cortex_m_dwt_comparator
*comparator
;
1403 for (comparator
= cortex_m
->dwt_comparator_list
;
1404 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1405 comparator
++, dwt_num
++)
1407 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1408 LOG_ERROR("Can not find free DWT Comparator");
1411 comparator
->used
= true;
1412 watchpoint
->set
= dwt_num
+ 1;
1414 comparator
->comp
= watchpoint
->address
;
1415 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1418 if ((cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M
) {
1419 uint32_t mask
= 0, temp
;
1421 /* watchpoint params were validated earlier */
1422 temp
= watchpoint
->length
;
1429 comparator
->mask
= mask
;
1430 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1433 switch (watchpoint
->rw
) {
1435 comparator
->function
= 5;
1438 comparator
->function
= 6;
1441 comparator
->function
= 7;
1445 uint32_t data_size
= watchpoint
->length
>> 1;
1446 comparator
->mask
= (watchpoint
->length
>> 1) | 1;
1448 switch (watchpoint
->rw
) {
1450 comparator
->function
= 4;
1453 comparator
->function
= 5;
1456 comparator
->function
= 6;
1459 comparator
->function
= comparator
->function
| (1 << 4) |
1463 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1464 comparator
->function
);
1466 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1467 watchpoint
->unique_id
, dwt_num
,
1468 (unsigned) comparator
->comp
,
1469 (unsigned) comparator
->mask
,
1470 (unsigned) comparator
->function
);
1474 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1476 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1477 struct cortex_m_dwt_comparator
*comparator
;
1480 if (!watchpoint
->set
) {
1481 LOG_WARNING("watchpoint (wpid: %d) not set",
1482 watchpoint
->unique_id
);
1486 dwt_num
= watchpoint
->set
- 1;
1488 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1489 watchpoint
->unique_id
, dwt_num
,
1490 (unsigned) watchpoint
->address
);
1492 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1493 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1497 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1498 comparator
->used
= false;
1499 comparator
->function
= 0;
1500 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1501 comparator
->function
);
1503 watchpoint
->set
= false;
1508 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1510 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1512 if (cortex_m
->dwt_comp_available
< 1) {
1513 LOG_DEBUG("no comparators?");
1514 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1517 /* hardware doesn't support data value masking */
1518 if (watchpoint
->mask
!= ~(uint32_t)0) {
1519 LOG_DEBUG("watchpoint value masks not supported");
1520 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1523 /* hardware allows address masks of up to 32K */
1526 for (mask
= 0; mask
< 16; mask
++) {
1527 if ((1u << mask
) == watchpoint
->length
)
1531 LOG_DEBUG("unsupported watchpoint length");
1532 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1534 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1535 LOG_DEBUG("watchpoint address is unaligned");
1536 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1539 /* Caller doesn't seem to be able to describe watching for data
1540 * values of zero; that flags "no value".
1542 * REVISIT This DWT may well be able to watch for specific data
1543 * values. Requires comparator #1 to set DATAVMATCH and match
1544 * the data, and another comparator (DATAVADDR0) matching addr.
1546 if (watchpoint
->value
) {
1547 LOG_DEBUG("data value watchpoint not YET supported");
1548 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1551 cortex_m
->dwt_comp_available
--;
1552 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1557 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1559 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1561 /* REVISIT why check? DWT can be updated with core running ... */
1562 if (target
->state
!= TARGET_HALTED
) {
1563 LOG_WARNING("target not halted");
1564 return ERROR_TARGET_NOT_HALTED
;
1567 if (watchpoint
->set
)
1568 cortex_m_unset_watchpoint(target
, watchpoint
);
1570 cortex_m
->dwt_comp_available
++;
1571 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1576 void cortex_m_enable_watchpoints(struct target
*target
)
1578 struct watchpoint
*watchpoint
= target
->watchpoints
;
1580 /* set any pending watchpoints */
1581 while (watchpoint
) {
1582 if (!watchpoint
->set
)
1583 cortex_m_set_watchpoint(target
, watchpoint
);
1584 watchpoint
= watchpoint
->next
;
1588 static int cortex_m_load_core_reg_u32(struct target
*target
,
1589 uint32_t num
, uint32_t *value
)
1593 /* NOTE: we "know" here that the register identifiers used
1594 * in the v7m header match the Cortex-M3 Debug Core Register
1595 * Selector values for R0..R15, xPSR, MSP, and PSP.
1599 /* read a normal core register */
1600 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1602 if (retval
!= ERROR_OK
) {
1603 LOG_ERROR("JTAG failure %i", retval
);
1604 return ERROR_JTAG_DEVICE_ERROR
;
1606 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1610 /* Floating-point Status and Registers */
1611 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1612 if (retval
!= ERROR_OK
)
1614 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1615 if (retval
!= ERROR_OK
)
1617 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1620 case ARMV7M_S0
... ARMV7M_S31
:
1621 /* Floating-point Status and Registers */
1622 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1623 if (retval
!= ERROR_OK
)
1625 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1626 if (retval
!= ERROR_OK
)
1628 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1629 (int)(num
- ARMV7M_S0
), *value
);
1632 case ARMV7M_PRIMASK
:
1633 case ARMV7M_BASEPRI
:
1634 case ARMV7M_FAULTMASK
:
1635 case ARMV7M_CONTROL
:
1636 /* Cortex-M3 packages these four registers as bitfields
1637 * in one Debug Core register. So say r0 and r2 docs;
1638 * it was removed from r1 docs, but still works.
1640 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1643 case ARMV7M_PRIMASK
:
1644 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1647 case ARMV7M_BASEPRI
:
1648 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1651 case ARMV7M_FAULTMASK
:
1652 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1655 case ARMV7M_CONTROL
:
1656 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1660 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1664 return ERROR_COMMAND_SYNTAX_ERROR
;
1670 static int cortex_m_store_core_reg_u32(struct target
*target
,
1671 uint32_t num
, uint32_t value
)
1675 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1677 /* NOTE: we "know" here that the register identifiers used
1678 * in the v7m header match the Cortex-M3 Debug Core Register
1679 * Selector values for R0..R15, xPSR, MSP, and PSP.
1683 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1684 if (retval
!= ERROR_OK
) {
1687 LOG_ERROR("JTAG failure");
1688 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1689 r
->dirty
= r
->valid
;
1690 return ERROR_JTAG_DEVICE_ERROR
;
1692 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1696 /* Floating-point Status and Registers */
1697 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1698 if (retval
!= ERROR_OK
)
1700 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1701 if (retval
!= ERROR_OK
)
1703 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1706 case ARMV7M_S0
... ARMV7M_S31
:
1707 /* Floating-point Status and Registers */
1708 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1709 if (retval
!= ERROR_OK
)
1711 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1712 if (retval
!= ERROR_OK
)
1714 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1715 (int)(num
- ARMV7M_S0
), value
);
1718 case ARMV7M_PRIMASK
:
1719 case ARMV7M_BASEPRI
:
1720 case ARMV7M_FAULTMASK
:
1721 case ARMV7M_CONTROL
:
1722 /* Cortex-M3 packages these four registers as bitfields
1723 * in one Debug Core register. So say r0 and r2 docs;
1724 * it was removed from r1 docs, but still works.
1726 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1729 case ARMV7M_PRIMASK
:
1730 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1733 case ARMV7M_BASEPRI
:
1734 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1737 case ARMV7M_FAULTMASK
:
1738 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1741 case ARMV7M_CONTROL
:
1742 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1746 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1748 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1752 return ERROR_COMMAND_SYNTAX_ERROR
;
1758 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
1759 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1761 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1763 if (armv7m
->arm
.is_armv6m
) {
1764 /* armv6m does not handle unaligned memory access */
1765 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1766 return ERROR_TARGET_UNALIGNED_ACCESS
;
1769 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1772 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
1773 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1775 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1777 if (armv7m
->arm
.is_armv6m
) {
1778 /* armv6m does not handle unaligned memory access */
1779 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1780 return ERROR_TARGET_UNALIGNED_ACCESS
;
1783 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1786 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1787 struct target
*target
)
1789 armv7m_build_reg_cache(target
);
1790 arm_semihosting_init(target
);
1794 void cortex_m_deinit_target(struct target
*target
)
1796 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1798 free(cortex_m
->fp_comparator_list
);
1800 cortex_m_dwt_free(target
);
1801 armv7m_free_reg_cache(target
);
1803 free(target
->private_config
);
1807 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
1808 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
1810 struct timeval timeout
, now
;
1811 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1813 bool use_pcsr
= false;
1814 int retval
= ERROR_OK
;
1817 gettimeofday(&timeout
, NULL
);
1818 timeval_add_time(&timeout
, seconds
, 0);
1820 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
1821 if (retval
!= ERROR_OK
) {
1822 LOG_ERROR("Error while reading PCSR");
1826 if (reg_value
!= 0) {
1828 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1830 LOG_INFO("Starting profiling. Halting and resuming the"
1831 " target as often as we can...");
1832 reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
1835 /* Make sure the target is running */
1836 target_poll(target
);
1837 if (target
->state
== TARGET_HALTED
)
1838 retval
= target_resume(target
, 1, 0, 0, 0);
1840 if (retval
!= ERROR_OK
) {
1841 LOG_ERROR("Error while resuming target");
1845 uint32_t sample_count
= 0;
1849 if (armv7m
&& armv7m
->debug_ap
) {
1850 uint32_t read_count
= max_num_samples
- sample_count
;
1851 if (read_count
> 1024)
1854 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
1855 (void *)&samples
[sample_count
],
1856 4, read_count
, DWT_PCSR
);
1857 sample_count
+= read_count
;
1859 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
1862 target_poll(target
);
1863 if (target
->state
== TARGET_HALTED
) {
1864 reg_value
= buf_get_u32(reg
->value
, 0, 32);
1865 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1866 retval
= target_resume(target
, 1, 0, 0, 0);
1867 samples
[sample_count
++] = reg_value
;
1868 target_poll(target
);
1869 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1870 } else if (target
->state
== TARGET_RUNNING
) {
1871 /* We want to quickly sample the PC. */
1872 retval
= target_halt(target
);
1874 LOG_INFO("Target not halted or running");
1880 if (retval
!= ERROR_OK
) {
1881 LOG_ERROR("Error while reading %s", use_pcsr
? "PCSR" : "target pc");
1886 gettimeofday(&now
, NULL
);
1887 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
1888 LOG_INFO("Profiling completed. %" PRIu32
" samples.", sample_count
);
1893 *num_samples
= sample_count
;
1898 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1899 * on r/w if the core is not running, and clear on resume or reset ... or
1900 * at least, in a post_restore_context() method.
1903 struct dwt_reg_state
{
1904 struct target
*target
;
1906 uint8_t value
[4]; /* scratch/cache */
1909 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1911 struct dwt_reg_state
*state
= reg
->arch_info
;
1914 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1915 if (retval
!= ERROR_OK
)
1918 buf_set_u32(state
->value
, 0, 32, tmp
);
1922 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1924 struct dwt_reg_state
*state
= reg
->arch_info
;
1926 return target_write_u32(state
->target
, state
->addr
,
1927 buf_get_u32(buf
, 0, reg
->size
));
1936 static const struct dwt_reg dwt_base_regs
[] = {
1937 { DWT_CTRL
, "dwt_ctrl", 32, },
1938 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1939 * increments while the core is asleep.
1941 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1942 /* plus some 8 bit counters, useful for profiling with TPIU */
1945 static const struct dwt_reg dwt_comp
[] = {
1946 #define DWT_COMPARATOR(i) \
1947 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1948 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1949 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1966 #undef DWT_COMPARATOR
1969 static const struct reg_arch_type dwt_reg_type
= {
1970 .get
= cortex_m_dwt_get_reg
,
1971 .set
= cortex_m_dwt_set_reg
,
1974 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
1976 struct dwt_reg_state
*state
;
1978 state
= calloc(1, sizeof *state
);
1981 state
->addr
= d
->addr
;
1986 r
->value
= state
->value
;
1987 r
->arch_info
= state
;
1988 r
->type
= &dwt_reg_type
;
1991 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1994 struct reg_cache
*cache
;
1995 struct cortex_m_dwt_comparator
*comparator
;
1998 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1999 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32
, dwtcr
);
2001 LOG_DEBUG("no DWT");
2005 target_read_u32(target
, DWT_DEVARCH
, &cm
->dwt_devarch
);
2006 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32
, cm
->dwt_devarch
);
2008 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
2009 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
2010 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
2011 sizeof(struct cortex_m_dwt_comparator
));
2012 if (!cm
->dwt_comparator_list
) {
2014 cm
->dwt_num_comp
= 0;
2015 LOG_ERROR("out of mem");
2019 cache
= calloc(1, sizeof *cache
);
2022 free(cm
->dwt_comparator_list
);
2025 cache
->name
= "Cortex-M DWT registers";
2026 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
2027 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
2028 if (!cache
->reg_list
) {
2033 for (reg
= 0; reg
< 2; reg
++)
2034 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2035 dwt_base_regs
+ reg
);
2037 comparator
= cm
->dwt_comparator_list
;
2038 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
2041 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
2042 for (j
= 0; j
< 3; j
++, reg
++)
2043 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2044 dwt_comp
+ 3 * i
+ j
);
2046 /* make sure we clear any watchpoints enabled on the target */
2047 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
2050 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
2051 cm
->dwt_cache
= cache
;
2053 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
2054 dwtcr
, cm
->dwt_num_comp
,
2055 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
2057 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2058 * implement single-address data value watchpoints ... so we
2059 * won't need to check it later, when asked to set one up.
2063 static void cortex_m_dwt_free(struct target
*target
)
2065 struct cortex_m_common
*cm
= target_to_cm(target
);
2066 struct reg_cache
*cache
= cm
->dwt_cache
;
2068 free(cm
->dwt_comparator_list
);
2069 cm
->dwt_comparator_list
= NULL
;
2070 cm
->dwt_num_comp
= 0;
2073 register_unlink_cache(&target
->reg_cache
, cache
);
2075 if (cache
->reg_list
) {
2076 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
2077 free(cache
->reg_list
[i
].arch_info
);
2078 free(cache
->reg_list
);
2082 cm
->dwt_cache
= NULL
;
2085 #define MVFR0 0xe000ef40
2086 #define MVFR1 0xe000ef44
2088 #define MVFR0_DEFAULT_M4 0x10110021
2089 #define MVFR1_DEFAULT_M4 0x11000011
2091 #define MVFR0_DEFAULT_M7_SP 0x10110021
2092 #define MVFR0_DEFAULT_M7_DP 0x10110221
2093 #define MVFR1_DEFAULT_M7_SP 0x11000011
2094 #define MVFR1_DEFAULT_M7_DP 0x12000011
2096 int cortex_m_examine(struct target
*target
)
2099 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
2101 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2102 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
2103 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2105 /* stlink shares the examine handler but does not support
2107 if (!armv7m
->stlink
) {
2108 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
2109 /* Search for the MEM-AP */
2110 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB3_AP
, &armv7m
->debug_ap
);
2111 if (retval
!= ERROR_OK
) {
2112 LOG_ERROR("Could not find MEM-AP to control the core");
2116 armv7m
->debug_ap
= dap_ap(swjdp
, cortex_m
->apsel
);
2119 /* Leave (only) generic DAP stuff for debugport_init(); */
2120 armv7m
->debug_ap
->memaccess_tck
= 8;
2122 retval
= mem_ap_init(armv7m
->debug_ap
);
2123 if (retval
!= ERROR_OK
)
2127 if (!target_was_examined(target
)) {
2128 target_set_examined(target
);
2130 /* Read from Device Identification Registers */
2131 retval
= target_read_u32(target
, CPUID
, &cpuid
);
2132 if (retval
!= ERROR_OK
)
2136 i
= (cpuid
>> 4) & 0xf;
2138 switch (cpuid
& ARM_CPUID_PARTNO_MASK
) {
2139 case CORTEX_M23_PARTNO
:
2143 case CORTEX_M33_PARTNO
:
2152 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
2153 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
2154 cortex_m
->maskints_erratum
= false;
2157 rev
= (cpuid
>> 20) & 0xf;
2158 patch
= (cpuid
>> 0) & 0xf;
2159 if ((rev
== 0) && (patch
< 2)) {
2160 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2161 cortex_m
->maskints_erratum
= true;
2164 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
2166 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2167 cortex_m
->vectreset_supported
= i
> 1;
2170 target_read_u32(target
, MVFR0
, &mvfr0
);
2171 target_read_u32(target
, MVFR1
, &mvfr1
);
2173 /* test for floating point feature on Cortex-M4 */
2174 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2175 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
2176 armv7m
->fp_feature
= FPv4_SP
;
2178 } else if (i
== 7 || i
== 33) {
2179 target_read_u32(target
, MVFR0
, &mvfr0
);
2180 target_read_u32(target
, MVFR1
, &mvfr1
);
2182 /* test for floating point features on Cortex-M7 */
2183 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2184 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
2185 armv7m
->fp_feature
= FPv5_SP
;
2186 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2187 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
2188 armv7m
->fp_feature
= FPv5_DP
;
2190 } else if (i
== 0) {
2191 /* Cortex-M0 does not support unaligned memory access */
2192 armv7m
->arm
.is_armv6m
= true;
2195 if (armv7m
->fp_feature
== FP_NONE
&&
2196 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
2197 /* free unavailable FPU registers */
2200 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
2201 idx
< armv7m
->arm
.core_cache
->num_regs
;
2203 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
2204 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
2205 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
2207 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
2210 if (!armv7m
->stlink
) {
2211 if (i
== 3 || i
== 4)
2212 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2213 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2214 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2216 /* Cortex-M7 has only 1024 bytes autoincrement range */
2217 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
2220 /* Configure trace modules */
2221 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2222 if (retval
!= ERROR_OK
)
2225 if (armv7m
->trace_config
.config_type
!= TRACE_CONFIG_TYPE_DISABLED
) {
2226 armv7m_trace_tpiu_config(target
);
2227 armv7m_trace_itm_config(target
);
2230 /* NOTE: FPB and DWT are both optional. */
2233 target_read_u32(target
, FP_CTRL
, &fpcr
);
2234 /* bits [14:12] and [7:4] */
2235 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2236 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2237 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2238 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2239 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2240 free(cortex_m
->fp_comparator_list
);
2241 cortex_m
->fp_comparator_list
= calloc(
2242 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2243 sizeof(struct cortex_m_fp_comparator
));
2244 cortex_m
->fpb_enabled
= fpcr
& 1;
2245 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2246 cortex_m
->fp_comparator_list
[i
].type
=
2247 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2248 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2250 /* make sure we clear any breakpoints enabled on the target */
2251 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2253 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2255 cortex_m
->fp_num_code
,
2256 cortex_m
->fp_num_lit
);
2259 cortex_m_dwt_free(target
);
2260 cortex_m_dwt_setup(cortex_m
, target
);
2262 /* These hardware breakpoints only work for code in flash! */
2263 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2264 target_name(target
),
2265 cortex_m
->fp_num_code
,
2266 cortex_m
->dwt_num_comp
);
2272 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2274 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2279 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2280 if (retval
!= ERROR_OK
)
2283 dcrdr
= target_buffer_get_u16(target
, buf
);
2284 *ctrl
= (uint8_t)dcrdr
;
2285 *value
= (uint8_t)(dcrdr
>> 8);
2287 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2289 /* write ack back to software dcc register
2290 * signify we have read data */
2291 if (dcrdr
& (1 << 0)) {
2292 target_buffer_set_u16(target
, buf
, 0);
2293 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2294 if (retval
!= ERROR_OK
)
2301 static int cortex_m_target_request_data(struct target
*target
,
2302 uint32_t size
, uint8_t *buffer
)
2308 for (i
= 0; i
< (size
* 4); i
++) {
2309 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2310 if (retval
!= ERROR_OK
)
2318 static int cortex_m_handle_target_request(void *priv
)
2320 struct target
*target
= priv
;
2321 if (!target_was_examined(target
))
2324 if (!target
->dbg_msg_enabled
)
2327 if (target
->state
== TARGET_RUNNING
) {
2332 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2333 if (retval
!= ERROR_OK
)
2336 /* check if we have data */
2337 if (ctrl
& (1 << 0)) {
2340 /* we assume target is quick enough */
2342 for (int i
= 1; i
<= 3; i
++) {
2343 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2344 if (retval
!= ERROR_OK
)
2346 request
|= ((uint32_t)data
<< (i
* 8));
2348 target_request(target
, request
);
2355 static int cortex_m_init_arch_info(struct target
*target
,
2356 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2358 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2360 armv7m_init_arch_info(target
, armv7m
);
2362 /* default reset mode is to use srst if fitted
2363 * if not it will use CORTEX_M3_RESET_VECTRESET */
2364 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2366 armv7m
->arm
.dap
= dap
;
2368 /* register arch-specific functions */
2369 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2371 armv7m
->post_debug_entry
= NULL
;
2373 armv7m
->pre_restore_context
= NULL
;
2375 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2376 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2378 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2379 TARGET_TIMER_TYPE_PERIODIC
, target
);
2384 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2386 struct adiv5_private_config
*pc
;
2388 pc
= (struct adiv5_private_config
*)target
->private_config
;
2389 if (adiv5_verify_config(pc
) != ERROR_OK
)
2392 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2393 if (cortex_m
== NULL
) {
2394 LOG_ERROR("No memory creating target");
2398 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2399 cortex_m
->apsel
= pc
->ap_num
;
2401 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2406 /*--------------------------------------------------------------------------*/
2408 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2409 struct cortex_m_common
*cm
)
2411 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2412 command_print(cmd
, "target is not a Cortex-M");
2413 return ERROR_TARGET_INVALID
;
2419 * Only stuff below this line should need to verify that its target
2420 * is a Cortex-M3. Everything else should have indirected through the
2421 * cortexm3_target structure, which is only used with CM3 targets.
2424 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2426 struct target
*target
= get_current_target(CMD_CTX
);
2427 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2428 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2432 static const struct {
2436 { "hard_err", VC_HARDERR
, },
2437 { "int_err", VC_INTERR
, },
2438 { "bus_err", VC_BUSERR
, },
2439 { "state_err", VC_STATERR
, },
2440 { "chk_err", VC_CHKERR
, },
2441 { "nocp_err", VC_NOCPERR
, },
2442 { "mm_err", VC_MMERR
, },
2443 { "reset", VC_CORERESET
, },
2446 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2447 if (retval
!= ERROR_OK
)
2450 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2451 if (retval
!= ERROR_OK
)
2457 if (CMD_ARGC
== 1) {
2458 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2459 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2460 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2461 | VC_MMERR
| VC_CORERESET
;
2463 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2466 while (CMD_ARGC
-- > 0) {
2468 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2469 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2471 catch |= vec_ids
[i
].mask
;
2474 if (i
== ARRAY_SIZE(vec_ids
)) {
2475 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2476 return ERROR_COMMAND_SYNTAX_ERROR
;
2480 /* For now, armv7m->demcr only stores vector catch flags. */
2481 armv7m
->demcr
= catch;
2486 /* write, but don't assume it stuck (why not??) */
2487 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2488 if (retval
!= ERROR_OK
)
2490 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2491 if (retval
!= ERROR_OK
)
2494 /* FIXME be sure to clear DEMCR on clean server shutdown.
2495 * Otherwise the vector catch hardware could fire when there's
2496 * no debugger hooked up, causing much confusion...
2500 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2501 command_print(CMD
, "%9s: %s", vec_ids
[i
].name
,
2502 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2508 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2510 struct target
*target
= get_current_target(CMD_CTX
);
2511 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2514 static const Jim_Nvp nvp_maskisr_modes
[] = {
2515 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2516 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2517 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2518 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2519 { .name
= NULL
, .value
= -1 },
2524 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2525 if (retval
!= ERROR_OK
)
2528 if (target
->state
!= TARGET_HALTED
) {
2529 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
2534 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2535 if (n
->name
== NULL
)
2536 return ERROR_COMMAND_SYNTAX_ERROR
;
2537 cortex_m
->isrmasking_mode
= n
->value
;
2538 cortex_m_set_maskints_for_halt(target
);
2541 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2542 command_print(CMD
, "cortex_m interrupt mask %s", n
->name
);
2547 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2549 struct target
*target
= get_current_target(CMD_CTX
);
2550 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2554 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2555 if (retval
!= ERROR_OK
)
2559 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2560 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2562 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2563 if (target_was_examined(target
)
2564 && !cortex_m
->vectreset_supported
)
2565 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2567 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2570 return ERROR_COMMAND_SYNTAX_ERROR
;
2573 switch (cortex_m
->soft_reset_config
) {
2574 case CORTEX_M_RESET_SYSRESETREQ
:
2575 reset_config
= "sysresetreq";
2578 case CORTEX_M_RESET_VECTRESET
:
2579 reset_config
= "vectreset";
2583 reset_config
= "unknown";
2587 command_print(CMD
, "cortex_m reset_config %s", reset_config
);
2592 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2595 .handler
= handle_cortex_m_mask_interrupts_command
,
2596 .mode
= COMMAND_EXEC
,
2597 .help
= "mask cortex_m interrupts",
2598 .usage
= "['auto'|'on'|'off'|'steponly']",
2601 .name
= "vector_catch",
2602 .handler
= handle_cortex_m_vector_catch_command
,
2603 .mode
= COMMAND_EXEC
,
2604 .help
= "configure hardware vectors to trigger debug entry",
2605 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2608 .name
= "reset_config",
2609 .handler
= handle_cortex_m_reset_config_command
,
2610 .mode
= COMMAND_ANY
,
2611 .help
= "configure software reset handling",
2612 .usage
= "['sysresetreq'|'vectreset']",
2614 COMMAND_REGISTRATION_DONE
2616 static const struct command_registration cortex_m_command_handlers
[] = {
2618 .chain
= armv7m_command_handlers
,
2621 .chain
= armv7m_trace_command_handlers
,
2625 .mode
= COMMAND_EXEC
,
2626 .help
= "Cortex-M command group",
2628 .chain
= cortex_m_exec_command_handlers
,
2630 COMMAND_REGISTRATION_DONE
2633 struct target_type cortexm_target
= {
2635 .deprecated_name
= "cortex_m3",
2637 .poll
= cortex_m_poll
,
2638 .arch_state
= armv7m_arch_state
,
2640 .target_request_data
= cortex_m_target_request_data
,
2642 .halt
= cortex_m_halt
,
2643 .resume
= cortex_m_resume
,
2644 .step
= cortex_m_step
,
2646 .assert_reset
= cortex_m_assert_reset
,
2647 .deassert_reset
= cortex_m_deassert_reset
,
2648 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2650 .get_gdb_arch
= arm_get_gdb_arch
,
2651 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2653 .read_memory
= cortex_m_read_memory
,
2654 .write_memory
= cortex_m_write_memory
,
2655 .checksum_memory
= armv7m_checksum_memory
,
2656 .blank_check_memory
= armv7m_blank_check_memory
,
2658 .run_algorithm
= armv7m_run_algorithm
,
2659 .start_algorithm
= armv7m_start_algorithm
,
2660 .wait_algorithm
= armv7m_wait_algorithm
,
2662 .add_breakpoint
= cortex_m_add_breakpoint
,
2663 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2664 .add_watchpoint
= cortex_m_add_watchpoint
,
2665 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2667 .commands
= cortex_m_command_handlers
,
2668 .target_create
= cortex_m_target_create
,
2669 .target_jim_configure
= adiv5_jim_configure
,
2670 .init_target
= cortex_m_init_target
,
2671 .examine
= cortex_m_examine
,
2672 .deinit_target
= cortex_m_deinit_target
,
2674 .profiling
= cortex_m_profiling
,
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