1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target
*target
,
56 uint32_t num
, uint32_t value
);
57 static void cortex_m_dwt_free(struct target
*target
);
59 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
60 uint32_t *value
, int regnum
)
62 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target
->dbg_msg_enabled
) {
69 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
70 if (retval
!= ERROR_OK
)
74 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
);
75 if (retval
!= ERROR_OK
)
78 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
79 if (retval
!= ERROR_OK
)
82 if (target
->dbg_msg_enabled
) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval
== ERROR_OK
)
86 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
92 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
93 uint32_t value
, int regnum
)
95 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target
->dbg_msg_enabled
) {
102 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
103 if (retval
!= ERROR_OK
)
107 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
108 if (retval
!= ERROR_OK
)
111 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
112 if (retval
!= ERROR_OK
)
115 if (target
->dbg_msg_enabled
) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval
== ERROR_OK
)
119 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
125 static int cortex_m_write_debug_halt_mask(struct target
*target
,
126 uint32_t mask_on
, uint32_t mask_off
)
128 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
129 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
131 /* mask off status bits */
132 cortex_m
->dcb_dhcsr
&= ~((0xFFFFul
<< 16) | mask_off
);
133 /* create new register mask */
134 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
136 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
139 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
141 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
142 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
143 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
148 static int cortex_m_set_maskints_for_halt(struct target
*target
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 switch (cortex_m
->isrmasking_mode
) {
152 case CORTEX_M_ISRMASK_AUTO
:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target
, false);
156 case CORTEX_M_ISRMASK_OFF
:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target
, false);
160 case CORTEX_M_ISRMASK_ON
:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target
, true);
164 case CORTEX_M_ISRMASK_STEPONLY
:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
172 static int cortex_m_set_maskints_for_run(struct target
*target
)
174 switch (target_to_cm(target
)->isrmasking_mode
) {
175 case CORTEX_M_ISRMASK_AUTO
:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target
, false);
179 case CORTEX_M_ISRMASK_OFF
:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target
, false);
183 case CORTEX_M_ISRMASK_ON
:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target
, true);
187 case CORTEX_M_ISRMASK_STEPONLY
:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target
, false);
194 static int cortex_m_set_maskints_for_step(struct target
*target
)
196 switch (target_to_cm(target
)->isrmasking_mode
) {
197 case CORTEX_M_ISRMASK_AUTO
:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target
, true);
201 case CORTEX_M_ISRMASK_OFF
:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target
, false);
205 case CORTEX_M_ISRMASK_ON
:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target
, true);
209 case CORTEX_M_ISRMASK_STEPONLY
:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target
, true);
216 static int cortex_m_clear_halt(struct target
*target
)
218 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
219 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
225 /* Read Debug Fault Status Register */
226 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
227 if (retval
!= ERROR_OK
)
230 /* Clear Debug Fault Status */
231 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
232 if (retval
!= ERROR_OK
)
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
239 static int cortex_m_single_step_core(struct target
*target
)
241 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
242 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
249 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
250 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
251 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
252 if (retval
!= ERROR_OK
)
255 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
256 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
257 if (retval
!= ERROR_OK
)
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target
);
267 static int cortex_m_enable_fpb(struct target
*target
)
269 int retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 /* check the fpb is actually enabled */
275 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
276 if (retval
!= ERROR_OK
)
285 static int cortex_m_endreset_event(struct target
*target
)
290 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
291 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
292 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
293 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
294 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
298 if (retval
!= ERROR_OK
)
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
302 /* this register is used for emulated dcc channel */
303 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
304 if (retval
!= ERROR_OK
)
307 /* Enable debug requests */
308 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
309 if (retval
!= ERROR_OK
)
311 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
312 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
313 if (retval
!= ERROR_OK
)
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target
);
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
327 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
328 if (retval
!= ERROR_OK
)
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
336 retval
= cortex_m_enable_fpb(target
);
337 if (retval
!= ERROR_OK
) {
338 LOG_ERROR("Failed to enable the FPB");
342 cortex_m
->fpb_enabled
= true;
344 /* Restore FPB registers */
345 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
346 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
347 if (retval
!= ERROR_OK
)
351 /* Restore DWT registers */
352 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
353 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
355 if (retval
!= ERROR_OK
)
357 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
359 if (retval
!= ERROR_OK
)
361 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
362 dwt_list
[i
].function
);
363 if (retval
!= ERROR_OK
)
366 retval
= dap_run(swjdp
);
367 if (retval
!= ERROR_OK
)
370 register_cache_invalidate(armv7m
->arm
.core_cache
);
372 /* make sure we have latest dhcsr flags */
373 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
378 static int cortex_m_examine_debug_reason(struct target
*target
)
380 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
385 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
386 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
387 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
388 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
389 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
390 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
391 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
392 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
393 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
394 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
395 else if (cortex_m
->nvic_dfsr
& DFSR_EXTERNAL
)
396 target
->debug_reason
= DBG_REASON_DBGRQ
;
398 target
->debug_reason
= DBG_REASON_UNDEFINED
;
404 static int cortex_m_examine_exception_reason(struct target
*target
)
406 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
407 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
408 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
411 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
412 if (retval
!= ERROR_OK
)
414 switch (armv7m
->exception_number
) {
417 case 3: /* Hard Fault */
418 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
419 if (retval
!= ERROR_OK
)
421 if (except_sr
& 0x40000000) {
422 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
423 if (retval
!= ERROR_OK
)
427 case 4: /* Memory Management */
428 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
429 if (retval
!= ERROR_OK
)
431 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
432 if (retval
!= ERROR_OK
)
435 case 5: /* Bus Fault */
436 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
437 if (retval
!= ERROR_OK
)
439 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
440 if (retval
!= ERROR_OK
)
443 case 6: /* Usage Fault */
444 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
445 if (retval
!= ERROR_OK
)
448 case 11: /* SVCall */
450 case 12: /* Debug Monitor */
451 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
452 if (retval
!= ERROR_OK
)
455 case 14: /* PendSV */
457 case 15: /* SysTick */
463 retval
= dap_run(swjdp
);
464 if (retval
== ERROR_OK
)
465 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
466 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
467 armv7m_exception_string(armv7m
->exception_number
),
468 shcsr
, except_sr
, cfsr
, except_ar
);
472 static int cortex_m_debug_entry(struct target
*target
)
477 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
478 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
479 struct arm
*arm
= &armv7m
->arm
;
484 /* Do this really early to minimize the window where the MASKINTS erratum
485 * can pile up pending interrupts. */
486 cortex_m_set_maskints_for_halt(target
);
488 cortex_m_clear_halt(target
);
489 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
490 if (retval
!= ERROR_OK
)
493 retval
= armv7m
->examine_debug_reason(target
);
494 if (retval
!= ERROR_OK
)
497 /* Examine target state and mode
498 * First load register accessible through core debug port */
499 int num_regs
= arm
->core_cache
->num_regs
;
501 for (i
= 0; i
< num_regs
; i
++) {
502 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
504 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
508 xPSR
= buf_get_u32(r
->value
, 0, 32);
510 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
513 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
516 /* Are we in an exception handler */
518 armv7m
->exception_number
= (xPSR
& 0x1FF);
520 arm
->core_mode
= ARM_MODE_HANDLER
;
521 arm
->map
= armv7m_msp_reg_map
;
523 unsigned control
= buf_get_u32(arm
->core_cache
524 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
526 /* is this thread privileged? */
527 arm
->core_mode
= control
& 1
528 ? ARM_MODE_USER_THREAD
531 /* which stack is it using? */
533 arm
->map
= armv7m_psp_reg_map
;
535 arm
->map
= armv7m_msp_reg_map
;
537 armv7m
->exception_number
= 0;
540 if (armv7m
->exception_number
)
541 cortex_m_examine_exception_reason(target
);
543 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
544 arm_mode_name(arm
->core_mode
),
545 buf_get_u32(arm
->pc
->value
, 0, 32),
546 target_state_name(target
));
548 if (armv7m
->post_debug_entry
) {
549 retval
= armv7m
->post_debug_entry(target
);
550 if (retval
!= ERROR_OK
)
557 static int cortex_m_poll(struct target
*target
)
559 int detected_failure
= ERROR_OK
;
560 int retval
= ERROR_OK
;
561 enum target_state prev_target_state
= target
->state
;
562 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
563 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
565 /* Read from Debug Halting Control and Status Register */
566 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
567 if (retval
!= ERROR_OK
) {
568 target
->state
= TARGET_UNKNOWN
;
572 /* Recover from lockup. See ARMv7-M architecture spec,
573 * section B1.5.15 "Unrecoverable exception cases".
575 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
576 LOG_ERROR("%s -- clearing lockup after double fault",
577 target_name(target
));
578 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
579 target
->debug_reason
= DBG_REASON_DBGRQ
;
581 /* We have to execute the rest (the "finally" equivalent, but
582 * still throw this exception again).
584 detected_failure
= ERROR_FAIL
;
586 /* refresh status bits */
587 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
588 if (retval
!= ERROR_OK
)
592 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
593 if (target
->state
!= TARGET_RESET
) {
594 target
->state
= TARGET_RESET
;
595 LOG_INFO("%s: external reset detected", target_name(target
));
600 if (target
->state
== TARGET_RESET
) {
601 /* Cannot switch context while running so endreset is
602 * called with target->state == TARGET_RESET
604 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
605 cortex_m
->dcb_dhcsr
);
606 retval
= cortex_m_endreset_event(target
);
607 if (retval
!= ERROR_OK
) {
608 target
->state
= TARGET_UNKNOWN
;
611 target
->state
= TARGET_RUNNING
;
612 prev_target_state
= TARGET_RUNNING
;
615 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
616 target
->state
= TARGET_HALTED
;
618 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
619 retval
= cortex_m_debug_entry(target
);
620 if (retval
!= ERROR_OK
)
623 if (arm_semihosting(target
, &retval
) != 0)
626 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
628 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
630 retval
= cortex_m_debug_entry(target
);
631 if (retval
!= ERROR_OK
)
634 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
638 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
639 * How best to model low power modes?
642 if (target
->state
== TARGET_UNKNOWN
) {
643 /* check if processor is retiring instructions */
644 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
645 target
->state
= TARGET_RUNNING
;
650 /* Check that target is truly halted, since the target could be resumed externally */
651 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
652 /* registers are now invalid */
653 register_cache_invalidate(armv7m
->arm
.core_cache
);
655 target
->state
= TARGET_RUNNING
;
656 LOG_WARNING("%s: external resume detected", target_name(target
));
657 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
661 /* Did we detect a failure condition that we cleared? */
662 if (detected_failure
!= ERROR_OK
)
663 retval
= detected_failure
;
667 static int cortex_m_halt(struct target
*target
)
669 LOG_DEBUG("target->state: %s",
670 target_state_name(target
));
672 if (target
->state
== TARGET_HALTED
) {
673 LOG_DEBUG("target was already halted");
677 if (target
->state
== TARGET_UNKNOWN
)
678 LOG_WARNING("target was in unknown state when halt was requested");
680 if (target
->state
== TARGET_RESET
) {
681 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
682 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
683 return ERROR_TARGET_FAILURE
;
685 /* we came here in a reset_halt or reset_init sequence
686 * debug entry was already prepared in cortex_m3_assert_reset()
688 target
->debug_reason
= DBG_REASON_DBGRQ
;
694 /* Write to Debug Halting Control and Status Register */
695 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
697 /* Do this really early to minimize the window where the MASKINTS erratum
698 * can pile up pending interrupts. */
699 cortex_m_set_maskints_for_halt(target
);
701 target
->debug_reason
= DBG_REASON_DBGRQ
;
706 static int cortex_m_soft_reset_halt(struct target
*target
)
708 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
709 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
710 uint32_t dcb_dhcsr
= 0;
711 int retval
, timeout
= 0;
713 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
714 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
715 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
716 * core, not the peripherals */
717 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
720 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_STEP
| C_MASKINTS
);
721 if (retval
!= ERROR_OK
)
724 /* Enter debug state on reset; restore DEMCR in endreset_event() */
725 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
726 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
727 if (retval
!= ERROR_OK
)
730 /* Request a core-only reset */
731 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
732 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
733 if (retval
!= ERROR_OK
)
735 target
->state
= TARGET_RESET
;
737 /* registers are now invalid */
738 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
740 while (timeout
< 100) {
741 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
742 if (retval
== ERROR_OK
) {
743 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
744 &cortex_m
->nvic_dfsr
);
745 if (retval
!= ERROR_OK
)
747 if ((dcb_dhcsr
& S_HALT
)
748 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
749 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
751 (unsigned) dcb_dhcsr
,
752 (unsigned) cortex_m
->nvic_dfsr
);
753 cortex_m_poll(target
);
754 /* FIXME restore user's vector catch config */
757 LOG_DEBUG("waiting for system reset-halt, "
758 "DHCSR 0x%08x, %d ms",
759 (unsigned) dcb_dhcsr
, timeout
);
768 void cortex_m_enable_breakpoints(struct target
*target
)
770 struct breakpoint
*breakpoint
= target
->breakpoints
;
772 /* set any pending breakpoints */
774 if (!breakpoint
->set
)
775 cortex_m_set_breakpoint(target
, breakpoint
);
776 breakpoint
= breakpoint
->next
;
780 static int cortex_m_resume(struct target
*target
, int current
,
781 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
783 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
784 struct breakpoint
*breakpoint
= NULL
;
788 if (target
->state
!= TARGET_HALTED
) {
789 LOG_WARNING("target not halted");
790 return ERROR_TARGET_NOT_HALTED
;
793 if (!debug_execution
) {
794 target_free_all_working_areas(target
);
795 cortex_m_enable_breakpoints(target
);
796 cortex_m_enable_watchpoints(target
);
799 if (debug_execution
) {
800 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
802 /* Disable interrupts */
803 /* We disable interrupts in the PRIMASK register instead of
804 * masking with C_MASKINTS. This is probably the same issue
805 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
806 * in parallel with disabled interrupts can cause local faults
809 * REVISIT this clearly breaks non-debug execution, since the
810 * PRIMASK register state isn't saved/restored... workaround
811 * by never resuming app code after debug execution.
813 buf_set_u32(r
->value
, 0, 1, 1);
817 /* Make sure we are in Thumb mode */
818 r
= armv7m
->arm
.cpsr
;
819 buf_set_u32(r
->value
, 24, 1, 1);
824 /* current = 1: continue on current pc, otherwise continue at <address> */
827 buf_set_u32(r
->value
, 0, 32, address
);
832 /* if we halted last time due to a bkpt instruction
833 * then we have to manually step over it, otherwise
834 * the core will break again */
836 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
838 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
840 resume_pc
= buf_get_u32(r
->value
, 0, 32);
842 armv7m_restore_context(target
);
844 /* the front-end may request us not to handle breakpoints */
845 if (handle_breakpoints
) {
846 /* Single step past breakpoint at current address */
847 breakpoint
= breakpoint_find(target
, resume_pc
);
849 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
851 breakpoint
->unique_id
);
852 cortex_m_unset_breakpoint(target
, breakpoint
);
853 cortex_m_single_step_core(target
);
854 cortex_m_set_breakpoint(target
, breakpoint
);
859 cortex_m_set_maskints_for_run(target
);
860 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
862 target
->debug_reason
= DBG_REASON_NOTHALTED
;
864 /* registers are now invalid */
865 register_cache_invalidate(armv7m
->arm
.core_cache
);
867 if (!debug_execution
) {
868 target
->state
= TARGET_RUNNING
;
869 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
870 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
872 target
->state
= TARGET_DEBUG_RUNNING
;
873 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
874 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
880 /* int irqstepcount = 0; */
881 static int cortex_m_step(struct target
*target
, int current
,
882 target_addr_t address
, int handle_breakpoints
)
884 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
885 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
886 struct breakpoint
*breakpoint
= NULL
;
887 struct reg
*pc
= armv7m
->arm
.pc
;
888 bool bkpt_inst_found
= false;
890 bool isr_timed_out
= false;
892 if (target
->state
!= TARGET_HALTED
) {
893 LOG_WARNING("target not halted");
894 return ERROR_TARGET_NOT_HALTED
;
897 /* current = 1: continue on current pc, otherwise continue at <address> */
899 buf_set_u32(pc
->value
, 0, 32, address
);
901 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
903 /* the front-end may request us not to handle breakpoints */
904 if (handle_breakpoints
) {
905 breakpoint
= breakpoint_find(target
, pc_value
);
907 cortex_m_unset_breakpoint(target
, breakpoint
);
910 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
912 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
914 armv7m_restore_context(target
);
916 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
918 /* if no bkpt instruction is found at pc then we can perform
919 * a normal step, otherwise we have to manually step over the bkpt
920 * instruction - as such simulate a step */
921 if (bkpt_inst_found
== false) {
922 if (cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
) {
923 /* Automatic ISR masking mode off: Just step over the next
924 * instruction, with interrupts on or off as appropriate. */
925 cortex_m_set_maskints_for_step(target
);
926 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
928 /* Process interrupts during stepping in a way they don't interfere
933 * Set a temporary break point at the current pc and let the core run
934 * with interrupts enabled. Pending interrupts get served and we run
935 * into the breakpoint again afterwards. Then we step over the next
936 * instruction with interrupts disabled.
938 * If the pending interrupts don't complete within time, we leave the
939 * core running. This may happen if the interrupts trigger faster
940 * than the core can process them or the handler doesn't return.
942 * If no more breakpoints are available we simply do a step with
943 * interrupts enabled.
949 * If a break point is already set on the lower half word then a break point on
950 * the upper half word will not break again when the core is restarted. So we
951 * just step over the instruction with interrupts disabled.
953 * The documentation has no information about this, it was found by observation
954 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
955 * suffer from this problem.
957 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
958 * address has it always cleared. The former is done to indicate thumb mode
962 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
963 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
964 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
965 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
966 /* Re-enable interrupts if appropriate */
967 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
968 cortex_m_set_maskints_for_halt(target
);
971 /* Set a temporary break point */
973 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
975 enum breakpoint_type type
= BKPT_HARD
;
976 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
977 /* FPB rev.1 cannot handle such addr, try BKPT instr */
980 retval
= breakpoint_add(target
, pc_value
, 2, type
);
983 bool tmp_bp_set
= (retval
== ERROR_OK
);
985 /* No more breakpoints left, just do a step */
987 cortex_m_set_maskints_for_step(target
);
988 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
989 /* Re-enable interrupts if appropriate */
990 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
991 cortex_m_set_maskints_for_halt(target
);
994 LOG_DEBUG("Starting core to serve pending interrupts");
995 int64_t t_start
= timeval_ms();
996 cortex_m_set_maskints_for_run(target
);
997 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
999 /* Wait for pending handlers to complete or timeout */
1001 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
1003 &cortex_m
->dcb_dhcsr
);
1004 if (retval
!= ERROR_OK
) {
1005 target
->state
= TARGET_UNKNOWN
;
1008 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1009 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1011 /* only remove breakpoint if we created it */
1013 cortex_m_unset_breakpoint(target
, breakpoint
);
1015 /* Remove the temporary breakpoint */
1016 breakpoint_remove(target
, pc_value
);
1019 if (isr_timed_out
) {
1020 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1021 "leaving target running");
1023 /* Step over next instruction with interrupts disabled */
1024 cortex_m_set_maskints_for_step(target
);
1025 cortex_m_write_debug_halt_mask(target
,
1026 C_HALT
| C_MASKINTS
,
1028 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1029 /* Re-enable interrupts if appropriate */
1030 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1031 cortex_m_set_maskints_for_halt(target
);
1038 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1039 if (retval
!= ERROR_OK
)
1042 /* registers are now invalid */
1043 register_cache_invalidate(armv7m
->arm
.core_cache
);
1046 cortex_m_set_breakpoint(target
, breakpoint
);
1048 if (isr_timed_out
) {
1049 /* Leave the core running. The user has to stop execution manually. */
1050 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1051 target
->state
= TARGET_RUNNING
;
1055 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1056 " nvic_icsr = 0x%" PRIx32
,
1057 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1059 retval
= cortex_m_debug_entry(target
);
1060 if (retval
!= ERROR_OK
)
1062 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1064 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1065 " nvic_icsr = 0x%" PRIx32
,
1066 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1071 static int cortex_m_assert_reset(struct target
*target
)
1073 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1074 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1075 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1077 LOG_DEBUG("target->state: %s",
1078 target_state_name(target
));
1080 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1082 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1083 /* allow scripts to override the reset event */
1085 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1086 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1087 target
->state
= TARGET_RESET
;
1092 /* some cores support connecting while srst is asserted
1093 * use that mode is it has been configured */
1095 bool srst_asserted
= false;
1097 if (!target_was_examined(target
)) {
1098 if (jtag_reset_config
& RESET_HAS_SRST
) {
1099 adapter_assert_reset();
1100 if (target
->reset_halt
)
1101 LOG_ERROR("Target not examined, will not halt after reset!");
1104 LOG_ERROR("Target not examined, reset NOT asserted!");
1109 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1110 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1111 adapter_assert_reset();
1112 srst_asserted
= true;
1115 /* Enable debug requests */
1117 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1118 /* Store important errors instead of failing and proceed to reset assert */
1120 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1121 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1123 /* If the processor is sleeping in a WFI or WFE instruction, the
1124 * C_HALT bit must be asserted to regain control */
1125 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1126 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1128 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1129 /* Ignore less important errors */
1131 if (!target
->reset_halt
) {
1132 /* Set/Clear C_MASKINTS in a separate operation */
1133 cortex_m_set_maskints_for_run(target
);
1135 /* clear any debug flags before resuming */
1136 cortex_m_clear_halt(target
);
1138 /* clear C_HALT in dhcsr reg */
1139 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1141 /* Halt in debug on reset; endreset_event() restores DEMCR.
1143 * REVISIT catching BUSERR presumably helps to defend against
1144 * bad vector table entries. Should this include MMERR or
1148 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1149 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1150 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1151 LOG_INFO("AP write error, reset will not halt");
1154 if (jtag_reset_config
& RESET_HAS_SRST
) {
1155 /* default to asserting srst */
1157 adapter_assert_reset();
1159 /* srst is asserted, ignore AP access errors */
1162 /* Use a standard Cortex-M3 software reset mechanism.
1163 * We default to using VECRESET as it is supported on all current cores
1164 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1165 * This has the disadvantage of not resetting the peripherals, so a
1166 * reset-init event handler is needed to perform any peripheral resets.
1168 if (!cortex_m
->vectreset_supported
1169 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1170 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1171 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1172 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1175 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1176 ? "SYSRESETREQ" : "VECTRESET");
1178 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1179 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1180 "handler to reset any peripherals or configure hardware srst support.");
1184 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1185 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1186 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1187 if (retval3
!= ERROR_OK
)
1188 LOG_DEBUG("Ignoring AP write error right after reset");
1190 retval3
= dap_dp_init(armv7m
->debug_ap
->dap
);
1191 if (retval3
!= ERROR_OK
)
1192 LOG_ERROR("DP initialisation failed");
1195 /* I do not know why this is necessary, but it
1196 * fixes strange effects (step/resume cause NMI
1197 * after reset) on LM3S6918 -- Michael Schwingen
1200 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1204 target
->state
= TARGET_RESET
;
1207 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1209 /* now return stored error code if any */
1210 if (retval
!= ERROR_OK
)
1213 if (target
->reset_halt
) {
1214 retval
= target_halt(target
);
1215 if (retval
!= ERROR_OK
)
1222 static int cortex_m_deassert_reset(struct target
*target
)
1224 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1226 LOG_DEBUG("target->state: %s",
1227 target_state_name(target
));
1229 /* deassert reset lines */
1230 adapter_deassert_reset();
1232 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1234 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1235 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1236 target_was_examined(target
)) {
1237 int retval
= dap_dp_init(armv7m
->debug_ap
->dap
);
1238 if (retval
!= ERROR_OK
) {
1239 LOG_ERROR("DP initialisation failed");
1247 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1251 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1252 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1254 if (breakpoint
->set
) {
1255 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1259 if (breakpoint
->type
== BKPT_HARD
) {
1260 uint32_t fpcr_value
;
1261 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1263 if (fp_num
>= cortex_m
->fp_num_code
) {
1264 LOG_ERROR("Can not find free FPB Comparator!");
1265 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1267 breakpoint
->set
= fp_num
+ 1;
1268 fpcr_value
= breakpoint
->address
| 1;
1269 if (cortex_m
->fp_rev
== 0) {
1270 if (breakpoint
->address
> 0x1FFFFFFF) {
1271 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1275 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1276 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1277 } else if (cortex_m
->fp_rev
> 1) {
1278 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1281 comparator_list
[fp_num
].used
= true;
1282 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1283 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1284 comparator_list
[fp_num
].fpcr_value
);
1285 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1287 comparator_list
[fp_num
].fpcr_value
);
1288 if (!cortex_m
->fpb_enabled
) {
1289 LOG_DEBUG("FPB wasn't enabled, do it now");
1290 retval
= cortex_m_enable_fpb(target
);
1291 if (retval
!= ERROR_OK
) {
1292 LOG_ERROR("Failed to enable the FPB");
1296 cortex_m
->fpb_enabled
= true;
1298 } else if (breakpoint
->type
== BKPT_SOFT
) {
1301 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1302 * semihosting; don't use that. Otherwise the BKPT
1303 * parameter is arbitrary.
1305 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1306 retval
= target_read_memory(target
,
1307 breakpoint
->address
& 0xFFFFFFFE,
1308 breakpoint
->length
, 1,
1309 breakpoint
->orig_instr
);
1310 if (retval
!= ERROR_OK
)
1312 retval
= target_write_memory(target
,
1313 breakpoint
->address
& 0xFFFFFFFE,
1314 breakpoint
->length
, 1,
1316 if (retval
!= ERROR_OK
)
1318 breakpoint
->set
= true;
1321 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1322 breakpoint
->unique_id
,
1323 (int)(breakpoint
->type
),
1324 breakpoint
->address
,
1331 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1334 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1335 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1337 if (!breakpoint
->set
) {
1338 LOG_WARNING("breakpoint not set");
1342 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1343 breakpoint
->unique_id
,
1344 (int)(breakpoint
->type
),
1345 breakpoint
->address
,
1349 if (breakpoint
->type
== BKPT_HARD
) {
1350 int fp_num
= breakpoint
->set
- 1;
1351 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1352 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1355 comparator_list
[fp_num
].used
= false;
1356 comparator_list
[fp_num
].fpcr_value
= 0;
1357 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1358 comparator_list
[fp_num
].fpcr_value
);
1360 /* restore original instruction (kept in target endianness) */
1361 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1362 breakpoint
->length
, 1,
1363 breakpoint
->orig_instr
);
1364 if (retval
!= ERROR_OK
)
1367 breakpoint
->set
= false;
1372 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1374 if (breakpoint
->length
== 3) {
1375 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1376 breakpoint
->length
= 2;
1379 if ((breakpoint
->length
!= 2)) {
1380 LOG_INFO("only breakpoints of two bytes length supported");
1381 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1384 return cortex_m_set_breakpoint(target
, breakpoint
);
1387 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1389 if (!breakpoint
->set
)
1392 return cortex_m_unset_breakpoint(target
, breakpoint
);
1395 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1398 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1400 /* REVISIT Don't fully trust these "not used" records ... users
1401 * may set up breakpoints by hand, e.g. dual-address data value
1402 * watchpoint using comparator #1; comparator #0 matching cycle
1403 * count; send data trace info through ITM and TPIU; etc
1405 struct cortex_m_dwt_comparator
*comparator
;
1407 for (comparator
= cortex_m
->dwt_comparator_list
;
1408 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1409 comparator
++, dwt_num
++)
1411 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1412 LOG_ERROR("Can not find free DWT Comparator");
1415 comparator
->used
= true;
1416 watchpoint
->set
= dwt_num
+ 1;
1418 comparator
->comp
= watchpoint
->address
;
1419 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1422 if ((cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M
) {
1423 uint32_t mask
= 0, temp
;
1425 /* watchpoint params were validated earlier */
1426 temp
= watchpoint
->length
;
1433 comparator
->mask
= mask
;
1434 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1437 switch (watchpoint
->rw
) {
1439 comparator
->function
= 5;
1442 comparator
->function
= 6;
1445 comparator
->function
= 7;
1449 uint32_t data_size
= watchpoint
->length
>> 1;
1450 comparator
->mask
= (watchpoint
->length
>> 1) | 1;
1452 switch (watchpoint
->rw
) {
1454 comparator
->function
= 4;
1457 comparator
->function
= 5;
1460 comparator
->function
= 6;
1463 comparator
->function
= comparator
->function
| (1 << 4) |
1467 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1468 comparator
->function
);
1470 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1471 watchpoint
->unique_id
, dwt_num
,
1472 (unsigned) comparator
->comp
,
1473 (unsigned) comparator
->mask
,
1474 (unsigned) comparator
->function
);
1478 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1480 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1481 struct cortex_m_dwt_comparator
*comparator
;
1484 if (!watchpoint
->set
) {
1485 LOG_WARNING("watchpoint (wpid: %d) not set",
1486 watchpoint
->unique_id
);
1490 dwt_num
= watchpoint
->set
- 1;
1492 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1493 watchpoint
->unique_id
, dwt_num
,
1494 (unsigned) watchpoint
->address
);
1496 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1497 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1501 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1502 comparator
->used
= false;
1503 comparator
->function
= 0;
1504 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1505 comparator
->function
);
1507 watchpoint
->set
= false;
1512 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1514 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1516 if (cortex_m
->dwt_comp_available
< 1) {
1517 LOG_DEBUG("no comparators?");
1518 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1521 /* hardware doesn't support data value masking */
1522 if (watchpoint
->mask
!= ~(uint32_t)0) {
1523 LOG_DEBUG("watchpoint value masks not supported");
1524 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1527 /* hardware allows address masks of up to 32K */
1530 for (mask
= 0; mask
< 16; mask
++) {
1531 if ((1u << mask
) == watchpoint
->length
)
1535 LOG_DEBUG("unsupported watchpoint length");
1536 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1538 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1539 LOG_DEBUG("watchpoint address is unaligned");
1540 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1543 /* Caller doesn't seem to be able to describe watching for data
1544 * values of zero; that flags "no value".
1546 * REVISIT This DWT may well be able to watch for specific data
1547 * values. Requires comparator #1 to set DATAVMATCH and match
1548 * the data, and another comparator (DATAVADDR0) matching addr.
1550 if (watchpoint
->value
) {
1551 LOG_DEBUG("data value watchpoint not YET supported");
1552 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1555 cortex_m
->dwt_comp_available
--;
1556 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1561 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1563 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1565 /* REVISIT why check? DWT can be updated with core running ... */
1566 if (target
->state
!= TARGET_HALTED
) {
1567 LOG_WARNING("target not halted");
1568 return ERROR_TARGET_NOT_HALTED
;
1571 if (watchpoint
->set
)
1572 cortex_m_unset_watchpoint(target
, watchpoint
);
1574 cortex_m
->dwt_comp_available
++;
1575 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1580 void cortex_m_enable_watchpoints(struct target
*target
)
1582 struct watchpoint
*watchpoint
= target
->watchpoints
;
1584 /* set any pending watchpoints */
1585 while (watchpoint
) {
1586 if (!watchpoint
->set
)
1587 cortex_m_set_watchpoint(target
, watchpoint
);
1588 watchpoint
= watchpoint
->next
;
1592 static int cortex_m_load_core_reg_u32(struct target
*target
,
1593 uint32_t num
, uint32_t *value
)
1597 /* NOTE: we "know" here that the register identifiers used
1598 * in the v7m header match the Cortex-M3 Debug Core Register
1599 * Selector values for R0..R15, xPSR, MSP, and PSP.
1603 /* read a normal core register */
1604 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1606 if (retval
!= ERROR_OK
) {
1607 LOG_ERROR("JTAG failure %i", retval
);
1608 return ERROR_JTAG_DEVICE_ERROR
;
1610 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1614 /* Floating-point Status and Registers */
1615 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1616 if (retval
!= ERROR_OK
)
1618 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1619 if (retval
!= ERROR_OK
)
1621 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1624 case ARMV7M_S0
... ARMV7M_S31
:
1625 /* Floating-point Status and Registers */
1626 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1627 if (retval
!= ERROR_OK
)
1629 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1630 if (retval
!= ERROR_OK
)
1632 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1633 (int)(num
- ARMV7M_S0
), *value
);
1636 case ARMV7M_PRIMASK
:
1637 case ARMV7M_BASEPRI
:
1638 case ARMV7M_FAULTMASK
:
1639 case ARMV7M_CONTROL
:
1640 /* Cortex-M3 packages these four registers as bitfields
1641 * in one Debug Core register. So say r0 and r2 docs;
1642 * it was removed from r1 docs, but still works.
1644 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1647 case ARMV7M_PRIMASK
:
1648 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1651 case ARMV7M_BASEPRI
:
1652 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1655 case ARMV7M_FAULTMASK
:
1656 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1659 case ARMV7M_CONTROL
:
1660 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1664 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1668 return ERROR_COMMAND_SYNTAX_ERROR
;
1674 static int cortex_m_store_core_reg_u32(struct target
*target
,
1675 uint32_t num
, uint32_t value
)
1679 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1681 /* NOTE: we "know" here that the register identifiers used
1682 * in the v7m header match the Cortex-M3 Debug Core Register
1683 * Selector values for R0..R15, xPSR, MSP, and PSP.
1687 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1688 if (retval
!= ERROR_OK
) {
1691 LOG_ERROR("JTAG failure");
1692 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1693 r
->dirty
= r
->valid
;
1694 return ERROR_JTAG_DEVICE_ERROR
;
1696 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1700 /* Floating-point Status and Registers */
1701 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1702 if (retval
!= ERROR_OK
)
1704 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1705 if (retval
!= ERROR_OK
)
1707 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1710 case ARMV7M_S0
... ARMV7M_S31
:
1711 /* Floating-point Status and Registers */
1712 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1713 if (retval
!= ERROR_OK
)
1715 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1716 if (retval
!= ERROR_OK
)
1718 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1719 (int)(num
- ARMV7M_S0
), value
);
1722 case ARMV7M_PRIMASK
:
1723 case ARMV7M_BASEPRI
:
1724 case ARMV7M_FAULTMASK
:
1725 case ARMV7M_CONTROL
:
1726 /* Cortex-M3 packages these four registers as bitfields
1727 * in one Debug Core register. So say r0 and r2 docs;
1728 * it was removed from r1 docs, but still works.
1730 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1733 case ARMV7M_PRIMASK
:
1734 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1737 case ARMV7M_BASEPRI
:
1738 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1741 case ARMV7M_FAULTMASK
:
1742 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1745 case ARMV7M_CONTROL
:
1746 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1750 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1752 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1756 return ERROR_COMMAND_SYNTAX_ERROR
;
1762 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
1763 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1765 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1767 if (armv7m
->arm
.is_armv6m
) {
1768 /* armv6m does not handle unaligned memory access */
1769 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1770 return ERROR_TARGET_UNALIGNED_ACCESS
;
1773 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1776 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
1777 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1779 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1781 if (armv7m
->arm
.is_armv6m
) {
1782 /* armv6m does not handle unaligned memory access */
1783 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1784 return ERROR_TARGET_UNALIGNED_ACCESS
;
1787 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1790 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1791 struct target
*target
)
1793 armv7m_build_reg_cache(target
);
1794 arm_semihosting_init(target
);
1798 void cortex_m_deinit_target(struct target
*target
)
1800 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1802 free(cortex_m
->fp_comparator_list
);
1804 cortex_m_dwt_free(target
);
1805 armv7m_free_reg_cache(target
);
1807 free(target
->private_config
);
1811 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
1812 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
1814 struct timeval timeout
, now
;
1815 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1817 bool use_pcsr
= false;
1818 int retval
= ERROR_OK
;
1821 gettimeofday(&timeout
, NULL
);
1822 timeval_add_time(&timeout
, seconds
, 0);
1824 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
1825 if (retval
!= ERROR_OK
) {
1826 LOG_ERROR("Error while reading PCSR");
1830 if (reg_value
!= 0) {
1832 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1834 LOG_INFO("Starting profiling. Halting and resuming the"
1835 " target as often as we can...");
1836 reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
1839 /* Make sure the target is running */
1840 target_poll(target
);
1841 if (target
->state
== TARGET_HALTED
)
1842 retval
= target_resume(target
, 1, 0, 0, 0);
1844 if (retval
!= ERROR_OK
) {
1845 LOG_ERROR("Error while resuming target");
1849 uint32_t sample_count
= 0;
1853 if (armv7m
&& armv7m
->debug_ap
) {
1854 uint32_t read_count
= max_num_samples
- sample_count
;
1855 if (read_count
> 1024)
1858 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
1859 (void *)&samples
[sample_count
],
1860 4, read_count
, DWT_PCSR
);
1861 sample_count
+= read_count
;
1863 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
1866 target_poll(target
);
1867 if (target
->state
== TARGET_HALTED
) {
1868 reg_value
= buf_get_u32(reg
->value
, 0, 32);
1869 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1870 retval
= target_resume(target
, 1, 0, 0, 0);
1871 samples
[sample_count
++] = reg_value
;
1872 target_poll(target
);
1873 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1874 } else if (target
->state
== TARGET_RUNNING
) {
1875 /* We want to quickly sample the PC. */
1876 retval
= target_halt(target
);
1878 LOG_INFO("Target not halted or running");
1884 if (retval
!= ERROR_OK
) {
1885 LOG_ERROR("Error while reading %s", use_pcsr
? "PCSR" : "target pc");
1890 gettimeofday(&now
, NULL
);
1891 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
1892 LOG_INFO("Profiling completed. %" PRIu32
" samples.", sample_count
);
1897 *num_samples
= sample_count
;
1902 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1903 * on r/w if the core is not running, and clear on resume or reset ... or
1904 * at least, in a post_restore_context() method.
1907 struct dwt_reg_state
{
1908 struct target
*target
;
1910 uint8_t value
[4]; /* scratch/cache */
1913 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1915 struct dwt_reg_state
*state
= reg
->arch_info
;
1918 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1919 if (retval
!= ERROR_OK
)
1922 buf_set_u32(state
->value
, 0, 32, tmp
);
1926 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1928 struct dwt_reg_state
*state
= reg
->arch_info
;
1930 return target_write_u32(state
->target
, state
->addr
,
1931 buf_get_u32(buf
, 0, reg
->size
));
1940 static const struct dwt_reg dwt_base_regs
[] = {
1941 { DWT_CTRL
, "dwt_ctrl", 32, },
1942 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1943 * increments while the core is asleep.
1945 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1946 /* plus some 8 bit counters, useful for profiling with TPIU */
1949 static const struct dwt_reg dwt_comp
[] = {
1950 #define DWT_COMPARATOR(i) \
1951 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1952 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1953 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1970 #undef DWT_COMPARATOR
1973 static const struct reg_arch_type dwt_reg_type
= {
1974 .get
= cortex_m_dwt_get_reg
,
1975 .set
= cortex_m_dwt_set_reg
,
1978 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
1980 struct dwt_reg_state
*state
;
1982 state
= calloc(1, sizeof(*state
));
1985 state
->addr
= d
->addr
;
1990 r
->value
= state
->value
;
1991 r
->arch_info
= state
;
1992 r
->type
= &dwt_reg_type
;
1995 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1998 struct reg_cache
*cache
;
1999 struct cortex_m_dwt_comparator
*comparator
;
2002 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
2003 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32
, dwtcr
);
2005 LOG_DEBUG("no DWT");
2009 target_read_u32(target
, DWT_DEVARCH
, &cm
->dwt_devarch
);
2010 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32
, cm
->dwt_devarch
);
2012 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
2013 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
2014 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
2015 sizeof(struct cortex_m_dwt_comparator
));
2016 if (!cm
->dwt_comparator_list
) {
2018 cm
->dwt_num_comp
= 0;
2019 LOG_ERROR("out of mem");
2023 cache
= calloc(1, sizeof(*cache
));
2026 free(cm
->dwt_comparator_list
);
2029 cache
->name
= "Cortex-M DWT registers";
2030 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
2031 cache
->reg_list
= calloc(cache
->num_regs
, sizeof(*cache
->reg_list
));
2032 if (!cache
->reg_list
) {
2037 for (reg
= 0; reg
< 2; reg
++)
2038 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2039 dwt_base_regs
+ reg
);
2041 comparator
= cm
->dwt_comparator_list
;
2042 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
2045 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
2046 for (j
= 0; j
< 3; j
++, reg
++)
2047 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2048 dwt_comp
+ 3 * i
+ j
);
2050 /* make sure we clear any watchpoints enabled on the target */
2051 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
2054 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
2055 cm
->dwt_cache
= cache
;
2057 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
2058 dwtcr
, cm
->dwt_num_comp
,
2059 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
2061 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2062 * implement single-address data value watchpoints ... so we
2063 * won't need to check it later, when asked to set one up.
2067 static void cortex_m_dwt_free(struct target
*target
)
2069 struct cortex_m_common
*cm
= target_to_cm(target
);
2070 struct reg_cache
*cache
= cm
->dwt_cache
;
2072 free(cm
->dwt_comparator_list
);
2073 cm
->dwt_comparator_list
= NULL
;
2074 cm
->dwt_num_comp
= 0;
2077 register_unlink_cache(&target
->reg_cache
, cache
);
2079 if (cache
->reg_list
) {
2080 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
2081 free(cache
->reg_list
[i
].arch_info
);
2082 free(cache
->reg_list
);
2086 cm
->dwt_cache
= NULL
;
2089 #define MVFR0 0xe000ef40
2090 #define MVFR1 0xe000ef44
2092 #define MVFR0_DEFAULT_M4 0x10110021
2093 #define MVFR1_DEFAULT_M4 0x11000011
2095 #define MVFR0_DEFAULT_M7_SP 0x10110021
2096 #define MVFR0_DEFAULT_M7_DP 0x10110221
2097 #define MVFR1_DEFAULT_M7_SP 0x11000011
2098 #define MVFR1_DEFAULT_M7_DP 0x12000011
2100 static int cortex_m_find_mem_ap(struct adiv5_dap
*swjdp
,
2101 struct adiv5_ap
**debug_ap
)
2103 if (dap_find_ap(swjdp
, AP_TYPE_AHB3_AP
, debug_ap
) == ERROR_OK
)
2106 return dap_find_ap(swjdp
, AP_TYPE_AHB5_AP
, debug_ap
);
2109 int cortex_m_examine(struct target
*target
)
2112 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
2114 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2115 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
2116 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2118 /* stlink shares the examine handler but does not support
2120 if (!armv7m
->stlink
) {
2121 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
2122 /* Search for the MEM-AP */
2123 retval
= cortex_m_find_mem_ap(swjdp
, &armv7m
->debug_ap
);
2124 if (retval
!= ERROR_OK
) {
2125 LOG_ERROR("Could not find MEM-AP to control the core");
2129 armv7m
->debug_ap
= dap_ap(swjdp
, cortex_m
->apsel
);
2132 /* Leave (only) generic DAP stuff for debugport_init(); */
2133 armv7m
->debug_ap
->memaccess_tck
= 8;
2135 retval
= mem_ap_init(armv7m
->debug_ap
);
2136 if (retval
!= ERROR_OK
)
2140 if (!target_was_examined(target
)) {
2141 target_set_examined(target
);
2143 /* Read from Device Identification Registers */
2144 retval
= target_read_u32(target
, CPUID
, &cpuid
);
2145 if (retval
!= ERROR_OK
)
2149 i
= (cpuid
>> 4) & 0xf;
2151 switch (cpuid
& ARM_CPUID_PARTNO_MASK
) {
2152 case CORTEX_M23_PARTNO
:
2156 case CORTEX_M33_PARTNO
:
2165 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
2166 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
2167 cortex_m
->maskints_erratum
= false;
2170 rev
= (cpuid
>> 20) & 0xf;
2171 patch
= (cpuid
>> 0) & 0xf;
2172 if ((rev
== 0) && (patch
< 2)) {
2173 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2174 cortex_m
->maskints_erratum
= true;
2177 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
2179 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2180 cortex_m
->vectreset_supported
= i
> 1;
2183 target_read_u32(target
, MVFR0
, &mvfr0
);
2184 target_read_u32(target
, MVFR1
, &mvfr1
);
2186 /* test for floating point feature on Cortex-M4 */
2187 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2188 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
2189 armv7m
->fp_feature
= FPv4_SP
;
2191 } else if (i
== 7 || i
== 33) {
2192 target_read_u32(target
, MVFR0
, &mvfr0
);
2193 target_read_u32(target
, MVFR1
, &mvfr1
);
2195 /* test for floating point features on Cortex-M7 */
2196 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2197 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
2198 armv7m
->fp_feature
= FPv5_SP
;
2199 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2200 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
2201 armv7m
->fp_feature
= FPv5_DP
;
2203 } else if (i
== 0) {
2204 /* Cortex-M0 does not support unaligned memory access */
2205 armv7m
->arm
.is_armv6m
= true;
2208 if (armv7m
->fp_feature
== FP_NONE
&&
2209 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
2210 /* free unavailable FPU registers */
2213 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
2214 idx
< armv7m
->arm
.core_cache
->num_regs
;
2216 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
2217 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
2218 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
2220 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
2223 if (!armv7m
->stlink
) {
2224 if (i
== 3 || i
== 4)
2225 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2226 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2227 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2229 /* Cortex-M7 has only 1024 bytes autoincrement range */
2230 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
2233 /* Enable debug requests */
2234 retval
= target_read_u32(target
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
2235 if (retval
!= ERROR_OK
)
2237 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
2238 uint32_t dhcsr
= (cortex_m
->dcb_dhcsr
| C_DEBUGEN
) & ~(C_HALT
| C_STEP
| C_MASKINTS
);
2240 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| (dhcsr
& 0x0000FFFFUL
));
2241 if (retval
!= ERROR_OK
)
2243 cortex_m
->dcb_dhcsr
= dhcsr
;
2246 /* Configure trace modules */
2247 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2248 if (retval
!= ERROR_OK
)
2251 if (armv7m
->trace_config
.config_type
!= TRACE_CONFIG_TYPE_DISABLED
) {
2252 armv7m_trace_tpiu_config(target
);
2253 armv7m_trace_itm_config(target
);
2256 /* NOTE: FPB and DWT are both optional. */
2259 target_read_u32(target
, FP_CTRL
, &fpcr
);
2260 /* bits [14:12] and [7:4] */
2261 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2262 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2263 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2264 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2265 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2266 free(cortex_m
->fp_comparator_list
);
2267 cortex_m
->fp_comparator_list
= calloc(
2268 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2269 sizeof(struct cortex_m_fp_comparator
));
2270 cortex_m
->fpb_enabled
= fpcr
& 1;
2271 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2272 cortex_m
->fp_comparator_list
[i
].type
=
2273 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2274 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2276 /* make sure we clear any breakpoints enabled on the target */
2277 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2279 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2281 cortex_m
->fp_num_code
,
2282 cortex_m
->fp_num_lit
);
2285 cortex_m_dwt_free(target
);
2286 cortex_m_dwt_setup(cortex_m
, target
);
2288 /* These hardware breakpoints only work for code in flash! */
2289 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2290 target_name(target
),
2291 cortex_m
->fp_num_code
,
2292 cortex_m
->dwt_num_comp
);
2298 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2300 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2305 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2306 if (retval
!= ERROR_OK
)
2309 dcrdr
= target_buffer_get_u16(target
, buf
);
2310 *ctrl
= (uint8_t)dcrdr
;
2311 *value
= (uint8_t)(dcrdr
>> 8);
2313 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2315 /* write ack back to software dcc register
2316 * signify we have read data */
2317 if (dcrdr
& (1 << 0)) {
2318 target_buffer_set_u16(target
, buf
, 0);
2319 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2320 if (retval
!= ERROR_OK
)
2327 static int cortex_m_target_request_data(struct target
*target
,
2328 uint32_t size
, uint8_t *buffer
)
2334 for (i
= 0; i
< (size
* 4); i
++) {
2335 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2336 if (retval
!= ERROR_OK
)
2344 static int cortex_m_handle_target_request(void *priv
)
2346 struct target
*target
= priv
;
2347 if (!target_was_examined(target
))
2350 if (!target
->dbg_msg_enabled
)
2353 if (target
->state
== TARGET_RUNNING
) {
2358 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2359 if (retval
!= ERROR_OK
)
2362 /* check if we have data */
2363 if (ctrl
& (1 << 0)) {
2366 /* we assume target is quick enough */
2368 for (int i
= 1; i
<= 3; i
++) {
2369 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2370 if (retval
!= ERROR_OK
)
2372 request
|= ((uint32_t)data
<< (i
* 8));
2374 target_request(target
, request
);
2381 static int cortex_m_init_arch_info(struct target
*target
,
2382 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2384 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2386 armv7m_init_arch_info(target
, armv7m
);
2388 /* default reset mode is to use srst if fitted
2389 * if not it will use CORTEX_M3_RESET_VECTRESET */
2390 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2392 armv7m
->arm
.dap
= dap
;
2394 /* register arch-specific functions */
2395 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2397 armv7m
->post_debug_entry
= NULL
;
2399 armv7m
->pre_restore_context
= NULL
;
2401 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2402 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2404 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2405 TARGET_TIMER_TYPE_PERIODIC
, target
);
2410 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2412 struct adiv5_private_config
*pc
;
2414 pc
= (struct adiv5_private_config
*)target
->private_config
;
2415 if (adiv5_verify_config(pc
) != ERROR_OK
)
2418 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2419 if (cortex_m
== NULL
) {
2420 LOG_ERROR("No memory creating target");
2424 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2425 cortex_m
->apsel
= pc
->ap_num
;
2427 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2432 /*--------------------------------------------------------------------------*/
2434 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2435 struct cortex_m_common
*cm
)
2437 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2438 command_print(cmd
, "target is not a Cortex-M");
2439 return ERROR_TARGET_INVALID
;
2445 * Only stuff below this line should need to verify that its target
2446 * is a Cortex-M3. Everything else should have indirected through the
2447 * cortexm3_target structure, which is only used with CM3 targets.
2450 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2452 struct target
*target
= get_current_target(CMD_CTX
);
2453 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2454 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2458 static const struct {
2462 { "hard_err", VC_HARDERR
, },
2463 { "int_err", VC_INTERR
, },
2464 { "bus_err", VC_BUSERR
, },
2465 { "state_err", VC_STATERR
, },
2466 { "chk_err", VC_CHKERR
, },
2467 { "nocp_err", VC_NOCPERR
, },
2468 { "mm_err", VC_MMERR
, },
2469 { "reset", VC_CORERESET
, },
2472 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2473 if (retval
!= ERROR_OK
)
2476 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2477 if (retval
!= ERROR_OK
)
2483 if (CMD_ARGC
== 1) {
2484 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2485 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2486 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2487 | VC_MMERR
| VC_CORERESET
;
2489 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2492 while (CMD_ARGC
-- > 0) {
2494 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2495 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2497 catch |= vec_ids
[i
].mask
;
2500 if (i
== ARRAY_SIZE(vec_ids
)) {
2501 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2502 return ERROR_COMMAND_SYNTAX_ERROR
;
2506 /* For now, armv7m->demcr only stores vector catch flags. */
2507 armv7m
->demcr
= catch;
2512 /* write, but don't assume it stuck (why not??) */
2513 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2514 if (retval
!= ERROR_OK
)
2516 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2517 if (retval
!= ERROR_OK
)
2520 /* FIXME be sure to clear DEMCR on clean server shutdown.
2521 * Otherwise the vector catch hardware could fire when there's
2522 * no debugger hooked up, causing much confusion...
2526 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2527 command_print(CMD
, "%9s: %s", vec_ids
[i
].name
,
2528 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2534 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2536 struct target
*target
= get_current_target(CMD_CTX
);
2537 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2540 static const Jim_Nvp nvp_maskisr_modes
[] = {
2541 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2542 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2543 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2544 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2545 { .name
= NULL
, .value
= -1 },
2550 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2551 if (retval
!= ERROR_OK
)
2554 if (target
->state
!= TARGET_HALTED
) {
2555 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
2560 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2561 if (n
->name
== NULL
)
2562 return ERROR_COMMAND_SYNTAX_ERROR
;
2563 cortex_m
->isrmasking_mode
= n
->value
;
2564 cortex_m_set_maskints_for_halt(target
);
2567 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2568 command_print(CMD
, "cortex_m interrupt mask %s", n
->name
);
2573 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2575 struct target
*target
= get_current_target(CMD_CTX
);
2576 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2580 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2581 if (retval
!= ERROR_OK
)
2585 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2586 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2588 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2589 if (target_was_examined(target
)
2590 && !cortex_m
->vectreset_supported
)
2591 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2593 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2596 return ERROR_COMMAND_SYNTAX_ERROR
;
2599 switch (cortex_m
->soft_reset_config
) {
2600 case CORTEX_M_RESET_SYSRESETREQ
:
2601 reset_config
= "sysresetreq";
2604 case CORTEX_M_RESET_VECTRESET
:
2605 reset_config
= "vectreset";
2609 reset_config
= "unknown";
2613 command_print(CMD
, "cortex_m reset_config %s", reset_config
);
2618 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2621 .handler
= handle_cortex_m_mask_interrupts_command
,
2622 .mode
= COMMAND_EXEC
,
2623 .help
= "mask cortex_m interrupts",
2624 .usage
= "['auto'|'on'|'off'|'steponly']",
2627 .name
= "vector_catch",
2628 .handler
= handle_cortex_m_vector_catch_command
,
2629 .mode
= COMMAND_EXEC
,
2630 .help
= "configure hardware vectors to trigger debug entry",
2631 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2634 .name
= "reset_config",
2635 .handler
= handle_cortex_m_reset_config_command
,
2636 .mode
= COMMAND_ANY
,
2637 .help
= "configure software reset handling",
2638 .usage
= "['sysresetreq'|'vectreset']",
2640 COMMAND_REGISTRATION_DONE
2642 static const struct command_registration cortex_m_command_handlers
[] = {
2644 .chain
= armv7m_command_handlers
,
2647 .chain
= armv7m_trace_command_handlers
,
2651 .mode
= COMMAND_EXEC
,
2652 .help
= "Cortex-M command group",
2654 .chain
= cortex_m_exec_command_handlers
,
2656 COMMAND_REGISTRATION_DONE
2659 struct target_type cortexm_target
= {
2661 .deprecated_name
= "cortex_m3",
2663 .poll
= cortex_m_poll
,
2664 .arch_state
= armv7m_arch_state
,
2666 .target_request_data
= cortex_m_target_request_data
,
2668 .halt
= cortex_m_halt
,
2669 .resume
= cortex_m_resume
,
2670 .step
= cortex_m_step
,
2672 .assert_reset
= cortex_m_assert_reset
,
2673 .deassert_reset
= cortex_m_deassert_reset
,
2674 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2676 .get_gdb_arch
= arm_get_gdb_arch
,
2677 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2679 .read_memory
= cortex_m_read_memory
,
2680 .write_memory
= cortex_m_write_memory
,
2681 .checksum_memory
= armv7m_checksum_memory
,
2682 .blank_check_memory
= armv7m_blank_check_memory
,
2684 .run_algorithm
= armv7m_run_algorithm
,
2685 .start_algorithm
= armv7m_start_algorithm
,
2686 .wait_algorithm
= armv7m_wait_algorithm
,
2688 .add_breakpoint
= cortex_m_add_breakpoint
,
2689 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2690 .add_watchpoint
= cortex_m_add_watchpoint
,
2691 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2693 .commands
= cortex_m_command_handlers
,
2694 .target_create
= cortex_m_target_create
,
2695 .target_jim_configure
= adiv5_jim_configure
,
2696 .init_target
= cortex_m_init_target
,
2697 .examine
= cortex_m_examine
,
2698 .deinit_target
= cortex_m_deinit_target
,
2700 .profiling
= cortex_m_profiling
,
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