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cortex_m: add armv8m special registers
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42 #include <rtt/rtt.h>
43
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FPB remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
49 *
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
52 * any longer.
53 */
54
55 /* forward declarations */
56 static int cortex_m_store_core_reg_u32(struct target *target,
57 uint32_t num, uint32_t value);
58 static void cortex_m_dwt_free(struct target *target);
59
60 static int cortex_m_load_core_reg_u32(struct target *target,
61 uint32_t regsel, uint32_t *value)
62 {
63 struct armv7m_common *armv7m = target_to_armv7m(target);
64 int retval;
65 uint32_t dcrdr;
66
67 /* because the DCB_DCRDR is used for the emulated dcc channel
68 * we have to save/restore the DCB_DCRDR when used */
69 if (target->dbg_msg_enabled) {
70 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
71 if (retval != ERROR_OK)
72 return retval;
73 }
74
75 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
76 if (retval != ERROR_OK)
77 return retval;
78
79 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
80 if (retval != ERROR_OK)
81 return retval;
82
83 if (target->dbg_msg_enabled) {
84 /* restore DCB_DCRDR - this needs to be in a separate
85 * transaction otherwise the emulated DCC channel breaks */
86 if (retval == ERROR_OK)
87 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
88 }
89
90 return retval;
91 }
92
93 static int cortex_m_store_core_reg_u32(struct target *target,
94 uint32_t regsel, uint32_t value)
95 {
96 struct armv7m_common *armv7m = target_to_armv7m(target);
97 int retval;
98 uint32_t dcrdr;
99
100 /* because the DCB_DCRDR is used for the emulated dcc channel
101 * we have to save/restore the DCB_DCRDR when used */
102 if (target->dbg_msg_enabled) {
103 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
104 if (retval != ERROR_OK)
105 return retval;
106 }
107
108 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
109 if (retval != ERROR_OK)
110 return retval;
111
112 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR);
113 if (retval != ERROR_OK)
114 return retval;
115
116 if (target->dbg_msg_enabled) {
117 /* restore DCB_DCRDR - this needs to be in a separate
118 * transaction otherwise the emulated DCC channel breaks */
119 if (retval == ERROR_OK)
120 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
121 }
122
123 return retval;
124 }
125
126 static int cortex_m_write_debug_halt_mask(struct target *target,
127 uint32_t mask_on, uint32_t mask_off)
128 {
129 struct cortex_m_common *cortex_m = target_to_cm(target);
130 struct armv7m_common *armv7m = &cortex_m->armv7m;
131
132 /* mask off status bits */
133 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
134 /* create new register mask */
135 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
136
137 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
138 }
139
140 static int cortex_m_set_maskints(struct target *target, bool mask)
141 {
142 struct cortex_m_common *cortex_m = target_to_cm(target);
143 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
144 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
145 else
146 return ERROR_OK;
147 }
148
149 static int cortex_m_set_maskints_for_halt(struct target *target)
150 {
151 struct cortex_m_common *cortex_m = target_to_cm(target);
152 switch (cortex_m->isrmasking_mode) {
153 case CORTEX_M_ISRMASK_AUTO:
154 /* interrupts taken at resume, whether for step or run -> no mask */
155 return cortex_m_set_maskints(target, false);
156
157 case CORTEX_M_ISRMASK_OFF:
158 /* interrupts never masked */
159 return cortex_m_set_maskints(target, false);
160
161 case CORTEX_M_ISRMASK_ON:
162 /* interrupts always masked */
163 return cortex_m_set_maskints(target, true);
164
165 case CORTEX_M_ISRMASK_STEPONLY:
166 /* interrupts masked for single step only -> mask now if MASKINTS
167 * erratum, otherwise only mask before stepping */
168 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
169 }
170 return ERROR_OK;
171 }
172
173 static int cortex_m_set_maskints_for_run(struct target *target)
174 {
175 switch (target_to_cm(target)->isrmasking_mode) {
176 case CORTEX_M_ISRMASK_AUTO:
177 /* interrupts taken at resume, whether for step or run -> no mask */
178 return cortex_m_set_maskints(target, false);
179
180 case CORTEX_M_ISRMASK_OFF:
181 /* interrupts never masked */
182 return cortex_m_set_maskints(target, false);
183
184 case CORTEX_M_ISRMASK_ON:
185 /* interrupts always masked */
186 return cortex_m_set_maskints(target, true);
187
188 case CORTEX_M_ISRMASK_STEPONLY:
189 /* interrupts masked for single step only -> no mask */
190 return cortex_m_set_maskints(target, false);
191 }
192 return ERROR_OK;
193 }
194
195 static int cortex_m_set_maskints_for_step(struct target *target)
196 {
197 switch (target_to_cm(target)->isrmasking_mode) {
198 case CORTEX_M_ISRMASK_AUTO:
199 /* the auto-interrupt should already be done -> mask */
200 return cortex_m_set_maskints(target, true);
201
202 case CORTEX_M_ISRMASK_OFF:
203 /* interrupts never masked */
204 return cortex_m_set_maskints(target, false);
205
206 case CORTEX_M_ISRMASK_ON:
207 /* interrupts always masked */
208 return cortex_m_set_maskints(target, true);
209
210 case CORTEX_M_ISRMASK_STEPONLY:
211 /* interrupts masked for single step only -> mask */
212 return cortex_m_set_maskints(target, true);
213 }
214 return ERROR_OK;
215 }
216
217 static int cortex_m_clear_halt(struct target *target)
218 {
219 struct cortex_m_common *cortex_m = target_to_cm(target);
220 struct armv7m_common *armv7m = &cortex_m->armv7m;
221 int retval;
222
223 /* clear step if any */
224 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
225
226 /* Read Debug Fault Status Register */
227 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
228 if (retval != ERROR_OK)
229 return retval;
230
231 /* Clear Debug Fault Status */
232 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
233 if (retval != ERROR_OK)
234 return retval;
235 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
236
237 return ERROR_OK;
238 }
239
240 static int cortex_m_single_step_core(struct target *target)
241 {
242 struct cortex_m_common *cortex_m = target_to_cm(target);
243 struct armv7m_common *armv7m = &cortex_m->armv7m;
244 int retval;
245
246 /* Mask interrupts before clearing halt, if not done already. This avoids
247 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
248 * HALT can put the core into an unknown state.
249 */
250 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
251 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
252 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
253 if (retval != ERROR_OK)
254 return retval;
255 }
256 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
257 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
258 if (retval != ERROR_OK)
259 return retval;
260 LOG_DEBUG(" ");
261
262 /* restore dhcsr reg */
263 cortex_m_clear_halt(target);
264
265 return ERROR_OK;
266 }
267
268 static int cortex_m_enable_fpb(struct target *target)
269 {
270 int retval = target_write_u32(target, FP_CTRL, 3);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* check the fpb is actually enabled */
275 uint32_t fpctrl;
276 retval = target_read_u32(target, FP_CTRL, &fpctrl);
277 if (retval != ERROR_OK)
278 return retval;
279
280 if (fpctrl & 1)
281 return ERROR_OK;
282
283 return ERROR_FAIL;
284 }
285
286 static int cortex_m_endreset_event(struct target *target)
287 {
288 int retval;
289 uint32_t dcb_demcr;
290 struct cortex_m_common *cortex_m = target_to_cm(target);
291 struct armv7m_common *armv7m = &cortex_m->armv7m;
292 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
293 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
294 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
295
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
298 if (retval != ERROR_OK)
299 return retval;
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
301
302 /* this register is used for emulated dcc channel */
303 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* Enable debug requests */
308 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
309 if (retval != ERROR_OK)
310 return retval;
311 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
312 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
313 if (retval != ERROR_OK)
314 return retval;
315 }
316
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target);
319
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
322 *
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
326 */
327 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
328 if (retval != ERROR_OK)
329 return retval;
330
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
333 */
334
335 /* Enable FPB */
336 retval = cortex_m_enable_fpb(target);
337 if (retval != ERROR_OK) {
338 LOG_ERROR("Failed to enable the FPB");
339 return retval;
340 }
341
342 cortex_m->fpb_enabled = true;
343
344 /* Restore FPB registers */
345 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
346 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350
351 /* Restore DWT registers */
352 for (unsigned int i = 0; i < cortex_m->dwt_num_comp; i++) {
353 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
354 dwt_list[i].comp);
355 if (retval != ERROR_OK)
356 return retval;
357 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
358 dwt_list[i].mask);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
362 dwt_list[i].function);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366 retval = dap_run(swjdp);
367 if (retval != ERROR_OK)
368 return retval;
369
370 register_cache_invalidate(armv7m->arm.core_cache);
371
372 /* make sure we have latest dhcsr flags */
373 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
374
375 return retval;
376 }
377
378 static int cortex_m_examine_debug_reason(struct target *target)
379 {
380 struct cortex_m_common *cortex_m = target_to_cm(target);
381
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
384
385 if ((target->debug_reason != DBG_REASON_DBGRQ)
386 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
387 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
388 target->debug_reason = DBG_REASON_BREAKPOINT;
389 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
390 target->debug_reason = DBG_REASON_WPTANDBKPT;
391 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
392 target->debug_reason = DBG_REASON_WATCHPOINT;
393 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
394 target->debug_reason = DBG_REASON_BREAKPOINT;
395 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
396 target->debug_reason = DBG_REASON_DBGRQ;
397 else /* HALTED */
398 target->debug_reason = DBG_REASON_UNDEFINED;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int cortex_m_examine_exception_reason(struct target *target)
405 {
406 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
407 struct armv7m_common *armv7m = target_to_armv7m(target);
408 struct adiv5_dap *swjdp = armv7m->arm.dap;
409 int retval;
410
411 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
412 if (retval != ERROR_OK)
413 return retval;
414 switch (armv7m->exception_number) {
415 case 2: /* NMI */
416 break;
417 case 3: /* Hard Fault */
418 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
419 if (retval != ERROR_OK)
420 return retval;
421 if (except_sr & 0x40000000) {
422 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
423 if (retval != ERROR_OK)
424 return retval;
425 }
426 break;
427 case 4: /* Memory Management */
428 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
432 if (retval != ERROR_OK)
433 return retval;
434 break;
435 case 5: /* Bus Fault */
436 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
440 if (retval != ERROR_OK)
441 return retval;
442 break;
443 case 6: /* Usage Fault */
444 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
445 if (retval != ERROR_OK)
446 return retval;
447 break;
448 case 7: /* Secure Fault */
449 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
453 if (retval != ERROR_OK)
454 return retval;
455 break;
456 case 11: /* SVCall */
457 break;
458 case 12: /* Debug Monitor */
459 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
460 if (retval != ERROR_OK)
461 return retval;
462 break;
463 case 14: /* PendSV */
464 break;
465 case 15: /* SysTick */
466 break;
467 default:
468 except_sr = 0;
469 break;
470 }
471 retval = dap_run(swjdp);
472 if (retval == ERROR_OK)
473 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
474 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
475 armv7m_exception_string(armv7m->exception_number),
476 shcsr, except_sr, cfsr, except_ar);
477 return retval;
478 }
479
480 static int cortex_m_debug_entry(struct target *target)
481 {
482 int i;
483 uint32_t xPSR;
484 int retval;
485 struct cortex_m_common *cortex_m = target_to_cm(target);
486 struct armv7m_common *armv7m = &cortex_m->armv7m;
487 struct arm *arm = &armv7m->arm;
488 struct reg *r;
489
490 LOG_DEBUG(" ");
491
492 /* Do this really early to minimize the window where the MASKINTS erratum
493 * can pile up pending interrupts. */
494 cortex_m_set_maskints_for_halt(target);
495
496 cortex_m_clear_halt(target);
497 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
498 if (retval != ERROR_OK)
499 return retval;
500
501 retval = armv7m->examine_debug_reason(target);
502 if (retval != ERROR_OK)
503 return retval;
504
505 /* examine PE security state */
506 bool secure_state = false;
507 if (armv7m->arm.is_armv8m) {
508 uint32_t dscsr;
509
510 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
511 if (retval != ERROR_OK)
512 return retval;
513
514 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
515 }
516
517 /* Examine target state and mode
518 * First load register accessible through core debug port */
519 int num_regs = arm->core_cache->num_regs;
520
521 for (i = 0; i < num_regs; i++) {
522 r = &armv7m->arm.core_cache->reg_list[i];
523 if (r->exist && !r->valid)
524 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
525 }
526
527 r = arm->cpsr;
528 xPSR = buf_get_u32(r->value, 0, 32);
529
530 /* Are we in an exception handler */
531 if (xPSR & 0x1FF) {
532 armv7m->exception_number = (xPSR & 0x1FF);
533
534 arm->core_mode = ARM_MODE_HANDLER;
535 arm->map = armv7m_msp_reg_map;
536 } else {
537 unsigned control = buf_get_u32(arm->core_cache
538 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
539
540 /* is this thread privileged? */
541 arm->core_mode = control & 1
542 ? ARM_MODE_USER_THREAD
543 : ARM_MODE_THREAD;
544
545 /* which stack is it using? */
546 if (control & 2)
547 arm->map = armv7m_psp_reg_map;
548 else
549 arm->map = armv7m_msp_reg_map;
550
551 armv7m->exception_number = 0;
552 }
553
554 if (armv7m->exception_number)
555 cortex_m_examine_exception_reason(target);
556
557 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
558 arm_mode_name(arm->core_mode),
559 buf_get_u32(arm->pc->value, 0, 32),
560 secure_state ? "Secure" : "Non-Secure",
561 target_state_name(target));
562
563 if (armv7m->post_debug_entry) {
564 retval = armv7m->post_debug_entry(target);
565 if (retval != ERROR_OK)
566 return retval;
567 }
568
569 return ERROR_OK;
570 }
571
572 static int cortex_m_poll(struct target *target)
573 {
574 int detected_failure = ERROR_OK;
575 int retval = ERROR_OK;
576 enum target_state prev_target_state = target->state;
577 struct cortex_m_common *cortex_m = target_to_cm(target);
578 struct armv7m_common *armv7m = &cortex_m->armv7m;
579
580 /* Read from Debug Halting Control and Status Register */
581 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
582 if (retval != ERROR_OK) {
583 target->state = TARGET_UNKNOWN;
584 return retval;
585 }
586
587 /* Recover from lockup. See ARMv7-M architecture spec,
588 * section B1.5.15 "Unrecoverable exception cases".
589 */
590 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
591 LOG_ERROR("%s -- clearing lockup after double fault",
592 target_name(target));
593 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
594 target->debug_reason = DBG_REASON_DBGRQ;
595
596 /* We have to execute the rest (the "finally" equivalent, but
597 * still throw this exception again).
598 */
599 detected_failure = ERROR_FAIL;
600
601 /* refresh status bits */
602 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
603 if (retval != ERROR_OK)
604 return retval;
605 }
606
607 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
608 if (target->state != TARGET_RESET) {
609 target->state = TARGET_RESET;
610 LOG_INFO("%s: external reset detected", target_name(target));
611 }
612 return ERROR_OK;
613 }
614
615 if (target->state == TARGET_RESET) {
616 /* Cannot switch context while running so endreset is
617 * called with target->state == TARGET_RESET
618 */
619 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
620 cortex_m->dcb_dhcsr);
621 retval = cortex_m_endreset_event(target);
622 if (retval != ERROR_OK) {
623 target->state = TARGET_UNKNOWN;
624 return retval;
625 }
626 target->state = TARGET_RUNNING;
627 prev_target_state = TARGET_RUNNING;
628 }
629
630 if (cortex_m->dcb_dhcsr & S_HALT) {
631 target->state = TARGET_HALTED;
632
633 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
634 retval = cortex_m_debug_entry(target);
635 if (retval != ERROR_OK)
636 return retval;
637
638 if (arm_semihosting(target, &retval) != 0)
639 return retval;
640
641 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
642 }
643 if (prev_target_state == TARGET_DEBUG_RUNNING) {
644 LOG_DEBUG(" ");
645 retval = cortex_m_debug_entry(target);
646 if (retval != ERROR_OK)
647 return retval;
648
649 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
650 }
651 }
652
653 if (target->state == TARGET_UNKNOWN) {
654 /* check if processor is retiring instructions or sleeping */
655 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
656 target->state = TARGET_RUNNING;
657 retval = ERROR_OK;
658 }
659 }
660
661 /* Check that target is truly halted, since the target could be resumed externally */
662 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
663 /* registers are now invalid */
664 register_cache_invalidate(armv7m->arm.core_cache);
665
666 target->state = TARGET_RUNNING;
667 LOG_WARNING("%s: external resume detected", target_name(target));
668 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
669 retval = ERROR_OK;
670 }
671
672 /* Did we detect a failure condition that we cleared? */
673 if (detected_failure != ERROR_OK)
674 retval = detected_failure;
675 return retval;
676 }
677
678 static int cortex_m_halt(struct target *target)
679 {
680 LOG_DEBUG("target->state: %s",
681 target_state_name(target));
682
683 if (target->state == TARGET_HALTED) {
684 LOG_DEBUG("target was already halted");
685 return ERROR_OK;
686 }
687
688 if (target->state == TARGET_UNKNOWN)
689 LOG_WARNING("target was in unknown state when halt was requested");
690
691 if (target->state == TARGET_RESET) {
692 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
693 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
694 return ERROR_TARGET_FAILURE;
695 } else {
696 /* we came here in a reset_halt or reset_init sequence
697 * debug entry was already prepared in cortex_m3_assert_reset()
698 */
699 target->debug_reason = DBG_REASON_DBGRQ;
700
701 return ERROR_OK;
702 }
703 }
704
705 /* Write to Debug Halting Control and Status Register */
706 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
707
708 /* Do this really early to minimize the window where the MASKINTS erratum
709 * can pile up pending interrupts. */
710 cortex_m_set_maskints_for_halt(target);
711
712 target->debug_reason = DBG_REASON_DBGRQ;
713
714 return ERROR_OK;
715 }
716
717 static int cortex_m_soft_reset_halt(struct target *target)
718 {
719 struct cortex_m_common *cortex_m = target_to_cm(target);
720 struct armv7m_common *armv7m = &cortex_m->armv7m;
721 uint32_t dcb_dhcsr = 0;
722 int retval, timeout = 0;
723
724 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
725 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
726 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
727 * core, not the peripherals */
728 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
729
730 /* Set C_DEBUGEN */
731 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
732 if (retval != ERROR_OK)
733 return retval;
734
735 /* Enter debug state on reset; restore DEMCR in endreset_event() */
736 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
737 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
738 if (retval != ERROR_OK)
739 return retval;
740
741 /* Request a core-only reset */
742 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
743 AIRCR_VECTKEY | AIRCR_VECTRESET);
744 if (retval != ERROR_OK)
745 return retval;
746 target->state = TARGET_RESET;
747
748 /* registers are now invalid */
749 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
750
751 while (timeout < 100) {
752 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
753 if (retval == ERROR_OK) {
754 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
755 &cortex_m->nvic_dfsr);
756 if (retval != ERROR_OK)
757 return retval;
758 if ((dcb_dhcsr & S_HALT)
759 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
760 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
761 "DFSR 0x%08x",
762 (unsigned) dcb_dhcsr,
763 (unsigned) cortex_m->nvic_dfsr);
764 cortex_m_poll(target);
765 /* FIXME restore user's vector catch config */
766 return ERROR_OK;
767 } else
768 LOG_DEBUG("waiting for system reset-halt, "
769 "DHCSR 0x%08x, %d ms",
770 (unsigned) dcb_dhcsr, timeout);
771 }
772 timeout++;
773 alive_sleep(1);
774 }
775
776 return ERROR_OK;
777 }
778
779 void cortex_m_enable_breakpoints(struct target *target)
780 {
781 struct breakpoint *breakpoint = target->breakpoints;
782
783 /* set any pending breakpoints */
784 while (breakpoint) {
785 if (!breakpoint->set)
786 cortex_m_set_breakpoint(target, breakpoint);
787 breakpoint = breakpoint->next;
788 }
789 }
790
791 static int cortex_m_resume(struct target *target, int current,
792 target_addr_t address, int handle_breakpoints, int debug_execution)
793 {
794 struct armv7m_common *armv7m = target_to_armv7m(target);
795 struct breakpoint *breakpoint = NULL;
796 uint32_t resume_pc;
797 struct reg *r;
798
799 if (target->state != TARGET_HALTED) {
800 LOG_WARNING("target not halted");
801 return ERROR_TARGET_NOT_HALTED;
802 }
803
804 if (!debug_execution) {
805 target_free_all_working_areas(target);
806 cortex_m_enable_breakpoints(target);
807 cortex_m_enable_watchpoints(target);
808 }
809
810 if (debug_execution) {
811 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
812
813 /* Disable interrupts */
814 /* We disable interrupts in the PRIMASK register instead of
815 * masking with C_MASKINTS. This is probably the same issue
816 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
817 * in parallel with disabled interrupts can cause local faults
818 * to not be taken.
819 *
820 * This breaks non-debug (application) execution if not
821 * called from armv7m_start_algorithm() which saves registers.
822 */
823 buf_set_u32(r->value, 0, 1, 1);
824 r->dirty = true;
825 r->valid = true;
826
827 /* Make sure we are in Thumb mode, set xPSR.T bit */
828 /* armv7m_start_algorithm() initializes entire xPSR register.
829 * This duplicity handles the case when cortex_m_resume()
830 * is used with the debug_execution flag directly,
831 * not called through armv7m_start_algorithm().
832 */
833 r = armv7m->arm.cpsr;
834 buf_set_u32(r->value, 24, 1, 1);
835 r->dirty = true;
836 r->valid = true;
837 }
838
839 /* current = 1: continue on current pc, otherwise continue at <address> */
840 r = armv7m->arm.pc;
841 if (!current) {
842 buf_set_u32(r->value, 0, 32, address);
843 r->dirty = true;
844 r->valid = true;
845 }
846
847 /* if we halted last time due to a bkpt instruction
848 * then we have to manually step over it, otherwise
849 * the core will break again */
850
851 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
852 && !debug_execution)
853 armv7m_maybe_skip_bkpt_inst(target, NULL);
854
855 resume_pc = buf_get_u32(r->value, 0, 32);
856
857 armv7m_restore_context(target);
858
859 /* the front-end may request us not to handle breakpoints */
860 if (handle_breakpoints) {
861 /* Single step past breakpoint at current address */
862 breakpoint = breakpoint_find(target, resume_pc);
863 if (breakpoint) {
864 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
865 breakpoint->address,
866 breakpoint->unique_id);
867 cortex_m_unset_breakpoint(target, breakpoint);
868 cortex_m_single_step_core(target);
869 cortex_m_set_breakpoint(target, breakpoint);
870 }
871 }
872
873 /* Restart core */
874 cortex_m_set_maskints_for_run(target);
875 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
876
877 target->debug_reason = DBG_REASON_NOTHALTED;
878
879 /* registers are now invalid */
880 register_cache_invalidate(armv7m->arm.core_cache);
881
882 if (!debug_execution) {
883 target->state = TARGET_RUNNING;
884 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
885 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
886 } else {
887 target->state = TARGET_DEBUG_RUNNING;
888 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
889 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
890 }
891
892 return ERROR_OK;
893 }
894
895 /* int irqstepcount = 0; */
896 static int cortex_m_step(struct target *target, int current,
897 target_addr_t address, int handle_breakpoints)
898 {
899 struct cortex_m_common *cortex_m = target_to_cm(target);
900 struct armv7m_common *armv7m = &cortex_m->armv7m;
901 struct breakpoint *breakpoint = NULL;
902 struct reg *pc = armv7m->arm.pc;
903 bool bkpt_inst_found = false;
904 int retval;
905 bool isr_timed_out = false;
906
907 if (target->state != TARGET_HALTED) {
908 LOG_WARNING("target not halted");
909 return ERROR_TARGET_NOT_HALTED;
910 }
911
912 /* current = 1: continue on current pc, otherwise continue at <address> */
913 if (!current)
914 buf_set_u32(pc->value, 0, 32, address);
915
916 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
917
918 /* the front-end may request us not to handle breakpoints */
919 if (handle_breakpoints) {
920 breakpoint = breakpoint_find(target, pc_value);
921 if (breakpoint)
922 cortex_m_unset_breakpoint(target, breakpoint);
923 }
924
925 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
926
927 target->debug_reason = DBG_REASON_SINGLESTEP;
928
929 armv7m_restore_context(target);
930
931 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
932
933 /* if no bkpt instruction is found at pc then we can perform
934 * a normal step, otherwise we have to manually step over the bkpt
935 * instruction - as such simulate a step */
936 if (bkpt_inst_found == false) {
937 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
938 /* Automatic ISR masking mode off: Just step over the next
939 * instruction, with interrupts on or off as appropriate. */
940 cortex_m_set_maskints_for_step(target);
941 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
942 } else {
943 /* Process interrupts during stepping in a way they don't interfere
944 * debugging.
945 *
946 * Principle:
947 *
948 * Set a temporary break point at the current pc and let the core run
949 * with interrupts enabled. Pending interrupts get served and we run
950 * into the breakpoint again afterwards. Then we step over the next
951 * instruction with interrupts disabled.
952 *
953 * If the pending interrupts don't complete within time, we leave the
954 * core running. This may happen if the interrupts trigger faster
955 * than the core can process them or the handler doesn't return.
956 *
957 * If no more breakpoints are available we simply do a step with
958 * interrupts enabled.
959 *
960 */
961
962 /* 2012-09-29 ph
963 *
964 * If a break point is already set on the lower half word then a break point on
965 * the upper half word will not break again when the core is restarted. So we
966 * just step over the instruction with interrupts disabled.
967 *
968 * The documentation has no information about this, it was found by observation
969 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
970 * suffer from this problem.
971 *
972 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
973 * address has it always cleared. The former is done to indicate thumb mode
974 * to gdb.
975 *
976 */
977 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
978 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
979 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
980 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
981 /* Re-enable interrupts if appropriate */
982 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
983 cortex_m_set_maskints_for_halt(target);
984 } else {
985
986 /* Set a temporary break point */
987 if (breakpoint) {
988 retval = cortex_m_set_breakpoint(target, breakpoint);
989 } else {
990 enum breakpoint_type type = BKPT_HARD;
991 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
992 /* FPB rev.1 cannot handle such addr, try BKPT instr */
993 type = BKPT_SOFT;
994 }
995 retval = breakpoint_add(target, pc_value, 2, type);
996 }
997
998 bool tmp_bp_set = (retval == ERROR_OK);
999
1000 /* No more breakpoints left, just do a step */
1001 if (!tmp_bp_set) {
1002 cortex_m_set_maskints_for_step(target);
1003 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1004 /* Re-enable interrupts if appropriate */
1005 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1006 cortex_m_set_maskints_for_halt(target);
1007 } else {
1008 /* Start the core */
1009 LOG_DEBUG("Starting core to serve pending interrupts");
1010 int64_t t_start = timeval_ms();
1011 cortex_m_set_maskints_for_run(target);
1012 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1013
1014 /* Wait for pending handlers to complete or timeout */
1015 do {
1016 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1017 DCB_DHCSR,
1018 &cortex_m->dcb_dhcsr);
1019 if (retval != ERROR_OK) {
1020 target->state = TARGET_UNKNOWN;
1021 return retval;
1022 }
1023 isr_timed_out = ((timeval_ms() - t_start) > 500);
1024 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1025
1026 /* only remove breakpoint if we created it */
1027 if (breakpoint)
1028 cortex_m_unset_breakpoint(target, breakpoint);
1029 else {
1030 /* Remove the temporary breakpoint */
1031 breakpoint_remove(target, pc_value);
1032 }
1033
1034 if (isr_timed_out) {
1035 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1036 "leaving target running");
1037 } else {
1038 /* Step over next instruction with interrupts disabled */
1039 cortex_m_set_maskints_for_step(target);
1040 cortex_m_write_debug_halt_mask(target,
1041 C_HALT | C_MASKINTS,
1042 0);
1043 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1044 /* Re-enable interrupts if appropriate */
1045 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1046 cortex_m_set_maskints_for_halt(target);
1047 }
1048 }
1049 }
1050 }
1051 }
1052
1053 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1054 if (retval != ERROR_OK)
1055 return retval;
1056
1057 /* registers are now invalid */
1058 register_cache_invalidate(armv7m->arm.core_cache);
1059
1060 if (breakpoint)
1061 cortex_m_set_breakpoint(target, breakpoint);
1062
1063 if (isr_timed_out) {
1064 /* Leave the core running. The user has to stop execution manually. */
1065 target->debug_reason = DBG_REASON_NOTHALTED;
1066 target->state = TARGET_RUNNING;
1067 return ERROR_OK;
1068 }
1069
1070 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1071 " nvic_icsr = 0x%" PRIx32,
1072 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1073
1074 retval = cortex_m_debug_entry(target);
1075 if (retval != ERROR_OK)
1076 return retval;
1077 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1078
1079 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1080 " nvic_icsr = 0x%" PRIx32,
1081 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1082
1083 return ERROR_OK;
1084 }
1085
1086 static int cortex_m_assert_reset(struct target *target)
1087 {
1088 struct cortex_m_common *cortex_m = target_to_cm(target);
1089 struct armv7m_common *armv7m = &cortex_m->armv7m;
1090 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1091
1092 LOG_DEBUG("target->state: %s",
1093 target_state_name(target));
1094
1095 enum reset_types jtag_reset_config = jtag_get_reset_config();
1096
1097 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1098 /* allow scripts to override the reset event */
1099
1100 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1101 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1102 target->state = TARGET_RESET;
1103
1104 return ERROR_OK;
1105 }
1106
1107 /* some cores support connecting while srst is asserted
1108 * use that mode is it has been configured */
1109
1110 bool srst_asserted = false;
1111
1112 if (!target_was_examined(target)) {
1113 if (jtag_reset_config & RESET_HAS_SRST) {
1114 adapter_assert_reset();
1115 if (target->reset_halt)
1116 LOG_ERROR("Target not examined, will not halt after reset!");
1117 return ERROR_OK;
1118 } else {
1119 LOG_ERROR("Target not examined, reset NOT asserted!");
1120 return ERROR_FAIL;
1121 }
1122 }
1123
1124 if ((jtag_reset_config & RESET_HAS_SRST) &&
1125 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1126 adapter_assert_reset();
1127 srst_asserted = true;
1128 }
1129
1130 /* Enable debug requests */
1131 int retval;
1132 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1133 /* Store important errors instead of failing and proceed to reset assert */
1134
1135 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1136 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1137
1138 /* If the processor is sleeping in a WFI or WFE instruction, the
1139 * C_HALT bit must be asserted to regain control */
1140 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1141 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1142
1143 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1144 /* Ignore less important errors */
1145
1146 if (!target->reset_halt) {
1147 /* Set/Clear C_MASKINTS in a separate operation */
1148 cortex_m_set_maskints_for_run(target);
1149
1150 /* clear any debug flags before resuming */
1151 cortex_m_clear_halt(target);
1152
1153 /* clear C_HALT in dhcsr reg */
1154 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1155 } else {
1156 /* Halt in debug on reset; endreset_event() restores DEMCR.
1157 *
1158 * REVISIT catching BUSERR presumably helps to defend against
1159 * bad vector table entries. Should this include MMERR or
1160 * other flags too?
1161 */
1162 int retval2;
1163 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1164 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1165 if (retval != ERROR_OK || retval2 != ERROR_OK)
1166 LOG_INFO("AP write error, reset will not halt");
1167 }
1168
1169 if (jtag_reset_config & RESET_HAS_SRST) {
1170 /* default to asserting srst */
1171 if (!srst_asserted)
1172 adapter_assert_reset();
1173
1174 /* srst is asserted, ignore AP access errors */
1175 retval = ERROR_OK;
1176 } else {
1177 /* Use a standard Cortex-M3 software reset mechanism.
1178 * We default to using VECRESET as it is supported on all current cores
1179 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1180 * This has the disadvantage of not resetting the peripherals, so a
1181 * reset-init event handler is needed to perform any peripheral resets.
1182 */
1183 if (!cortex_m->vectreset_supported
1184 && reset_config == CORTEX_M_RESET_VECTRESET) {
1185 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1186 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1187 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1188 }
1189
1190 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1191 ? "SYSRESETREQ" : "VECTRESET");
1192
1193 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1194 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1195 "handler to reset any peripherals or configure hardware srst support.");
1196 }
1197
1198 int retval3;
1199 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1200 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1201 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1202 if (retval3 != ERROR_OK)
1203 LOG_DEBUG("Ignoring AP write error right after reset");
1204
1205 retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1206 if (retval3 != ERROR_OK) {
1207 LOG_ERROR("DP initialisation failed");
1208 /* The error return value must not be propagated in this case.
1209 * SYSRESETREQ or VECTRESET have been possibly triggered
1210 * so reset processing should continue */
1211 } else {
1212 /* I do not know why this is necessary, but it
1213 * fixes strange effects (step/resume cause NMI
1214 * after reset) on LM3S6918 -- Michael Schwingen
1215 */
1216 uint32_t tmp;
1217 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1218 }
1219 }
1220
1221 target->state = TARGET_RESET;
1222 jtag_sleep(50000);
1223
1224 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1225
1226 /* now return stored error code if any */
1227 if (retval != ERROR_OK)
1228 return retval;
1229
1230 if (target->reset_halt) {
1231 retval = target_halt(target);
1232 if (retval != ERROR_OK)
1233 return retval;
1234 }
1235
1236 return ERROR_OK;
1237 }
1238
1239 static int cortex_m_deassert_reset(struct target *target)
1240 {
1241 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1242
1243 LOG_DEBUG("target->state: %s",
1244 target_state_name(target));
1245
1246 /* deassert reset lines */
1247 adapter_deassert_reset();
1248
1249 enum reset_types jtag_reset_config = jtag_get_reset_config();
1250
1251 if ((jtag_reset_config & RESET_HAS_SRST) &&
1252 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1253 target_was_examined(target)) {
1254
1255 int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1256 if (retval != ERROR_OK) {
1257 LOG_ERROR("DP initialisation failed");
1258 return retval;
1259 }
1260 }
1261
1262 return ERROR_OK;
1263 }
1264
1265 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1266 {
1267 int retval;
1268 unsigned int fp_num = 0;
1269 struct cortex_m_common *cortex_m = target_to_cm(target);
1270 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1271
1272 if (breakpoint->set) {
1273 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1274 return ERROR_OK;
1275 }
1276
1277 if (breakpoint->type == BKPT_HARD) {
1278 uint32_t fpcr_value;
1279 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1280 fp_num++;
1281 if (fp_num >= cortex_m->fp_num_code) {
1282 LOG_ERROR("Can not find free FPB Comparator!");
1283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1284 }
1285 breakpoint->set = fp_num + 1;
1286 fpcr_value = breakpoint->address | 1;
1287 if (cortex_m->fp_rev == 0) {
1288 if (breakpoint->address > 0x1FFFFFFF) {
1289 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1290 return ERROR_FAIL;
1291 }
1292 uint32_t hilo;
1293 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1294 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1295 } else if (cortex_m->fp_rev > 1) {
1296 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1297 return ERROR_FAIL;
1298 }
1299 comparator_list[fp_num].used = true;
1300 comparator_list[fp_num].fpcr_value = fpcr_value;
1301 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1302 comparator_list[fp_num].fpcr_value);
1303 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1304 fp_num,
1305 comparator_list[fp_num].fpcr_value);
1306 if (!cortex_m->fpb_enabled) {
1307 LOG_DEBUG("FPB wasn't enabled, do it now");
1308 retval = cortex_m_enable_fpb(target);
1309 if (retval != ERROR_OK) {
1310 LOG_ERROR("Failed to enable the FPB");
1311 return retval;
1312 }
1313
1314 cortex_m->fpb_enabled = true;
1315 }
1316 } else if (breakpoint->type == BKPT_SOFT) {
1317 uint8_t code[4];
1318
1319 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1320 * semihosting; don't use that. Otherwise the BKPT
1321 * parameter is arbitrary.
1322 */
1323 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1324 retval = target_read_memory(target,
1325 breakpoint->address & 0xFFFFFFFE,
1326 breakpoint->length, 1,
1327 breakpoint->orig_instr);
1328 if (retval != ERROR_OK)
1329 return retval;
1330 retval = target_write_memory(target,
1331 breakpoint->address & 0xFFFFFFFE,
1332 breakpoint->length, 1,
1333 code);
1334 if (retval != ERROR_OK)
1335 return retval;
1336 breakpoint->set = true;
1337 }
1338
1339 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1340 breakpoint->unique_id,
1341 (int)(breakpoint->type),
1342 breakpoint->address,
1343 breakpoint->length,
1344 breakpoint->set);
1345
1346 return ERROR_OK;
1347 }
1348
1349 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1350 {
1351 int retval;
1352 struct cortex_m_common *cortex_m = target_to_cm(target);
1353 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1354
1355 if (breakpoint->set <= 0) {
1356 LOG_WARNING("breakpoint not set");
1357 return ERROR_OK;
1358 }
1359
1360 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1361 breakpoint->unique_id,
1362 (int)(breakpoint->type),
1363 breakpoint->address,
1364 breakpoint->length,
1365 breakpoint->set);
1366
1367 if (breakpoint->type == BKPT_HARD) {
1368 unsigned int fp_num = breakpoint->set - 1;
1369 if (fp_num >= cortex_m->fp_num_code) {
1370 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1371 return ERROR_OK;
1372 }
1373 comparator_list[fp_num].used = false;
1374 comparator_list[fp_num].fpcr_value = 0;
1375 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1376 comparator_list[fp_num].fpcr_value);
1377 } else {
1378 /* restore original instruction (kept in target endianness) */
1379 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1380 breakpoint->length, 1,
1381 breakpoint->orig_instr);
1382 if (retval != ERROR_OK)
1383 return retval;
1384 }
1385 breakpoint->set = false;
1386
1387 return ERROR_OK;
1388 }
1389
1390 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1391 {
1392 if (breakpoint->length == 3) {
1393 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1394 breakpoint->length = 2;
1395 }
1396
1397 if ((breakpoint->length != 2)) {
1398 LOG_INFO("only breakpoints of two bytes length supported");
1399 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1400 }
1401
1402 return cortex_m_set_breakpoint(target, breakpoint);
1403 }
1404
1405 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1406 {
1407 if (!breakpoint->set)
1408 return ERROR_OK;
1409
1410 return cortex_m_unset_breakpoint(target, breakpoint);
1411 }
1412
1413 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1414 {
1415 unsigned int dwt_num = 0;
1416 struct cortex_m_common *cortex_m = target_to_cm(target);
1417
1418 /* REVISIT Don't fully trust these "not used" records ... users
1419 * may set up breakpoints by hand, e.g. dual-address data value
1420 * watchpoint using comparator #1; comparator #0 matching cycle
1421 * count; send data trace info through ITM and TPIU; etc
1422 */
1423 struct cortex_m_dwt_comparator *comparator;
1424
1425 for (comparator = cortex_m->dwt_comparator_list;
1426 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1427 comparator++, dwt_num++)
1428 continue;
1429 if (dwt_num >= cortex_m->dwt_num_comp) {
1430 LOG_ERROR("Can not find free DWT Comparator");
1431 return ERROR_FAIL;
1432 }
1433 comparator->used = true;
1434 watchpoint->set = dwt_num + 1;
1435
1436 comparator->comp = watchpoint->address;
1437 target_write_u32(target, comparator->dwt_comparator_address + 0,
1438 comparator->comp);
1439
1440 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1441 uint32_t mask = 0, temp;
1442
1443 /* watchpoint params were validated earlier */
1444 temp = watchpoint->length;
1445 while (temp) {
1446 temp >>= 1;
1447 mask++;
1448 }
1449 mask--;
1450
1451 comparator->mask = mask;
1452 target_write_u32(target, comparator->dwt_comparator_address + 4,
1453 comparator->mask);
1454
1455 switch (watchpoint->rw) {
1456 case WPT_READ:
1457 comparator->function = 5;
1458 break;
1459 case WPT_WRITE:
1460 comparator->function = 6;
1461 break;
1462 case WPT_ACCESS:
1463 comparator->function = 7;
1464 break;
1465 }
1466 } else {
1467 uint32_t data_size = watchpoint->length >> 1;
1468 comparator->mask = (watchpoint->length >> 1) | 1;
1469
1470 switch (watchpoint->rw) {
1471 case WPT_ACCESS:
1472 comparator->function = 4;
1473 break;
1474 case WPT_WRITE:
1475 comparator->function = 5;
1476 break;
1477 case WPT_READ:
1478 comparator->function = 6;
1479 break;
1480 }
1481 comparator->function = comparator->function | (1 << 4) |
1482 (data_size << 10);
1483 }
1484
1485 target_write_u32(target, comparator->dwt_comparator_address + 8,
1486 comparator->function);
1487
1488 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1489 watchpoint->unique_id, dwt_num,
1490 (unsigned) comparator->comp,
1491 (unsigned) comparator->mask,
1492 (unsigned) comparator->function);
1493 return ERROR_OK;
1494 }
1495
1496 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1497 {
1498 struct cortex_m_common *cortex_m = target_to_cm(target);
1499 struct cortex_m_dwt_comparator *comparator;
1500
1501 if (watchpoint->set <= 0) {
1502 LOG_WARNING("watchpoint (wpid: %d) not set",
1503 watchpoint->unique_id);
1504 return ERROR_OK;
1505 }
1506
1507 unsigned int dwt_num = watchpoint->set - 1;
1508
1509 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1510 watchpoint->unique_id, dwt_num,
1511 (unsigned) watchpoint->address);
1512
1513 if (dwt_num >= cortex_m->dwt_num_comp) {
1514 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1515 return ERROR_OK;
1516 }
1517
1518 comparator = cortex_m->dwt_comparator_list + dwt_num;
1519 comparator->used = false;
1520 comparator->function = 0;
1521 target_write_u32(target, comparator->dwt_comparator_address + 8,
1522 comparator->function);
1523
1524 watchpoint->set = false;
1525
1526 return ERROR_OK;
1527 }
1528
1529 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1530 {
1531 struct cortex_m_common *cortex_m = target_to_cm(target);
1532
1533 if (cortex_m->dwt_comp_available < 1) {
1534 LOG_DEBUG("no comparators?");
1535 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1536 }
1537
1538 /* hardware doesn't support data value masking */
1539 if (watchpoint->mask != ~(uint32_t)0) {
1540 LOG_DEBUG("watchpoint value masks not supported");
1541 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1542 }
1543
1544 /* hardware allows address masks of up to 32K */
1545 unsigned mask;
1546
1547 for (mask = 0; mask < 16; mask++) {
1548 if ((1u << mask) == watchpoint->length)
1549 break;
1550 }
1551 if (mask == 16) {
1552 LOG_DEBUG("unsupported watchpoint length");
1553 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1554 }
1555 if (watchpoint->address & ((1 << mask) - 1)) {
1556 LOG_DEBUG("watchpoint address is unaligned");
1557 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1558 }
1559
1560 /* Caller doesn't seem to be able to describe watching for data
1561 * values of zero; that flags "no value".
1562 *
1563 * REVISIT This DWT may well be able to watch for specific data
1564 * values. Requires comparator #1 to set DATAVMATCH and match
1565 * the data, and another comparator (DATAVADDR0) matching addr.
1566 */
1567 if (watchpoint->value) {
1568 LOG_DEBUG("data value watchpoint not YET supported");
1569 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1570 }
1571
1572 cortex_m->dwt_comp_available--;
1573 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1574
1575 return ERROR_OK;
1576 }
1577
1578 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1579 {
1580 struct cortex_m_common *cortex_m = target_to_cm(target);
1581
1582 /* REVISIT why check? DWT can be updated with core running ... */
1583 if (target->state != TARGET_HALTED) {
1584 LOG_WARNING("target not halted");
1585 return ERROR_TARGET_NOT_HALTED;
1586 }
1587
1588 if (watchpoint->set)
1589 cortex_m_unset_watchpoint(target, watchpoint);
1590
1591 cortex_m->dwt_comp_available++;
1592 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1593
1594 return ERROR_OK;
1595 }
1596
1597 int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1598 {
1599 if (target->debug_reason != DBG_REASON_WATCHPOINT)
1600 return ERROR_FAIL;
1601
1602 struct cortex_m_common *cortex_m = target_to_cm(target);
1603
1604 for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
1605 if (!wp->set)
1606 continue;
1607
1608 unsigned int dwt_num = wp->set - 1;
1609 struct cortex_m_dwt_comparator *comparator = cortex_m->dwt_comparator_list + dwt_num;
1610
1611 uint32_t dwt_function;
1612 int retval = target_read_u32(target, comparator->dwt_comparator_address + 8, &dwt_function);
1613 if (retval != ERROR_OK)
1614 return ERROR_FAIL;
1615
1616 /* check the MATCHED bit */
1617 if (dwt_function & BIT(24)) {
1618 *hit_watchpoint = wp;
1619 return ERROR_OK;
1620 }
1621 }
1622
1623 return ERROR_FAIL;
1624 }
1625
1626 void cortex_m_enable_watchpoints(struct target *target)
1627 {
1628 struct watchpoint *watchpoint = target->watchpoints;
1629
1630 /* set any pending watchpoints */
1631 while (watchpoint) {
1632 if (!watchpoint->set)
1633 cortex_m_set_watchpoint(target, watchpoint);
1634 watchpoint = watchpoint->next;
1635 }
1636 }
1637
1638 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1639 uint32_t size, uint32_t count, uint8_t *buffer)
1640 {
1641 struct armv7m_common *armv7m = target_to_armv7m(target);
1642
1643 if (armv7m->arm.is_armv6m) {
1644 /* armv6m does not handle unaligned memory access */
1645 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1646 return ERROR_TARGET_UNALIGNED_ACCESS;
1647 }
1648
1649 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1650 }
1651
1652 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1653 uint32_t size, uint32_t count, const uint8_t *buffer)
1654 {
1655 struct armv7m_common *armv7m = target_to_armv7m(target);
1656
1657 if (armv7m->arm.is_armv6m) {
1658 /* armv6m does not handle unaligned memory access */
1659 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1660 return ERROR_TARGET_UNALIGNED_ACCESS;
1661 }
1662
1663 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1664 }
1665
1666 static int cortex_m_init_target(struct command_context *cmd_ctx,
1667 struct target *target)
1668 {
1669 armv7m_build_reg_cache(target);
1670 arm_semihosting_init(target);
1671 return ERROR_OK;
1672 }
1673
1674 void cortex_m_deinit_target(struct target *target)
1675 {
1676 struct cortex_m_common *cortex_m = target_to_cm(target);
1677
1678 free(cortex_m->fp_comparator_list);
1679
1680 cortex_m_dwt_free(target);
1681 armv7m_free_reg_cache(target);
1682
1683 free(target->private_config);
1684 free(cortex_m);
1685 }
1686
1687 int cortex_m_profiling(struct target *target, uint32_t *samples,
1688 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1689 {
1690 struct timeval timeout, now;
1691 struct armv7m_common *armv7m = target_to_armv7m(target);
1692 uint32_t reg_value;
1693 int retval;
1694
1695 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1696 if (retval != ERROR_OK) {
1697 LOG_ERROR("Error while reading PCSR");
1698 return retval;
1699 }
1700 if (reg_value == 0) {
1701 LOG_INFO("PCSR sampling not supported on this processor.");
1702 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1703 }
1704
1705 gettimeofday(&timeout, NULL);
1706 timeval_add_time(&timeout, seconds, 0);
1707
1708 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1709
1710 /* Make sure the target is running */
1711 target_poll(target);
1712 if (target->state == TARGET_HALTED)
1713 retval = target_resume(target, 1, 0, 0, 0);
1714
1715 if (retval != ERROR_OK) {
1716 LOG_ERROR("Error while resuming target");
1717 return retval;
1718 }
1719
1720 uint32_t sample_count = 0;
1721
1722 for (;;) {
1723 if (armv7m && armv7m->debug_ap) {
1724 uint32_t read_count = max_num_samples - sample_count;
1725 if (read_count > 1024)
1726 read_count = 1024;
1727
1728 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1729 (void *)&samples[sample_count],
1730 4, read_count, DWT_PCSR);
1731 sample_count += read_count;
1732 } else {
1733 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1734 }
1735
1736 if (retval != ERROR_OK) {
1737 LOG_ERROR("Error while reading PCSR");
1738 return retval;
1739 }
1740
1741
1742 gettimeofday(&now, NULL);
1743 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1744 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1745 break;
1746 }
1747 }
1748
1749 *num_samples = sample_count;
1750 return retval;
1751 }
1752
1753
1754 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1755 * on r/w if the core is not running, and clear on resume or reset ... or
1756 * at least, in a post_restore_context() method.
1757 */
1758
1759 struct dwt_reg_state {
1760 struct target *target;
1761 uint32_t addr;
1762 uint8_t value[4]; /* scratch/cache */
1763 };
1764
1765 static int cortex_m_dwt_get_reg(struct reg *reg)
1766 {
1767 struct dwt_reg_state *state = reg->arch_info;
1768
1769 uint32_t tmp;
1770 int retval = target_read_u32(state->target, state->addr, &tmp);
1771 if (retval != ERROR_OK)
1772 return retval;
1773
1774 buf_set_u32(state->value, 0, 32, tmp);
1775 return ERROR_OK;
1776 }
1777
1778 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1779 {
1780 struct dwt_reg_state *state = reg->arch_info;
1781
1782 return target_write_u32(state->target, state->addr,
1783 buf_get_u32(buf, 0, reg->size));
1784 }
1785
1786 struct dwt_reg {
1787 uint32_t addr;
1788 const char *name;
1789 unsigned size;
1790 };
1791
1792 static const struct dwt_reg dwt_base_regs[] = {
1793 { DWT_CTRL, "dwt_ctrl", 32, },
1794 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1795 * increments while the core is asleep.
1796 */
1797 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1798 /* plus some 8 bit counters, useful for profiling with TPIU */
1799 };
1800
1801 static const struct dwt_reg dwt_comp[] = {
1802 #define DWT_COMPARATOR(i) \
1803 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1804 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1805 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1806 DWT_COMPARATOR(0),
1807 DWT_COMPARATOR(1),
1808 DWT_COMPARATOR(2),
1809 DWT_COMPARATOR(3),
1810 DWT_COMPARATOR(4),
1811 DWT_COMPARATOR(5),
1812 DWT_COMPARATOR(6),
1813 DWT_COMPARATOR(7),
1814 DWT_COMPARATOR(8),
1815 DWT_COMPARATOR(9),
1816 DWT_COMPARATOR(10),
1817 DWT_COMPARATOR(11),
1818 DWT_COMPARATOR(12),
1819 DWT_COMPARATOR(13),
1820 DWT_COMPARATOR(14),
1821 DWT_COMPARATOR(15),
1822 #undef DWT_COMPARATOR
1823 };
1824
1825 static const struct reg_arch_type dwt_reg_type = {
1826 .get = cortex_m_dwt_get_reg,
1827 .set = cortex_m_dwt_set_reg,
1828 };
1829
1830 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1831 {
1832 struct dwt_reg_state *state;
1833
1834 state = calloc(1, sizeof(*state));
1835 if (!state)
1836 return;
1837 state->addr = d->addr;
1838 state->target = t;
1839
1840 r->name = d->name;
1841 r->size = d->size;
1842 r->value = state->value;
1843 r->arch_info = state;
1844 r->type = &dwt_reg_type;
1845 }
1846
1847 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1848 {
1849 uint32_t dwtcr;
1850 struct reg_cache *cache;
1851 struct cortex_m_dwt_comparator *comparator;
1852 int reg;
1853
1854 target_read_u32(target, DWT_CTRL, &dwtcr);
1855 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1856 if (!dwtcr) {
1857 LOG_DEBUG("no DWT");
1858 return;
1859 }
1860
1861 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
1862 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
1863
1864 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1865 cm->dwt_comp_available = cm->dwt_num_comp;
1866 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1867 sizeof(struct cortex_m_dwt_comparator));
1868 if (!cm->dwt_comparator_list) {
1869 fail0:
1870 cm->dwt_num_comp = 0;
1871 LOG_ERROR("out of mem");
1872 return;
1873 }
1874
1875 cache = calloc(1, sizeof(*cache));
1876 if (!cache) {
1877 fail1:
1878 free(cm->dwt_comparator_list);
1879 goto fail0;
1880 }
1881 cache->name = "Cortex-M DWT registers";
1882 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1883 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
1884 if (!cache->reg_list) {
1885 free(cache);
1886 goto fail1;
1887 }
1888
1889 for (reg = 0; reg < 2; reg++)
1890 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1891 dwt_base_regs + reg);
1892
1893 comparator = cm->dwt_comparator_list;
1894 for (unsigned int i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1895 int j;
1896
1897 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1898 for (j = 0; j < 3; j++, reg++)
1899 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1900 dwt_comp + 3 * i + j);
1901
1902 /* make sure we clear any watchpoints enabled on the target */
1903 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1904 }
1905
1906 *register_get_last_cache_p(&target->reg_cache) = cache;
1907 cm->dwt_cache = cache;
1908
1909 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1910 dwtcr, cm->dwt_num_comp,
1911 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1912
1913 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1914 * implement single-address data value watchpoints ... so we
1915 * won't need to check it later, when asked to set one up.
1916 */
1917 }
1918
1919 static void cortex_m_dwt_free(struct target *target)
1920 {
1921 struct cortex_m_common *cm = target_to_cm(target);
1922 struct reg_cache *cache = cm->dwt_cache;
1923
1924 free(cm->dwt_comparator_list);
1925 cm->dwt_comparator_list = NULL;
1926 cm->dwt_num_comp = 0;
1927
1928 if (cache) {
1929 register_unlink_cache(&target->reg_cache, cache);
1930
1931 if (cache->reg_list) {
1932 for (size_t i = 0; i < cache->num_regs; i++)
1933 free(cache->reg_list[i].arch_info);
1934 free(cache->reg_list);
1935 }
1936 free(cache);
1937 }
1938 cm->dwt_cache = NULL;
1939 }
1940
1941 #define MVFR0 0xe000ef40
1942 #define MVFR1 0xe000ef44
1943
1944 #define MVFR0_DEFAULT_M4 0x10110021
1945 #define MVFR1_DEFAULT_M4 0x11000011
1946
1947 #define MVFR0_DEFAULT_M7_SP 0x10110021
1948 #define MVFR0_DEFAULT_M7_DP 0x10110221
1949 #define MVFR1_DEFAULT_M7_SP 0x11000011
1950 #define MVFR1_DEFAULT_M7_DP 0x12000011
1951
1952 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
1953 struct adiv5_ap **debug_ap)
1954 {
1955 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
1956 return ERROR_OK;
1957
1958 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
1959 }
1960
1961 int cortex_m_examine(struct target *target)
1962 {
1963 int retval;
1964 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1965 struct cortex_m_common *cortex_m = target_to_cm(target);
1966 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1967 struct armv7m_common *armv7m = target_to_armv7m(target);
1968
1969 /* stlink shares the examine handler but does not support
1970 * all its calls */
1971 if (!armv7m->stlink) {
1972 if (cortex_m->apsel == DP_APSEL_INVALID) {
1973 /* Search for the MEM-AP */
1974 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
1975 if (retval != ERROR_OK) {
1976 LOG_ERROR("Could not find MEM-AP to control the core");
1977 return retval;
1978 }
1979 } else {
1980 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1981 }
1982
1983 /* Leave (only) generic DAP stuff for debugport_init(); */
1984 armv7m->debug_ap->memaccess_tck = 8;
1985
1986 retval = mem_ap_init(armv7m->debug_ap);
1987 if (retval != ERROR_OK)
1988 return retval;
1989 }
1990
1991 if (!target_was_examined(target)) {
1992 target_set_examined(target);
1993
1994 /* Read from Device Identification Registers */
1995 retval = target_read_u32(target, CPUID, &cpuid);
1996 if (retval != ERROR_OK)
1997 return retval;
1998
1999 /* Get CPU Type */
2000 unsigned int core = (cpuid >> 4) & 0xf;
2001
2002 /* Check if it is an ARMv8-M core */
2003 armv7m->arm.is_armv8m = true;
2004
2005 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
2006 case CORTEX_M23_PARTNO:
2007 core = 23;
2008 break;
2009 case CORTEX_M33_PARTNO:
2010 core = 33;
2011 break;
2012 case CORTEX_M35P_PARTNO:
2013 core = 35;
2014 break;
2015 case CORTEX_M55_PARTNO:
2016 core = 55;
2017 break;
2018 default:
2019 armv7m->arm.is_armv8m = false;
2020 break;
2021 }
2022
2023
2024 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2025 core, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2026 cortex_m->maskints_erratum = false;
2027 if (core == 7) {
2028 uint8_t rev, patch;
2029 rev = (cpuid >> 20) & 0xf;
2030 patch = (cpuid >> 0) & 0xf;
2031 if ((rev == 0) && (patch < 2)) {
2032 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2033 cortex_m->maskints_erratum = true;
2034 }
2035 }
2036 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2037
2038 /* VECTRESET is supported only on ARMv7-M cores */
2039 cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m;
2040
2041 if (core == 4) {
2042 target_read_u32(target, MVFR0, &mvfr0);
2043 target_read_u32(target, MVFR1, &mvfr1);
2044
2045 /* test for floating point feature on Cortex-M4 */
2046 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2047 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", core);
2048 armv7m->fp_feature = FPV4_SP;
2049 }
2050 } else if (core == 7 || core == 33 || core == 35 || core == 55) {
2051 target_read_u32(target, MVFR0, &mvfr0);
2052 target_read_u32(target, MVFR1, &mvfr1);
2053
2054 /* test for floating point features on Cortex-M7 */
2055 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2056 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", core);
2057 armv7m->fp_feature = FPV5_SP;
2058 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2059 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", core);
2060 armv7m->fp_feature = FPV5_DP;
2061 }
2062 } else if (core == 0) {
2063 /* Cortex-M0 does not support unaligned memory access */
2064 armv7m->arm.is_armv6m = true;
2065 }
2066
2067 /* Check for FPU, otherwise mark FPU register as non-existent */
2068 if (armv7m->fp_feature == FP_NONE)
2069 for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
2070 armv7m->arm.core_cache->reg_list[idx].exist = false;
2071
2072 if (!armv7m->arm.is_armv8m)
2073 for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
2074 armv7m->arm.core_cache->reg_list[idx].exist = false;
2075
2076 if (!armv7m->stlink) {
2077 if (core == 3 || core == 4)
2078 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2079 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2080 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2081 else if (core == 7)
2082 /* Cortex-M7 has only 1024 bytes autoincrement range */
2083 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2084 }
2085
2086 /* Enable debug requests */
2087 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2088 if (retval != ERROR_OK)
2089 return retval;
2090 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2091 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2092
2093 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2094 if (retval != ERROR_OK)
2095 return retval;
2096 cortex_m->dcb_dhcsr = dhcsr;
2097 }
2098
2099 /* Configure trace modules */
2100 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2101 if (retval != ERROR_OK)
2102 return retval;
2103
2104 if (armv7m->trace_config.itm_deferred_config)
2105 armv7m_trace_itm_config(target);
2106
2107 /* NOTE: FPB and DWT are both optional. */
2108
2109 /* Setup FPB */
2110 target_read_u32(target, FP_CTRL, &fpcr);
2111 /* bits [14:12] and [7:4] */
2112 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2113 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2114 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2115 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2116 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2117 free(cortex_m->fp_comparator_list);
2118 cortex_m->fp_comparator_list = calloc(
2119 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2120 sizeof(struct cortex_m_fp_comparator));
2121 cortex_m->fpb_enabled = fpcr & 1;
2122 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2123 cortex_m->fp_comparator_list[i].type =
2124 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2125 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2126
2127 /* make sure we clear any breakpoints enabled on the target */
2128 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2129 }
2130 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2131 fpcr,
2132 cortex_m->fp_num_code,
2133 cortex_m->fp_num_lit);
2134
2135 /* Setup DWT */
2136 cortex_m_dwt_free(target);
2137 cortex_m_dwt_setup(cortex_m, target);
2138
2139 /* These hardware breakpoints only work for code in flash! */
2140 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2141 target_name(target),
2142 cortex_m->fp_num_code,
2143 cortex_m->dwt_num_comp);
2144 }
2145
2146 return ERROR_OK;
2147 }
2148
2149 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2150 {
2151 struct armv7m_common *armv7m = target_to_armv7m(target);
2152 uint16_t dcrdr;
2153 uint8_t buf[2];
2154 int retval;
2155
2156 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2157 if (retval != ERROR_OK)
2158 return retval;
2159
2160 dcrdr = target_buffer_get_u16(target, buf);
2161 *ctrl = (uint8_t)dcrdr;
2162 *value = (uint8_t)(dcrdr >> 8);
2163
2164 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2165
2166 /* write ack back to software dcc register
2167 * signify we have read data */
2168 if (dcrdr & (1 << 0)) {
2169 target_buffer_set_u16(target, buf, 0);
2170 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2171 if (retval != ERROR_OK)
2172 return retval;
2173 }
2174
2175 return ERROR_OK;
2176 }
2177
2178 static int cortex_m_target_request_data(struct target *target,
2179 uint32_t size, uint8_t *buffer)
2180 {
2181 uint8_t data;
2182 uint8_t ctrl;
2183 uint32_t i;
2184
2185 for (i = 0; i < (size * 4); i++) {
2186 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2187 if (retval != ERROR_OK)
2188 return retval;
2189 buffer[i] = data;
2190 }
2191
2192 return ERROR_OK;
2193 }
2194
2195 static int cortex_m_handle_target_request(void *priv)
2196 {
2197 struct target *target = priv;
2198 if (!target_was_examined(target))
2199 return ERROR_OK;
2200
2201 if (!target->dbg_msg_enabled)
2202 return ERROR_OK;
2203
2204 if (target->state == TARGET_RUNNING) {
2205 uint8_t data;
2206 uint8_t ctrl;
2207 int retval;
2208
2209 retval = cortex_m_dcc_read(target, &data, &ctrl);
2210 if (retval != ERROR_OK)
2211 return retval;
2212
2213 /* check if we have data */
2214 if (ctrl & (1 << 0)) {
2215 uint32_t request;
2216
2217 /* we assume target is quick enough */
2218 request = data;
2219 for (int i = 1; i <= 3; i++) {
2220 retval = cortex_m_dcc_read(target, &data, &ctrl);
2221 if (retval != ERROR_OK)
2222 return retval;
2223 request |= ((uint32_t)data << (i * 8));
2224 }
2225 target_request(target, request);
2226 }
2227 }
2228
2229 return ERROR_OK;
2230 }
2231
2232 static int cortex_m_init_arch_info(struct target *target,
2233 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2234 {
2235 struct armv7m_common *armv7m = &cortex_m->armv7m;
2236
2237 armv7m_init_arch_info(target, armv7m);
2238
2239 /* default reset mode is to use srst if fitted
2240 * if not it will use CORTEX_M3_RESET_VECTRESET */
2241 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2242
2243 armv7m->arm.dap = dap;
2244
2245 /* register arch-specific functions */
2246 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2247
2248 armv7m->post_debug_entry = NULL;
2249
2250 armv7m->pre_restore_context = NULL;
2251
2252 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2253 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2254
2255 target_register_timer_callback(cortex_m_handle_target_request, 1,
2256 TARGET_TIMER_TYPE_PERIODIC, target);
2257
2258 return ERROR_OK;
2259 }
2260
2261 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2262 {
2263 struct adiv5_private_config *pc;
2264
2265 pc = (struct adiv5_private_config *)target->private_config;
2266 if (adiv5_verify_config(pc) != ERROR_OK)
2267 return ERROR_FAIL;
2268
2269 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2270 if (cortex_m == NULL) {
2271 LOG_ERROR("No memory creating target");
2272 return ERROR_FAIL;
2273 }
2274
2275 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2276 cortex_m->apsel = pc->ap_num;
2277
2278 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2279
2280 return ERROR_OK;
2281 }
2282
2283 /*--------------------------------------------------------------------------*/
2284
2285 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2286 struct cortex_m_common *cm)
2287 {
2288 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2289 command_print(cmd, "target is not a Cortex-M");
2290 return ERROR_TARGET_INVALID;
2291 }
2292 return ERROR_OK;
2293 }
2294
2295 /*
2296 * Only stuff below this line should need to verify that its target
2297 * is a Cortex-M3. Everything else should have indirected through the
2298 * cortexm3_target structure, which is only used with CM3 targets.
2299 */
2300
2301 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2302 {
2303 struct target *target = get_current_target(CMD_CTX);
2304 struct cortex_m_common *cortex_m = target_to_cm(target);
2305 struct armv7m_common *armv7m = &cortex_m->armv7m;
2306 uint32_t demcr = 0;
2307 int retval;
2308
2309 static const struct {
2310 char name[10];
2311 unsigned mask;
2312 } vec_ids[] = {
2313 { "hard_err", VC_HARDERR, },
2314 { "int_err", VC_INTERR, },
2315 { "bus_err", VC_BUSERR, },
2316 { "state_err", VC_STATERR, },
2317 { "chk_err", VC_CHKERR, },
2318 { "nocp_err", VC_NOCPERR, },
2319 { "mm_err", VC_MMERR, },
2320 { "reset", VC_CORERESET, },
2321 };
2322
2323 retval = cortex_m_verify_pointer(CMD, cortex_m);
2324 if (retval != ERROR_OK)
2325 return retval;
2326
2327 if (!target_was_examined(target)) {
2328 LOG_ERROR("Target not examined yet");
2329 return ERROR_FAIL;
2330 }
2331
2332 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2333 if (retval != ERROR_OK)
2334 return retval;
2335
2336 if (CMD_ARGC > 0) {
2337 unsigned catch = 0;
2338
2339 if (CMD_ARGC == 1) {
2340 if (strcmp(CMD_ARGV[0], "all") == 0) {
2341 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2342 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2343 | VC_MMERR | VC_CORERESET;
2344 goto write;
2345 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2346 goto write;
2347 }
2348 while (CMD_ARGC-- > 0) {
2349 unsigned i;
2350 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2351 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2352 continue;
2353 catch |= vec_ids[i].mask;
2354 break;
2355 }
2356 if (i == ARRAY_SIZE(vec_ids)) {
2357 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2358 return ERROR_COMMAND_SYNTAX_ERROR;
2359 }
2360 }
2361 write:
2362 /* For now, armv7m->demcr only stores vector catch flags. */
2363 armv7m->demcr = catch;
2364
2365 demcr &= ~0xffff;
2366 demcr |= catch;
2367
2368 /* write, but don't assume it stuck (why not??) */
2369 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2370 if (retval != ERROR_OK)
2371 return retval;
2372 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2373 if (retval != ERROR_OK)
2374 return retval;
2375
2376 /* FIXME be sure to clear DEMCR on clean server shutdown.
2377 * Otherwise the vector catch hardware could fire when there's
2378 * no debugger hooked up, causing much confusion...
2379 */
2380 }
2381
2382 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2383 command_print(CMD, "%9s: %s", vec_ids[i].name,
2384 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2385 }
2386
2387 return ERROR_OK;
2388 }
2389
2390 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2391 {
2392 struct target *target = get_current_target(CMD_CTX);
2393 struct cortex_m_common *cortex_m = target_to_cm(target);
2394 int retval;
2395
2396 static const Jim_Nvp nvp_maskisr_modes[] = {
2397 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2398 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2399 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2400 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2401 { .name = NULL, .value = -1 },
2402 };
2403 const Jim_Nvp *n;
2404
2405
2406 retval = cortex_m_verify_pointer(CMD, cortex_m);
2407 if (retval != ERROR_OK)
2408 return retval;
2409
2410 if (target->state != TARGET_HALTED) {
2411 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2412 return ERROR_OK;
2413 }
2414
2415 if (CMD_ARGC > 0) {
2416 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2417 if (n->name == NULL)
2418 return ERROR_COMMAND_SYNTAX_ERROR;
2419 cortex_m->isrmasking_mode = n->value;
2420 cortex_m_set_maskints_for_halt(target);
2421 }
2422
2423 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2424 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2425
2426 return ERROR_OK;
2427 }
2428
2429 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2430 {
2431 struct target *target = get_current_target(CMD_CTX);
2432 struct cortex_m_common *cortex_m = target_to_cm(target);
2433 int retval;
2434 char *reset_config;
2435
2436 retval = cortex_m_verify_pointer(CMD, cortex_m);
2437 if (retval != ERROR_OK)
2438 return retval;
2439
2440 if (CMD_ARGC > 0) {
2441 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2442 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2443
2444 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2445 if (target_was_examined(target)
2446 && !cortex_m->vectreset_supported)
2447 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2448 else
2449 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2450
2451 } else
2452 return ERROR_COMMAND_SYNTAX_ERROR;
2453 }
2454
2455 switch (cortex_m->soft_reset_config) {
2456 case CORTEX_M_RESET_SYSRESETREQ:
2457 reset_config = "sysresetreq";
2458 break;
2459
2460 case CORTEX_M_RESET_VECTRESET:
2461 reset_config = "vectreset";
2462 break;
2463
2464 default:
2465 reset_config = "unknown";
2466 break;
2467 }
2468
2469 command_print(CMD, "cortex_m reset_config %s", reset_config);
2470
2471 return ERROR_OK;
2472 }
2473
2474 static const struct command_registration cortex_m_exec_command_handlers[] = {
2475 {
2476 .name = "maskisr",
2477 .handler = handle_cortex_m_mask_interrupts_command,
2478 .mode = COMMAND_EXEC,
2479 .help = "mask cortex_m interrupts",
2480 .usage = "['auto'|'on'|'off'|'steponly']",
2481 },
2482 {
2483 .name = "vector_catch",
2484 .handler = handle_cortex_m_vector_catch_command,
2485 .mode = COMMAND_EXEC,
2486 .help = "configure hardware vectors to trigger debug entry",
2487 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2488 },
2489 {
2490 .name = "reset_config",
2491 .handler = handle_cortex_m_reset_config_command,
2492 .mode = COMMAND_ANY,
2493 .help = "configure software reset handling",
2494 .usage = "['sysresetreq'|'vectreset']",
2495 },
2496 COMMAND_REGISTRATION_DONE
2497 };
2498 static const struct command_registration cortex_m_command_handlers[] = {
2499 {
2500 .chain = armv7m_command_handlers,
2501 },
2502 {
2503 .chain = armv7m_trace_command_handlers,
2504 },
2505 /* START_DEPRECATED_TPIU */
2506 {
2507 .chain = arm_tpiu_deprecated_command_handlers,
2508 },
2509 /* END_DEPRECATED_TPIU */
2510 {
2511 .name = "cortex_m",
2512 .mode = COMMAND_EXEC,
2513 .help = "Cortex-M command group",
2514 .usage = "",
2515 .chain = cortex_m_exec_command_handlers,
2516 },
2517 {
2518 .chain = rtt_target_command_handlers,
2519 },
2520 COMMAND_REGISTRATION_DONE
2521 };
2522
2523 struct target_type cortexm_target = {
2524 .name = "cortex_m",
2525
2526 .poll = cortex_m_poll,
2527 .arch_state = armv7m_arch_state,
2528
2529 .target_request_data = cortex_m_target_request_data,
2530
2531 .halt = cortex_m_halt,
2532 .resume = cortex_m_resume,
2533 .step = cortex_m_step,
2534
2535 .assert_reset = cortex_m_assert_reset,
2536 .deassert_reset = cortex_m_deassert_reset,
2537 .soft_reset_halt = cortex_m_soft_reset_halt,
2538
2539 .get_gdb_arch = arm_get_gdb_arch,
2540 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2541
2542 .read_memory = cortex_m_read_memory,
2543 .write_memory = cortex_m_write_memory,
2544 .checksum_memory = armv7m_checksum_memory,
2545 .blank_check_memory = armv7m_blank_check_memory,
2546
2547 .run_algorithm = armv7m_run_algorithm,
2548 .start_algorithm = armv7m_start_algorithm,
2549 .wait_algorithm = armv7m_wait_algorithm,
2550
2551 .add_breakpoint = cortex_m_add_breakpoint,
2552 .remove_breakpoint = cortex_m_remove_breakpoint,
2553 .add_watchpoint = cortex_m_add_watchpoint,
2554 .remove_watchpoint = cortex_m_remove_watchpoint,
2555 .hit_watchpoint = cortex_m_hit_watchpoint,
2556
2557 .commands = cortex_m_command_handlers,
2558 .target_create = cortex_m_target_create,
2559 .target_jim_configure = adiv5_jim_configure,
2560 .init_target = cortex_m_init_target,
2561 .examine = cortex_m_examine,
2562 .deinit_target = cortex_m_deinit_target,
2563
2564 .profiling = cortex_m_profiling,
2565 };
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