1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
55 * Returns the type of a break point required by address location
57 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
59 /* forward declarations */
60 static int cortex_m_store_core_reg_u32(struct target
*target
,
61 uint32_t num
, uint32_t value
);
62 static void cortex_m_dwt_free(struct target
*target
);
64 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
65 uint32_t *value
, int regnum
)
67 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
71 /* because the DCB_DCRDR is used for the emulated dcc channel
72 * we have to save/restore the DCB_DCRDR when used */
73 if (target
->dbg_msg_enabled
) {
74 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
75 if (retval
!= ERROR_OK
)
79 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
);
80 if (retval
!= ERROR_OK
)
83 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
84 if (retval
!= ERROR_OK
)
87 if (target
->dbg_msg_enabled
) {
88 /* restore DCB_DCRDR - this needs to be in a separate
89 * transaction otherwise the emulated DCC channel breaks */
90 if (retval
== ERROR_OK
)
91 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
97 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
98 uint32_t value
, int regnum
)
100 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
104 /* because the DCB_DCRDR is used for the emulated dcc channel
105 * we have to save/restore the DCB_DCRDR when used */
106 if (target
->dbg_msg_enabled
) {
107 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
108 if (retval
!= ERROR_OK
)
112 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
113 if (retval
!= ERROR_OK
)
116 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
117 if (retval
!= ERROR_OK
)
120 if (target
->dbg_msg_enabled
) {
121 /* restore DCB_DCRDR - this needs to be in a seperate
122 * transaction otherwise the emulated DCC channel breaks */
123 if (retval
== ERROR_OK
)
124 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
130 static int cortex_m_write_debug_halt_mask(struct target
*target
,
131 uint32_t mask_on
, uint32_t mask_off
)
133 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
134 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
136 /* mask off status bits */
137 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
138 /* create new register mask */
139 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
141 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
144 static int cortex_m_clear_halt(struct target
*target
)
146 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
147 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
150 /* clear step if any */
151 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
153 /* Read Debug Fault Status Register */
154 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
155 if (retval
!= ERROR_OK
)
158 /* Clear Debug Fault Status */
159 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
160 if (retval
!= ERROR_OK
)
162 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
167 static int cortex_m_single_step_core(struct target
*target
)
169 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
170 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
174 /* backup dhcsr reg */
175 dhcsr_save
= cortex_m
->dcb_dhcsr
;
177 /* Mask interrupts before clearing halt, if done already. This avoids
178 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
179 * HALT can put the core into an unknown state.
181 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
182 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
183 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
184 if (retval
!= ERROR_OK
)
187 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
188 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
189 if (retval
!= ERROR_OK
)
193 /* restore dhcsr reg */
194 cortex_m
->dcb_dhcsr
= dhcsr_save
;
195 cortex_m_clear_halt(target
);
200 static int cortex_m_enable_fpb(struct target
*target
)
202 int retval
= target_write_u32(target
, FP_CTRL
, 3);
203 if (retval
!= ERROR_OK
)
206 /* check the fpb is actually enabled */
208 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
209 if (retval
!= ERROR_OK
)
218 static int cortex_m_endreset_event(struct target
*target
)
223 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
224 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
225 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
226 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
227 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
231 if (retval
!= ERROR_OK
)
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
235 /* this register is used for emulated dcc channel */
236 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
237 if (retval
!= ERROR_OK
)
240 /* Enable debug requests */
241 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
242 if (retval
!= ERROR_OK
)
244 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
245 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
246 if (retval
!= ERROR_OK
)
250 /* clear any interrupt masking */
251 cortex_m_write_debug_halt_mask(target
, 0, C_MASKINTS
);
253 /* Enable features controlled by ITM and DWT blocks, and catch only
254 * the vectors we were told to pay attention to.
256 * Target firmware is responsible for all fault handling policy
257 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
258 * or manual updates to the NVIC SHCSR and CCR registers.
260 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
261 if (retval
!= ERROR_OK
)
264 /* Paranoia: evidently some (early?) chips don't preserve all the
265 * debug state (including FBP, DWT, etc) across reset...
269 retval
= cortex_m_enable_fpb(target
);
270 if (retval
!= ERROR_OK
) {
271 LOG_ERROR("Failed to enable the FPB");
275 cortex_m
->fpb_enabled
= 1;
277 /* Restore FPB registers */
278 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
279 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
280 if (retval
!= ERROR_OK
)
284 /* Restore DWT registers */
285 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
286 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
288 if (retval
!= ERROR_OK
)
290 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
292 if (retval
!= ERROR_OK
)
294 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
295 dwt_list
[i
].function
);
296 if (retval
!= ERROR_OK
)
299 retval
= dap_run(swjdp
);
300 if (retval
!= ERROR_OK
)
303 register_cache_invalidate(armv7m
->arm
.core_cache
);
305 /* make sure we have latest dhcsr flags */
306 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
311 static int cortex_m_examine_debug_reason(struct target
*target
)
313 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
315 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
316 * only check the debug reason if we don't know it already */
318 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
319 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
320 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
321 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
322 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
323 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
324 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
325 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
326 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
327 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
328 else /* EXTERNAL, HALTED */
329 target
->debug_reason
= DBG_REASON_UNDEFINED
;
335 static int cortex_m_examine_exception_reason(struct target
*target
)
337 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
338 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
339 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
342 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
343 if (retval
!= ERROR_OK
)
345 switch (armv7m
->exception_number
) {
348 case 3: /* Hard Fault */
349 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
350 if (retval
!= ERROR_OK
)
352 if (except_sr
& 0x40000000) {
353 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
354 if (retval
!= ERROR_OK
)
358 case 4: /* Memory Management */
359 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
360 if (retval
!= ERROR_OK
)
362 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
363 if (retval
!= ERROR_OK
)
366 case 5: /* Bus Fault */
367 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
368 if (retval
!= ERROR_OK
)
370 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
371 if (retval
!= ERROR_OK
)
374 case 6: /* Usage Fault */
375 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
376 if (retval
!= ERROR_OK
)
379 case 11: /* SVCall */
381 case 12: /* Debug Monitor */
382 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
383 if (retval
!= ERROR_OK
)
386 case 14: /* PendSV */
388 case 15: /* SysTick */
394 retval
= dap_run(swjdp
);
395 if (retval
== ERROR_OK
)
396 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
397 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
398 armv7m_exception_string(armv7m
->exception_number
),
399 shcsr
, except_sr
, cfsr
, except_ar
);
403 static int cortex_m_debug_entry(struct target
*target
)
408 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
409 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
410 struct arm
*arm
= &armv7m
->arm
;
415 cortex_m_clear_halt(target
);
416 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
417 if (retval
!= ERROR_OK
)
420 retval
= armv7m
->examine_debug_reason(target
);
421 if (retval
!= ERROR_OK
)
424 /* Examine target state and mode
425 * First load register accessible through core debug port */
426 int num_regs
= arm
->core_cache
->num_regs
;
428 for (i
= 0; i
< num_regs
; i
++) {
429 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
431 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
435 xPSR
= buf_get_u32(r
->value
, 0, 32);
437 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
440 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
443 /* Are we in an exception handler */
445 armv7m
->exception_number
= (xPSR
& 0x1FF);
447 arm
->core_mode
= ARM_MODE_HANDLER
;
448 arm
->map
= armv7m_msp_reg_map
;
450 unsigned control
= buf_get_u32(arm
->core_cache
451 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
453 /* is this thread privileged? */
454 arm
->core_mode
= control
& 1
455 ? ARM_MODE_USER_THREAD
458 /* which stack is it using? */
460 arm
->map
= armv7m_psp_reg_map
;
462 arm
->map
= armv7m_msp_reg_map
;
464 armv7m
->exception_number
= 0;
467 if (armv7m
->exception_number
)
468 cortex_m_examine_exception_reason(target
);
470 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
471 arm_mode_name(arm
->core_mode
),
472 buf_get_u32(arm
->pc
->value
, 0, 32),
473 target_state_name(target
));
475 if (armv7m
->post_debug_entry
) {
476 retval
= armv7m
->post_debug_entry(target
);
477 if (retval
!= ERROR_OK
)
484 static int cortex_m_poll(struct target
*target
)
486 int detected_failure
= ERROR_OK
;
487 int retval
= ERROR_OK
;
488 enum target_state prev_target_state
= target
->state
;
489 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
490 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
492 /* Read from Debug Halting Control and Status Register */
493 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
494 if (retval
!= ERROR_OK
) {
495 target
->state
= TARGET_UNKNOWN
;
499 /* Recover from lockup. See ARMv7-M architecture spec,
500 * section B1.5.15 "Unrecoverable exception cases".
502 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
503 LOG_ERROR("%s -- clearing lockup after double fault",
504 target_name(target
));
505 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
506 target
->debug_reason
= DBG_REASON_DBGRQ
;
508 /* We have to execute the rest (the "finally" equivalent, but
509 * still throw this exception again).
511 detected_failure
= ERROR_FAIL
;
513 /* refresh status bits */
514 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
515 if (retval
!= ERROR_OK
)
519 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
520 target
->state
= TARGET_RESET
;
524 if (target
->state
== TARGET_RESET
) {
525 /* Cannot switch context while running so endreset is
526 * called with target->state == TARGET_RESET
528 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
529 cortex_m
->dcb_dhcsr
);
530 retval
= cortex_m_endreset_event(target
);
531 if (retval
!= ERROR_OK
) {
532 target
->state
= TARGET_UNKNOWN
;
535 target
->state
= TARGET_RUNNING
;
536 prev_target_state
= TARGET_RUNNING
;
539 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
540 target
->state
= TARGET_HALTED
;
542 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
543 retval
= cortex_m_debug_entry(target
);
544 if (retval
!= ERROR_OK
)
547 if (arm_semihosting(target
, &retval
) != 0)
550 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
552 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
554 retval
= cortex_m_debug_entry(target
);
555 if (retval
!= ERROR_OK
)
558 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
562 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
563 * How best to model low power modes?
566 if (target
->state
== TARGET_UNKNOWN
) {
567 /* check if processor is retiring instructions */
568 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
569 target
->state
= TARGET_RUNNING
;
574 /* Did we detect a failure condition that we cleared? */
575 if (detected_failure
!= ERROR_OK
)
576 retval
= detected_failure
;
580 static int cortex_m_halt(struct target
*target
)
582 LOG_DEBUG("target->state: %s",
583 target_state_name(target
));
585 if (target
->state
== TARGET_HALTED
) {
586 LOG_DEBUG("target was already halted");
590 if (target
->state
== TARGET_UNKNOWN
)
591 LOG_WARNING("target was in unknown state when halt was requested");
593 if (target
->state
== TARGET_RESET
) {
594 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
595 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
596 return ERROR_TARGET_FAILURE
;
598 /* we came here in a reset_halt or reset_init sequence
599 * debug entry was already prepared in cortex_m3_assert_reset()
601 target
->debug_reason
= DBG_REASON_DBGRQ
;
607 /* Write to Debug Halting Control and Status Register */
608 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
610 target
->debug_reason
= DBG_REASON_DBGRQ
;
615 static int cortex_m_soft_reset_halt(struct target
*target
)
617 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
618 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
619 uint32_t dcb_dhcsr
= 0;
620 int retval
, timeout
= 0;
622 /* soft_reset_halt is deprecated on cortex_m as the same functionality
623 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
624 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
625 * core, not the peripherals */
626 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
628 /* Enter debug state on reset; restore DEMCR in endreset_event() */
629 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
630 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
631 if (retval
!= ERROR_OK
)
634 /* Request a core-only reset */
635 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
636 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
637 if (retval
!= ERROR_OK
)
639 target
->state
= TARGET_RESET
;
641 /* registers are now invalid */
642 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
644 while (timeout
< 100) {
645 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
646 if (retval
== ERROR_OK
) {
647 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
648 &cortex_m
->nvic_dfsr
);
649 if (retval
!= ERROR_OK
)
651 if ((dcb_dhcsr
& S_HALT
)
652 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
653 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
655 (unsigned) dcb_dhcsr
,
656 (unsigned) cortex_m
->nvic_dfsr
);
657 cortex_m_poll(target
);
658 /* FIXME restore user's vector catch config */
661 LOG_DEBUG("waiting for system reset-halt, "
662 "DHCSR 0x%08x, %d ms",
663 (unsigned) dcb_dhcsr
, timeout
);
672 void cortex_m_enable_breakpoints(struct target
*target
)
674 struct breakpoint
*breakpoint
= target
->breakpoints
;
676 /* set any pending breakpoints */
678 if (!breakpoint
->set
)
679 cortex_m_set_breakpoint(target
, breakpoint
);
680 breakpoint
= breakpoint
->next
;
684 static int cortex_m_resume(struct target
*target
, int current
,
685 uint32_t address
, int handle_breakpoints
, int debug_execution
)
687 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
688 struct breakpoint
*breakpoint
= NULL
;
692 if (target
->state
!= TARGET_HALTED
) {
693 LOG_WARNING("target not halted");
694 return ERROR_TARGET_NOT_HALTED
;
697 if (!debug_execution
) {
698 target_free_all_working_areas(target
);
699 cortex_m_enable_breakpoints(target
);
700 cortex_m_enable_watchpoints(target
);
703 if (debug_execution
) {
704 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
706 /* Disable interrupts */
707 /* We disable interrupts in the PRIMASK register instead of
708 * masking with C_MASKINTS. This is probably the same issue
709 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
710 * in parallel with disabled interrupts can cause local faults
713 * REVISIT this clearly breaks non-debug execution, since the
714 * PRIMASK register state isn't saved/restored... workaround
715 * by never resuming app code after debug execution.
717 buf_set_u32(r
->value
, 0, 1, 1);
721 /* Make sure we are in Thumb mode */
722 r
= armv7m
->arm
.cpsr
;
723 buf_set_u32(r
->value
, 24, 1, 1);
728 /* current = 1: continue on current pc, otherwise continue at <address> */
731 buf_set_u32(r
->value
, 0, 32, address
);
736 /* if we halted last time due to a bkpt instruction
737 * then we have to manually step over it, otherwise
738 * the core will break again */
740 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
742 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
744 resume_pc
= buf_get_u32(r
->value
, 0, 32);
746 armv7m_restore_context(target
);
748 /* the front-end may request us not to handle breakpoints */
749 if (handle_breakpoints
) {
750 /* Single step past breakpoint at current address */
751 breakpoint
= breakpoint_find(target
, resume_pc
);
753 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %" PRIu32
")",
755 breakpoint
->unique_id
);
756 cortex_m_unset_breakpoint(target
, breakpoint
);
757 cortex_m_single_step_core(target
);
758 cortex_m_set_breakpoint(target
, breakpoint
);
763 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
765 target
->debug_reason
= DBG_REASON_NOTHALTED
;
767 /* registers are now invalid */
768 register_cache_invalidate(armv7m
->arm
.core_cache
);
770 if (!debug_execution
) {
771 target
->state
= TARGET_RUNNING
;
772 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
773 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
775 target
->state
= TARGET_DEBUG_RUNNING
;
776 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
777 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
783 /* int irqstepcount = 0; */
784 static int cortex_m_step(struct target
*target
, int current
,
785 uint32_t address
, int handle_breakpoints
)
787 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
788 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
789 struct breakpoint
*breakpoint
= NULL
;
790 struct reg
*pc
= armv7m
->arm
.pc
;
791 bool bkpt_inst_found
= false;
793 bool isr_timed_out
= false;
795 if (target
->state
!= TARGET_HALTED
) {
796 LOG_WARNING("target not halted");
797 return ERROR_TARGET_NOT_HALTED
;
800 /* current = 1: continue on current pc, otherwise continue at <address> */
802 buf_set_u32(pc
->value
, 0, 32, address
);
804 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
806 /* the front-end may request us not to handle breakpoints */
807 if (handle_breakpoints
) {
808 breakpoint
= breakpoint_find(target
, pc_value
);
810 cortex_m_unset_breakpoint(target
, breakpoint
);
813 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
815 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
817 armv7m_restore_context(target
);
819 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
821 /* if no bkpt instruction is found at pc then we can perform
822 * a normal step, otherwise we have to manually step over the bkpt
823 * instruction - as such simulate a step */
824 if (bkpt_inst_found
== false) {
825 /* Automatic ISR masking mode off: Just step over the next instruction */
826 if ((cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
))
827 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
829 /* Process interrupts during stepping in a way they don't interfere
834 * Set a temporary break point at the current pc and let the core run
835 * with interrupts enabled. Pending interrupts get served and we run
836 * into the breakpoint again afterwards. Then we step over the next
837 * instruction with interrupts disabled.
839 * If the pending interrupts don't complete within time, we leave the
840 * core running. This may happen if the interrupts trigger faster
841 * than the core can process them or the handler doesn't return.
843 * If no more breakpoints are available we simply do a step with
844 * interrupts enabled.
850 * If a break point is already set on the lower half word then a break point on
851 * the upper half word will not break again when the core is restarted. So we
852 * just step over the instruction with interrupts disabled.
854 * The documentation has no information about this, it was found by observation
855 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
856 * suffer from this problem.
858 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
859 * address has it always cleared. The former is done to indicate thumb mode
863 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
864 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
865 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
866 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
867 /* Re-enable interrupts */
868 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
872 /* Set a temporary break point */
874 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
876 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
877 bool tmp_bp_set
= (retval
== ERROR_OK
);
879 /* No more breakpoints left, just do a step */
881 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
884 LOG_DEBUG("Starting core to serve pending interrupts");
885 int64_t t_start
= timeval_ms();
886 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
888 /* Wait for pending handlers to complete or timeout */
890 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
892 &cortex_m
->dcb_dhcsr
);
893 if (retval
!= ERROR_OK
) {
894 target
->state
= TARGET_UNKNOWN
;
897 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
898 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
900 /* only remove breakpoint if we created it */
902 cortex_m_unset_breakpoint(target
, breakpoint
);
904 /* Remove the temporary breakpoint */
905 breakpoint_remove(target
, pc_value
);
909 LOG_DEBUG("Interrupt handlers didn't complete within time, "
910 "leaving target running");
912 /* Step over next instruction with interrupts disabled */
913 cortex_m_write_debug_halt_mask(target
,
916 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
917 /* Re-enable interrupts */
918 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
925 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
926 if (retval
!= ERROR_OK
)
929 /* registers are now invalid */
930 register_cache_invalidate(armv7m
->arm
.core_cache
);
933 cortex_m_set_breakpoint(target
, breakpoint
);
936 /* Leave the core running. The user has to stop execution manually. */
937 target
->debug_reason
= DBG_REASON_NOTHALTED
;
938 target
->state
= TARGET_RUNNING
;
942 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
943 " nvic_icsr = 0x%" PRIx32
,
944 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
946 retval
= cortex_m_debug_entry(target
);
947 if (retval
!= ERROR_OK
)
949 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
951 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
952 " nvic_icsr = 0x%" PRIx32
,
953 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
958 static int cortex_m_assert_reset(struct target
*target
)
960 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
961 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
962 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
964 LOG_DEBUG("target->state: %s",
965 target_state_name(target
));
967 enum reset_types jtag_reset_config
= jtag_get_reset_config();
969 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
970 /* allow scripts to override the reset event */
972 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
973 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
974 target
->state
= TARGET_RESET
;
979 /* some cores support connecting while srst is asserted
980 * use that mode is it has been configured */
982 bool srst_asserted
= false;
984 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
985 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
986 adapter_assert_reset();
987 srst_asserted
= true;
990 /* Enable debug requests */
992 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
993 /* Store important errors instead of failing and proceed to reset assert */
995 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
996 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
998 /* If the processor is sleeping in a WFI or WFE instruction, the
999 * C_HALT bit must be asserted to regain control */
1000 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1001 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1003 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1004 /* Ignore less important errors */
1006 if (!target
->reset_halt
) {
1007 /* Set/Clear C_MASKINTS in a separate operation */
1008 if (cortex_m
->dcb_dhcsr
& C_MASKINTS
)
1009 mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
1010 DBGKEY
| C_DEBUGEN
| C_HALT
);
1012 /* clear any debug flags before resuming */
1013 cortex_m_clear_halt(target
);
1015 /* clear C_HALT in dhcsr reg */
1016 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1018 /* Halt in debug on reset; endreset_event() restores DEMCR.
1020 * REVISIT catching BUSERR presumably helps to defend against
1021 * bad vector table entries. Should this include MMERR or
1025 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1026 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1027 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1028 LOG_INFO("AP write error, reset will not halt");
1031 if (jtag_reset_config
& RESET_HAS_SRST
) {
1032 /* default to asserting srst */
1034 adapter_assert_reset();
1036 /* srst is asserted, ignore AP access errors */
1039 /* Use a standard Cortex-M3 software reset mechanism.
1040 * We default to using VECRESET as it is supported on all current cores.
1041 * This has the disadvantage of not resetting the peripherals, so a
1042 * reset-init event handler is needed to perform any peripheral resets.
1044 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1045 ? "SYSRESETREQ" : "VECTRESET");
1047 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1048 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1049 "handler to reset any peripherals or configure hardware srst support.");
1053 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1054 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1055 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1056 if (retval3
!= ERROR_OK
)
1057 LOG_DEBUG("Ignoring AP write error right after reset");
1059 retval3
= dap_dp_init(armv7m
->debug_ap
->dap
);
1060 if (retval3
!= ERROR_OK
)
1061 LOG_ERROR("DP initialisation failed");
1064 /* I do not know why this is necessary, but it
1065 * fixes strange effects (step/resume cause NMI
1066 * after reset) on LM3S6918 -- Michael Schwingen
1069 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1073 target
->state
= TARGET_RESET
;
1074 jtag_add_sleep(50000);
1076 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1078 /* now return stored error code if any */
1079 if (retval
!= ERROR_OK
)
1082 if (target
->reset_halt
) {
1083 retval
= target_halt(target
);
1084 if (retval
!= ERROR_OK
)
1091 static int cortex_m_deassert_reset(struct target
*target
)
1093 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1095 LOG_DEBUG("target->state: %s",
1096 target_state_name(target
));
1098 /* deassert reset lines */
1099 adapter_deassert_reset();
1101 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1103 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1104 !(jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1105 int retval
= dap_dp_init(armv7m
->debug_ap
->dap
);
1106 if (retval
!= ERROR_OK
) {
1107 LOG_ERROR("DP initialisation failed");
1115 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1119 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1120 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1122 if (breakpoint
->set
) {
1123 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1127 if (cortex_m
->auto_bp_type
)
1128 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1130 if (breakpoint
->type
== BKPT_HARD
) {
1131 uint32_t fpcr_value
;
1132 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1134 if (fp_num
>= cortex_m
->fp_num_code
) {
1135 LOG_ERROR("Can not find free FPB Comparator!");
1138 breakpoint
->set
= fp_num
+ 1;
1139 fpcr_value
= breakpoint
->address
| 1;
1140 if (cortex_m
->fp_rev
== 0) {
1142 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1143 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1144 } else if (cortex_m
->fp_rev
> 1) {
1145 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1148 comparator_list
[fp_num
].used
= 1;
1149 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1150 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1151 comparator_list
[fp_num
].fpcr_value
);
1152 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1154 comparator_list
[fp_num
].fpcr_value
);
1155 if (!cortex_m
->fpb_enabled
) {
1156 LOG_DEBUG("FPB wasn't enabled, do it now");
1157 retval
= cortex_m_enable_fpb(target
);
1158 if (retval
!= ERROR_OK
) {
1159 LOG_ERROR("Failed to enable the FPB");
1163 cortex_m
->fpb_enabled
= 1;
1165 } else if (breakpoint
->type
== BKPT_SOFT
) {
1168 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1169 * semihosting; don't use that. Otherwise the BKPT
1170 * parameter is arbitrary.
1172 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1173 retval
= target_read_memory(target
,
1174 breakpoint
->address
& 0xFFFFFFFE,
1175 breakpoint
->length
, 1,
1176 breakpoint
->orig_instr
);
1177 if (retval
!= ERROR_OK
)
1179 retval
= target_write_memory(target
,
1180 breakpoint
->address
& 0xFFFFFFFE,
1181 breakpoint
->length
, 1,
1183 if (retval
!= ERROR_OK
)
1185 breakpoint
->set
= true;
1188 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1189 breakpoint
->unique_id
,
1190 (int)(breakpoint
->type
),
1191 breakpoint
->address
,
1198 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1201 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1202 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1204 if (!breakpoint
->set
) {
1205 LOG_WARNING("breakpoint not set");
1209 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1210 breakpoint
->unique_id
,
1211 (int)(breakpoint
->type
),
1212 breakpoint
->address
,
1216 if (breakpoint
->type
== BKPT_HARD
) {
1217 int fp_num
= breakpoint
->set
- 1;
1218 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1219 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1222 comparator_list
[fp_num
].used
= 0;
1223 comparator_list
[fp_num
].fpcr_value
= 0;
1224 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1225 comparator_list
[fp_num
].fpcr_value
);
1227 /* restore original instruction (kept in target endianness) */
1228 if (breakpoint
->length
== 4) {
1229 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1230 breakpoint
->orig_instr
);
1231 if (retval
!= ERROR_OK
)
1234 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1235 breakpoint
->orig_instr
);
1236 if (retval
!= ERROR_OK
)
1240 breakpoint
->set
= false;
1245 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1247 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1249 if (cortex_m
->auto_bp_type
)
1250 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1252 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1253 if (breakpoint
->type
== BKPT_HARD
) {
1254 LOG_INFO("flash patch comparator requested outside code memory region");
1255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1258 if (breakpoint
->type
== BKPT_SOFT
) {
1259 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1260 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1264 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m
->fp_code_available
< 1)) {
1265 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1266 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1269 if (breakpoint
->length
== 3) {
1270 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1271 breakpoint
->length
= 2;
1274 if ((breakpoint
->length
!= 2)) {
1275 LOG_INFO("only breakpoints of two bytes length supported");
1276 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1279 if (breakpoint
->type
== BKPT_HARD
)
1280 cortex_m
->fp_code_available
--;
1282 return cortex_m_set_breakpoint(target
, breakpoint
);
1285 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1287 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1289 /* REVISIT why check? FBP can be updated with core running ... */
1290 if (target
->state
!= TARGET_HALTED
) {
1291 LOG_WARNING("target not halted");
1292 return ERROR_TARGET_NOT_HALTED
;
1295 if (cortex_m
->auto_bp_type
)
1296 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1298 if (breakpoint
->set
)
1299 cortex_m_unset_breakpoint(target
, breakpoint
);
1301 if (breakpoint
->type
== BKPT_HARD
)
1302 cortex_m
->fp_code_available
++;
1307 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1310 uint32_t mask
, temp
;
1311 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1313 /* watchpoint params were validated earlier */
1315 temp
= watchpoint
->length
;
1322 /* REVISIT Don't fully trust these "not used" records ... users
1323 * may set up breakpoints by hand, e.g. dual-address data value
1324 * watchpoint using comparator #1; comparator #0 matching cycle
1325 * count; send data trace info through ITM and TPIU; etc
1327 struct cortex_m_dwt_comparator
*comparator
;
1329 for (comparator
= cortex_m
->dwt_comparator_list
;
1330 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1331 comparator
++, dwt_num
++)
1333 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1334 LOG_ERROR("Can not find free DWT Comparator");
1337 comparator
->used
= 1;
1338 watchpoint
->set
= dwt_num
+ 1;
1340 comparator
->comp
= watchpoint
->address
;
1341 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1344 comparator
->mask
= mask
;
1345 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1348 switch (watchpoint
->rw
) {
1350 comparator
->function
= 5;
1353 comparator
->function
= 6;
1356 comparator
->function
= 7;
1359 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1360 comparator
->function
);
1362 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1363 watchpoint
->unique_id
, dwt_num
,
1364 (unsigned) comparator
->comp
,
1365 (unsigned) comparator
->mask
,
1366 (unsigned) comparator
->function
);
1370 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1372 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1373 struct cortex_m_dwt_comparator
*comparator
;
1376 if (!watchpoint
->set
) {
1377 LOG_WARNING("watchpoint (wpid: %d) not set",
1378 watchpoint
->unique_id
);
1382 dwt_num
= watchpoint
->set
- 1;
1384 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1385 watchpoint
->unique_id
, dwt_num
,
1386 (unsigned) watchpoint
->address
);
1388 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1389 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1393 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1394 comparator
->used
= 0;
1395 comparator
->function
= 0;
1396 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1397 comparator
->function
);
1399 watchpoint
->set
= false;
1404 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1406 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1408 if (cortex_m
->dwt_comp_available
< 1) {
1409 LOG_DEBUG("no comparators?");
1410 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1413 /* hardware doesn't support data value masking */
1414 if (watchpoint
->mask
!= ~(uint32_t)0) {
1415 LOG_DEBUG("watchpoint value masks not supported");
1416 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1419 /* hardware allows address masks of up to 32K */
1422 for (mask
= 0; mask
< 16; mask
++) {
1423 if ((1u << mask
) == watchpoint
->length
)
1427 LOG_DEBUG("unsupported watchpoint length");
1428 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1430 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1431 LOG_DEBUG("watchpoint address is unaligned");
1432 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1435 /* Caller doesn't seem to be able to describe watching for data
1436 * values of zero; that flags "no value".
1438 * REVISIT This DWT may well be able to watch for specific data
1439 * values. Requires comparator #1 to set DATAVMATCH and match
1440 * the data, and another comparator (DATAVADDR0) matching addr.
1442 if (watchpoint
->value
) {
1443 LOG_DEBUG("data value watchpoint not YET supported");
1444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1447 cortex_m
->dwt_comp_available
--;
1448 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1453 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1455 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1457 /* REVISIT why check? DWT can be updated with core running ... */
1458 if (target
->state
!= TARGET_HALTED
) {
1459 LOG_WARNING("target not halted");
1460 return ERROR_TARGET_NOT_HALTED
;
1463 if (watchpoint
->set
)
1464 cortex_m_unset_watchpoint(target
, watchpoint
);
1466 cortex_m
->dwt_comp_available
++;
1467 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1472 void cortex_m_enable_watchpoints(struct target
*target
)
1474 struct watchpoint
*watchpoint
= target
->watchpoints
;
1476 /* set any pending watchpoints */
1477 while (watchpoint
) {
1478 if (!watchpoint
->set
)
1479 cortex_m_set_watchpoint(target
, watchpoint
);
1480 watchpoint
= watchpoint
->next
;
1484 static int cortex_m_load_core_reg_u32(struct target
*target
,
1485 uint32_t num
, uint32_t *value
)
1489 /* NOTE: we "know" here that the register identifiers used
1490 * in the v7m header match the Cortex-M3 Debug Core Register
1491 * Selector values for R0..R15, xPSR, MSP, and PSP.
1495 /* read a normal core register */
1496 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1498 if (retval
!= ERROR_OK
) {
1499 LOG_ERROR("JTAG failure %i", retval
);
1500 return ERROR_JTAG_DEVICE_ERROR
;
1502 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1506 /* Floating-point Status and Registers */
1507 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1508 if (retval
!= ERROR_OK
)
1510 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1511 if (retval
!= ERROR_OK
)
1513 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1516 case ARMV7M_S0
... ARMV7M_S31
:
1517 /* Floating-point Status and Registers */
1518 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1519 if (retval
!= ERROR_OK
)
1521 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1522 if (retval
!= ERROR_OK
)
1524 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1525 (int)(num
- ARMV7M_S0
), *value
);
1528 case ARMV7M_PRIMASK
:
1529 case ARMV7M_BASEPRI
:
1530 case ARMV7M_FAULTMASK
:
1531 case ARMV7M_CONTROL
:
1532 /* Cortex-M3 packages these four registers as bitfields
1533 * in one Debug Core register. So say r0 and r2 docs;
1534 * it was removed from r1 docs, but still works.
1536 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1539 case ARMV7M_PRIMASK
:
1540 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1543 case ARMV7M_BASEPRI
:
1544 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1547 case ARMV7M_FAULTMASK
:
1548 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1551 case ARMV7M_CONTROL
:
1552 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1556 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1560 return ERROR_COMMAND_SYNTAX_ERROR
;
1566 static int cortex_m_store_core_reg_u32(struct target
*target
,
1567 uint32_t num
, uint32_t value
)
1571 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1573 /* NOTE: we "know" here that the register identifiers used
1574 * in the v7m header match the Cortex-M3 Debug Core Register
1575 * Selector values for R0..R15, xPSR, MSP, and PSP.
1579 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1580 if (retval
!= ERROR_OK
) {
1583 LOG_ERROR("JTAG failure");
1584 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1585 r
->dirty
= r
->valid
;
1586 return ERROR_JTAG_DEVICE_ERROR
;
1588 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1592 /* Floating-point Status and Registers */
1593 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1594 if (retval
!= ERROR_OK
)
1596 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1597 if (retval
!= ERROR_OK
)
1599 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1602 case ARMV7M_S0
... ARMV7M_S31
:
1603 /* Floating-point Status and Registers */
1604 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1605 if (retval
!= ERROR_OK
)
1607 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1608 if (retval
!= ERROR_OK
)
1610 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1611 (int)(num
- ARMV7M_S0
), value
);
1614 case ARMV7M_PRIMASK
:
1615 case ARMV7M_BASEPRI
:
1616 case ARMV7M_FAULTMASK
:
1617 case ARMV7M_CONTROL
:
1618 /* Cortex-M3 packages these four registers as bitfields
1619 * in one Debug Core register. So say r0 and r2 docs;
1620 * it was removed from r1 docs, but still works.
1622 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1625 case ARMV7M_PRIMASK
:
1626 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1629 case ARMV7M_BASEPRI
:
1630 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1633 case ARMV7M_FAULTMASK
:
1634 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1637 case ARMV7M_CONTROL
:
1638 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1642 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1644 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1648 return ERROR_COMMAND_SYNTAX_ERROR
;
1654 static int cortex_m_read_memory(struct target
*target
, uint32_t address
,
1655 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1657 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1659 if (armv7m
->arm
.is_armv6m
) {
1660 /* armv6m does not handle unaligned memory access */
1661 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1662 return ERROR_TARGET_UNALIGNED_ACCESS
;
1665 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1668 static int cortex_m_write_memory(struct target
*target
, uint32_t address
,
1669 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1671 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1673 if (armv7m
->arm
.is_armv6m
) {
1674 /* armv6m does not handle unaligned memory access */
1675 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1676 return ERROR_TARGET_UNALIGNED_ACCESS
;
1679 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1682 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1683 struct target
*target
)
1685 armv7m_build_reg_cache(target
);
1689 void cortex_m_deinit_target(struct target
*target
)
1691 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1693 free(cortex_m
->fp_comparator_list
);
1695 cortex_m_dwt_free(target
);
1696 armv7m_free_reg_cache(target
);
1701 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1702 * on r/w if the core is not running, and clear on resume or reset ... or
1703 * at least, in a post_restore_context() method.
1706 struct dwt_reg_state
{
1707 struct target
*target
;
1709 uint8_t value
[4]; /* scratch/cache */
1712 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1714 struct dwt_reg_state
*state
= reg
->arch_info
;
1717 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1718 if (retval
!= ERROR_OK
)
1721 buf_set_u32(state
->value
, 0, 32, tmp
);
1725 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1727 struct dwt_reg_state
*state
= reg
->arch_info
;
1729 return target_write_u32(state
->target
, state
->addr
,
1730 buf_get_u32(buf
, 0, reg
->size
));
1739 static struct dwt_reg dwt_base_regs
[] = {
1740 { DWT_CTRL
, "dwt_ctrl", 32, },
1741 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1742 * increments while the core is asleep.
1744 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1745 /* plus some 8 bit counters, useful for profiling with TPIU */
1748 static struct dwt_reg dwt_comp
[] = {
1749 #define DWT_COMPARATOR(i) \
1750 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1751 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1752 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1757 #undef DWT_COMPARATOR
1760 static const struct reg_arch_type dwt_reg_type
= {
1761 .get
= cortex_m_dwt_get_reg
,
1762 .set
= cortex_m_dwt_set_reg
,
1765 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1767 struct dwt_reg_state
*state
;
1769 state
= calloc(1, sizeof *state
);
1772 state
->addr
= d
->addr
;
1777 r
->value
= state
->value
;
1778 r
->arch_info
= state
;
1779 r
->type
= &dwt_reg_type
;
1782 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1785 struct reg_cache
*cache
;
1786 struct cortex_m_dwt_comparator
*comparator
;
1789 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1791 LOG_DEBUG("no DWT");
1795 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1796 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
1797 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
1798 sizeof(struct cortex_m_dwt_comparator
));
1799 if (!cm
->dwt_comparator_list
) {
1801 cm
->dwt_num_comp
= 0;
1802 LOG_ERROR("out of mem");
1806 cache
= calloc(1, sizeof *cache
);
1809 free(cm
->dwt_comparator_list
);
1812 cache
->name
= "Cortex-M DWT registers";
1813 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
1814 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1815 if (!cache
->reg_list
) {
1820 for (reg
= 0; reg
< 2; reg
++)
1821 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1822 dwt_base_regs
+ reg
);
1824 comparator
= cm
->dwt_comparator_list
;
1825 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
1828 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1829 for (j
= 0; j
< 3; j
++, reg
++)
1830 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1831 dwt_comp
+ 3 * i
+ j
);
1833 /* make sure we clear any watchpoints enabled on the target */
1834 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1837 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1838 cm
->dwt_cache
= cache
;
1840 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1841 dwtcr
, cm
->dwt_num_comp
,
1842 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1844 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1845 * implement single-address data value watchpoints ... so we
1846 * won't need to check it later, when asked to set one up.
1850 static void cortex_m_dwt_free(struct target
*target
)
1852 struct cortex_m_common
*cm
= target_to_cm(target
);
1853 struct reg_cache
*cache
= cm
->dwt_cache
;
1855 free(cm
->dwt_comparator_list
);
1856 cm
->dwt_comparator_list
= NULL
;
1857 cm
->dwt_num_comp
= 0;
1860 register_unlink_cache(&target
->reg_cache
, cache
);
1862 if (cache
->reg_list
) {
1863 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
1864 free(cache
->reg_list
[i
].arch_info
);
1865 free(cache
->reg_list
);
1869 cm
->dwt_cache
= NULL
;
1872 #define MVFR0 0xe000ef40
1873 #define MVFR1 0xe000ef44
1875 #define MVFR0_DEFAULT_M4 0x10110021
1876 #define MVFR1_DEFAULT_M4 0x11000011
1878 #define MVFR0_DEFAULT_M7_SP 0x10110021
1879 #define MVFR0_DEFAULT_M7_DP 0x10110221
1880 #define MVFR1_DEFAULT_M7_SP 0x11000011
1881 #define MVFR1_DEFAULT_M7_DP 0x12000011
1883 int cortex_m_examine(struct target
*target
)
1886 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1888 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1889 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
1890 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1892 /* stlink shares the examine handler but does not support
1894 if (!armv7m
->stlink
) {
1895 retval
= dap_dp_init(swjdp
);
1896 if (retval
!= ERROR_OK
) {
1897 LOG_ERROR("Could not initialize the debug port");
1901 /* Search for the MEM-AP */
1902 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7m
->debug_ap
);
1903 if (retval
!= ERROR_OK
) {
1904 LOG_ERROR("Could not find MEM-AP to control the core");
1908 /* Leave (only) generic DAP stuff for debugport_init(); */
1909 armv7m
->debug_ap
->memaccess_tck
= 8;
1911 retval
= mem_ap_init(armv7m
->debug_ap
);
1912 if (retval
!= ERROR_OK
)
1916 if (!target_was_examined(target
)) {
1917 target_set_examined(target
);
1919 /* Read from Device Identification Registers */
1920 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1921 if (retval
!= ERROR_OK
)
1925 i
= (cpuid
>> 4) & 0xf;
1927 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1928 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1931 rev
= (cpuid
>> 20) & 0xf;
1932 patch
= (cpuid
>> 0) & 0xf;
1933 if ((rev
== 0) && (patch
< 2))
1934 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
1936 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1939 target_read_u32(target
, MVFR0
, &mvfr0
);
1940 target_read_u32(target
, MVFR1
, &mvfr1
);
1942 /* test for floating point feature on Cortex-M4 */
1943 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1944 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1945 armv7m
->fp_feature
= FPv4_SP
;
1947 } else if (i
== 7) {
1948 target_read_u32(target
, MVFR0
, &mvfr0
);
1949 target_read_u32(target
, MVFR1
, &mvfr1
);
1951 /* test for floating point features on Cortex-M7 */
1952 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
1953 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
1954 armv7m
->fp_feature
= FPv5_SP
;
1955 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
1956 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
1957 armv7m
->fp_feature
= FPv5_DP
;
1959 } else if (i
== 0) {
1960 /* Cortex-M0 does not support unaligned memory access */
1961 armv7m
->arm
.is_armv6m
= true;
1964 if (armv7m
->fp_feature
== FP_NONE
&&
1965 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
1966 /* free unavailable FPU registers */
1969 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
1970 idx
< armv7m
->arm
.core_cache
->num_regs
;
1972 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
1973 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
1974 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
1976 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
1979 if (!armv7m
->stlink
) {
1980 if (i
== 3 || i
== 4)
1981 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
1982 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
1983 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
1985 /* Cortex-M7 has only 1024 bytes autoincrement range */
1986 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
1989 /* Configure trace modules */
1990 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
1991 if (retval
!= ERROR_OK
)
1994 if (armv7m
->trace_config
.config_type
!= DISABLED
) {
1995 armv7m_trace_tpiu_config(target
);
1996 armv7m_trace_itm_config(target
);
1999 /* NOTE: FPB and DWT are both optional. */
2002 target_read_u32(target
, FP_CTRL
, &fpcr
);
2003 cortex_m
->auto_bp_type
= 1;
2004 /* bits [14:12] and [7:4] */
2005 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2006 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2007 cortex_m
->fp_code_available
= cortex_m
->fp_num_code
;
2008 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2009 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2010 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2011 free(cortex_m
->fp_comparator_list
);
2012 cortex_m
->fp_comparator_list
= calloc(
2013 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2014 sizeof(struct cortex_m_fp_comparator
));
2015 cortex_m
->fpb_enabled
= fpcr
& 1;
2016 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2017 cortex_m
->fp_comparator_list
[i
].type
=
2018 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2019 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2021 /* make sure we clear any breakpoints enabled on the target */
2022 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2024 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2026 cortex_m
->fp_num_code
,
2027 cortex_m
->fp_num_lit
);
2030 cortex_m_dwt_free(target
);
2031 cortex_m_dwt_setup(cortex_m
, target
);
2033 /* These hardware breakpoints only work for code in flash! */
2034 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2035 target_name(target
),
2036 cortex_m
->fp_num_code
,
2037 cortex_m
->dwt_num_comp
);
2043 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2045 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2050 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2051 if (retval
!= ERROR_OK
)
2054 dcrdr
= target_buffer_get_u16(target
, buf
);
2055 *ctrl
= (uint8_t)dcrdr
;
2056 *value
= (uint8_t)(dcrdr
>> 8);
2058 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2060 /* write ack back to software dcc register
2061 * signify we have read data */
2062 if (dcrdr
& (1 << 0)) {
2063 target_buffer_set_u16(target
, buf
, 0);
2064 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2065 if (retval
!= ERROR_OK
)
2072 static int cortex_m_target_request_data(struct target
*target
,
2073 uint32_t size
, uint8_t *buffer
)
2079 for (i
= 0; i
< (size
* 4); i
++) {
2080 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2081 if (retval
!= ERROR_OK
)
2089 static int cortex_m_handle_target_request(void *priv
)
2091 struct target
*target
= priv
;
2092 if (!target_was_examined(target
))
2095 if (!target
->dbg_msg_enabled
)
2098 if (target
->state
== TARGET_RUNNING
) {
2103 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2104 if (retval
!= ERROR_OK
)
2107 /* check if we have data */
2108 if (ctrl
& (1 << 0)) {
2111 /* we assume target is quick enough */
2113 for (int i
= 1; i
<= 3; i
++) {
2114 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2115 if (retval
!= ERROR_OK
)
2117 request
|= ((uint32_t)data
<< (i
* 8));
2119 target_request(target
, request
);
2126 static int cortex_m_init_arch_info(struct target
*target
,
2127 struct cortex_m_common
*cortex_m
, struct jtag_tap
*tap
)
2129 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2131 armv7m_init_arch_info(target
, armv7m
);
2133 /* tap has no dap initialized */
2135 tap
->dap
= dap_init();
2137 /* Leave (only) generic DAP stuff for debugport_init() */
2138 tap
->dap
->tap
= tap
;
2141 /* default reset mode is to use srst if fitted
2142 * if not it will use CORTEX_M3_RESET_VECTRESET */
2143 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2145 armv7m
->arm
.dap
= tap
->dap
;
2147 /* register arch-specific functions */
2148 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2150 armv7m
->post_debug_entry
= NULL
;
2152 armv7m
->pre_restore_context
= NULL
;
2154 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2155 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2157 target_register_timer_callback(cortex_m_handle_target_request
, 1, 1, target
);
2162 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2164 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2166 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2167 cortex_m_init_arch_info(target
, cortex_m
, target
->tap
);
2172 /*--------------------------------------------------------------------------*/
2174 static int cortex_m_verify_pointer(struct command_context
*cmd_ctx
,
2175 struct cortex_m_common
*cm
)
2177 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2178 command_print(cmd_ctx
, "target is not a Cortex-M");
2179 return ERROR_TARGET_INVALID
;
2185 * Only stuff below this line should need to verify that its target
2186 * is a Cortex-M3. Everything else should have indirected through the
2187 * cortexm3_target structure, which is only used with CM3 targets.
2190 static const struct {
2194 { "hard_err", VC_HARDERR
, },
2195 { "int_err", VC_INTERR
, },
2196 { "bus_err", VC_BUSERR
, },
2197 { "state_err", VC_STATERR
, },
2198 { "chk_err", VC_CHKERR
, },
2199 { "nocp_err", VC_NOCPERR
, },
2200 { "mm_err", VC_MMERR
, },
2201 { "reset", VC_CORERESET
, },
2204 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2206 struct target
*target
= get_current_target(CMD_CTX
);
2207 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2208 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2212 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2213 if (retval
!= ERROR_OK
)
2216 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2217 if (retval
!= ERROR_OK
)
2223 if (CMD_ARGC
== 1) {
2224 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2225 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2226 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2227 | VC_MMERR
| VC_CORERESET
;
2229 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2232 while (CMD_ARGC
-- > 0) {
2234 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2235 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2237 catch |= vec_ids
[i
].mask
;
2240 if (i
== ARRAY_SIZE(vec_ids
)) {
2241 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2242 return ERROR_COMMAND_SYNTAX_ERROR
;
2246 /* For now, armv7m->demcr only stores vector catch flags. */
2247 armv7m
->demcr
= catch;
2252 /* write, but don't assume it stuck (why not??) */
2253 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2254 if (retval
!= ERROR_OK
)
2256 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2257 if (retval
!= ERROR_OK
)
2260 /* FIXME be sure to clear DEMCR on clean server shutdown.
2261 * Otherwise the vector catch hardware could fire when there's
2262 * no debugger hooked up, causing much confusion...
2266 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2267 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2268 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2274 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2276 struct target
*target
= get_current_target(CMD_CTX
);
2277 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2280 static const Jim_Nvp nvp_maskisr_modes
[] = {
2281 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2282 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2283 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2284 { .name
= NULL
, .value
= -1 },
2289 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2290 if (retval
!= ERROR_OK
)
2293 if (target
->state
!= TARGET_HALTED
) {
2294 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2299 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2300 if (n
->name
== NULL
)
2301 return ERROR_COMMAND_SYNTAX_ERROR
;
2302 cortex_m
->isrmasking_mode
= n
->value
;
2305 if (cortex_m
->isrmasking_mode
== CORTEX_M_ISRMASK_ON
)
2306 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2308 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2311 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2312 command_print(CMD_CTX
, "cortex_m interrupt mask %s", n
->name
);
2317 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2319 struct target
*target
= get_current_target(CMD_CTX
);
2320 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2324 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2325 if (retval
!= ERROR_OK
)
2329 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2330 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2331 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2332 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2335 switch (cortex_m
->soft_reset_config
) {
2336 case CORTEX_M_RESET_SYSRESETREQ
:
2337 reset_config
= "sysresetreq";
2340 case CORTEX_M_RESET_VECTRESET
:
2341 reset_config
= "vectreset";
2345 reset_config
= "unknown";
2349 command_print(CMD_CTX
, "cortex_m reset_config %s", reset_config
);
2354 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2357 .handler
= handle_cortex_m_mask_interrupts_command
,
2358 .mode
= COMMAND_EXEC
,
2359 .help
= "mask cortex_m interrupts",
2360 .usage
= "['auto'|'on'|'off']",
2363 .name
= "vector_catch",
2364 .handler
= handle_cortex_m_vector_catch_command
,
2365 .mode
= COMMAND_EXEC
,
2366 .help
= "configure hardware vectors to trigger debug entry",
2367 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2370 .name
= "reset_config",
2371 .handler
= handle_cortex_m_reset_config_command
,
2372 .mode
= COMMAND_ANY
,
2373 .help
= "configure software reset handling",
2374 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2376 COMMAND_REGISTRATION_DONE
2378 static const struct command_registration cortex_m_command_handlers
[] = {
2380 .chain
= armv7m_command_handlers
,
2383 .chain
= armv7m_trace_command_handlers
,
2387 .mode
= COMMAND_EXEC
,
2388 .help
= "Cortex-M command group",
2390 .chain
= cortex_m_exec_command_handlers
,
2392 COMMAND_REGISTRATION_DONE
2395 struct target_type cortexm_target
= {
2397 .deprecated_name
= "cortex_m3",
2399 .poll
= cortex_m_poll
,
2400 .arch_state
= armv7m_arch_state
,
2402 .target_request_data
= cortex_m_target_request_data
,
2404 .halt
= cortex_m_halt
,
2405 .resume
= cortex_m_resume
,
2406 .step
= cortex_m_step
,
2408 .assert_reset
= cortex_m_assert_reset
,
2409 .deassert_reset
= cortex_m_deassert_reset
,
2410 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2412 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2414 .read_memory
= cortex_m_read_memory
,
2415 .write_memory
= cortex_m_write_memory
,
2416 .checksum_memory
= armv7m_checksum_memory
,
2417 .blank_check_memory
= armv7m_blank_check_memory
,
2419 .run_algorithm
= armv7m_run_algorithm
,
2420 .start_algorithm
= armv7m_start_algorithm
,
2421 .wait_algorithm
= armv7m_wait_algorithm
,
2423 .add_breakpoint
= cortex_m_add_breakpoint
,
2424 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2425 .add_watchpoint
= cortex_m_add_watchpoint
,
2426 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2428 .commands
= cortex_m_command_handlers
,
2429 .target_create
= cortex_m_target_create
,
2430 .init_target
= cortex_m_init_target
,
2431 .examine
= cortex_m_examine
,
2432 .deinit_target
= cortex_m_deinit_target
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)