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arm_adi_v5: prevent possibly endless recursion in dap_dp_init()
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortex_m_load_core_reg_u32(struct target *target,
60 uint32_t regsel, uint32_t *value)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortex_m_store_core_reg_u32(struct target *target,
93 uint32_t regsel, uint32_t value)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a separate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_set_maskints(struct target *target, bool mask)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
143 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
144 else
145 return ERROR_OK;
146 }
147
148 static int cortex_m_set_maskints_for_halt(struct target *target)
149 {
150 struct cortex_m_common *cortex_m = target_to_cm(target);
151 switch (cortex_m->isrmasking_mode) {
152 case CORTEX_M_ISRMASK_AUTO:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target, false);
155
156 case CORTEX_M_ISRMASK_OFF:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target, false);
159
160 case CORTEX_M_ISRMASK_ON:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target, true);
163
164 case CORTEX_M_ISRMASK_STEPONLY:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
168 }
169 return ERROR_OK;
170 }
171
172 static int cortex_m_set_maskints_for_run(struct target *target)
173 {
174 switch (target_to_cm(target)->isrmasking_mode) {
175 case CORTEX_M_ISRMASK_AUTO:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target, false);
178
179 case CORTEX_M_ISRMASK_OFF:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target, false);
182
183 case CORTEX_M_ISRMASK_ON:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target, true);
186
187 case CORTEX_M_ISRMASK_STEPONLY:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target, false);
190 }
191 return ERROR_OK;
192 }
193
194 static int cortex_m_set_maskints_for_step(struct target *target)
195 {
196 switch (target_to_cm(target)->isrmasking_mode) {
197 case CORTEX_M_ISRMASK_AUTO:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target, true);
200
201 case CORTEX_M_ISRMASK_OFF:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target, false);
204
205 case CORTEX_M_ISRMASK_ON:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target, true);
208
209 case CORTEX_M_ISRMASK_STEPONLY:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target, true);
212 }
213 return ERROR_OK;
214 }
215
216 static int cortex_m_clear_halt(struct target *target)
217 {
218 struct cortex_m_common *cortex_m = target_to_cm(target);
219 struct armv7m_common *armv7m = &cortex_m->armv7m;
220 int retval;
221
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
224
225 /* Read Debug Fault Status Register */
226 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Clear Debug Fault Status */
231 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
232 if (retval != ERROR_OK)
233 return retval;
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
235
236 return ERROR_OK;
237 }
238
239 static int cortex_m_single_step_core(struct target *target)
240 {
241 struct cortex_m_common *cortex_m = target_to_cm(target);
242 struct armv7m_common *armv7m = &cortex_m->armv7m;
243 int retval;
244
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
248 */
249 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
250 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
251 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
252 if (retval != ERROR_OK)
253 return retval;
254 }
255 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
256 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
257 if (retval != ERROR_OK)
258 return retval;
259 LOG_DEBUG(" ");
260
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target);
263
264 return ERROR_OK;
265 }
266
267 static int cortex_m_enable_fpb(struct target *target)
268 {
269 int retval = target_write_u32(target, FP_CTRL, 3);
270 if (retval != ERROR_OK)
271 return retval;
272
273 /* check the fpb is actually enabled */
274 uint32_t fpctrl;
275 retval = target_read_u32(target, FP_CTRL, &fpctrl);
276 if (retval != ERROR_OK)
277 return retval;
278
279 if (fpctrl & 1)
280 return ERROR_OK;
281
282 return ERROR_FAIL;
283 }
284
285 static int cortex_m_endreset_event(struct target *target)
286 {
287 int i;
288 int retval;
289 uint32_t dcb_demcr;
290 struct cortex_m_common *cortex_m = target_to_cm(target);
291 struct armv7m_common *armv7m = &cortex_m->armv7m;
292 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
293 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
294 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
295
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
298 if (retval != ERROR_OK)
299 return retval;
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
301
302 /* this register is used for emulated dcc channel */
303 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* Enable debug requests */
308 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
309 if (retval != ERROR_OK)
310 return retval;
311 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
312 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
313 if (retval != ERROR_OK)
314 return retval;
315 }
316
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target);
319
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
322 *
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
326 */
327 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
328 if (retval != ERROR_OK)
329 return retval;
330
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
333 */
334
335 /* Enable FPB */
336 retval = cortex_m_enable_fpb(target);
337 if (retval != ERROR_OK) {
338 LOG_ERROR("Failed to enable the FPB");
339 return retval;
340 }
341
342 cortex_m->fpb_enabled = true;
343
344 /* Restore FPB registers */
345 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
346 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350
351 /* Restore DWT registers */
352 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
353 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
354 dwt_list[i].comp);
355 if (retval != ERROR_OK)
356 return retval;
357 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
358 dwt_list[i].mask);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
362 dwt_list[i].function);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366 retval = dap_run(swjdp);
367 if (retval != ERROR_OK)
368 return retval;
369
370 register_cache_invalidate(armv7m->arm.core_cache);
371
372 /* make sure we have latest dhcsr flags */
373 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
374
375 return retval;
376 }
377
378 static int cortex_m_examine_debug_reason(struct target *target)
379 {
380 struct cortex_m_common *cortex_m = target_to_cm(target);
381
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
384
385 if ((target->debug_reason != DBG_REASON_DBGRQ)
386 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
387 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
388 target->debug_reason = DBG_REASON_BREAKPOINT;
389 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
390 target->debug_reason = DBG_REASON_WPTANDBKPT;
391 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
392 target->debug_reason = DBG_REASON_WATCHPOINT;
393 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
394 target->debug_reason = DBG_REASON_BREAKPOINT;
395 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
396 target->debug_reason = DBG_REASON_DBGRQ;
397 else /* HALTED */
398 target->debug_reason = DBG_REASON_UNDEFINED;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int cortex_m_examine_exception_reason(struct target *target)
405 {
406 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
407 struct armv7m_common *armv7m = target_to_armv7m(target);
408 struct adiv5_dap *swjdp = armv7m->arm.dap;
409 int retval;
410
411 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
412 if (retval != ERROR_OK)
413 return retval;
414 switch (armv7m->exception_number) {
415 case 2: /* NMI */
416 break;
417 case 3: /* Hard Fault */
418 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
419 if (retval != ERROR_OK)
420 return retval;
421 if (except_sr & 0x40000000) {
422 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
423 if (retval != ERROR_OK)
424 return retval;
425 }
426 break;
427 case 4: /* Memory Management */
428 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
432 if (retval != ERROR_OK)
433 return retval;
434 break;
435 case 5: /* Bus Fault */
436 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
440 if (retval != ERROR_OK)
441 return retval;
442 break;
443 case 6: /* Usage Fault */
444 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
445 if (retval != ERROR_OK)
446 return retval;
447 break;
448 case 7: /* Secure Fault */
449 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
453 if (retval != ERROR_OK)
454 return retval;
455 break;
456 case 11: /* SVCall */
457 break;
458 case 12: /* Debug Monitor */
459 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
460 if (retval != ERROR_OK)
461 return retval;
462 break;
463 case 14: /* PendSV */
464 break;
465 case 15: /* SysTick */
466 break;
467 default:
468 except_sr = 0;
469 break;
470 }
471 retval = dap_run(swjdp);
472 if (retval == ERROR_OK)
473 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
474 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
475 armv7m_exception_string(armv7m->exception_number),
476 shcsr, except_sr, cfsr, except_ar);
477 return retval;
478 }
479
480 static int cortex_m_debug_entry(struct target *target)
481 {
482 int i;
483 uint32_t xPSR;
484 int retval;
485 struct cortex_m_common *cortex_m = target_to_cm(target);
486 struct armv7m_common *armv7m = &cortex_m->armv7m;
487 struct arm *arm = &armv7m->arm;
488 struct reg *r;
489
490 LOG_DEBUG(" ");
491
492 /* Do this really early to minimize the window where the MASKINTS erratum
493 * can pile up pending interrupts. */
494 cortex_m_set_maskints_for_halt(target);
495
496 cortex_m_clear_halt(target);
497 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
498 if (retval != ERROR_OK)
499 return retval;
500
501 retval = armv7m->examine_debug_reason(target);
502 if (retval != ERROR_OK)
503 return retval;
504
505 /* examine PE security state */
506 bool secure_state = false;
507 if (armv7m->arm.is_armv8m) {
508 uint32_t dscsr;
509
510 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
511 if (retval != ERROR_OK)
512 return retval;
513
514 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
515 }
516
517 /* Examine target state and mode
518 * First load register accessible through core debug port */
519 int num_regs = arm->core_cache->num_regs;
520
521 for (i = 0; i < num_regs; i++) {
522 r = &armv7m->arm.core_cache->reg_list[i];
523 if (!r->valid)
524 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
525 }
526
527 r = arm->cpsr;
528 xPSR = buf_get_u32(r->value, 0, 32);
529
530 /* Are we in an exception handler */
531 if (xPSR & 0x1FF) {
532 armv7m->exception_number = (xPSR & 0x1FF);
533
534 arm->core_mode = ARM_MODE_HANDLER;
535 arm->map = armv7m_msp_reg_map;
536 } else {
537 unsigned control = buf_get_u32(arm->core_cache
538 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
539
540 /* is this thread privileged? */
541 arm->core_mode = control & 1
542 ? ARM_MODE_USER_THREAD
543 : ARM_MODE_THREAD;
544
545 /* which stack is it using? */
546 if (control & 2)
547 arm->map = armv7m_psp_reg_map;
548 else
549 arm->map = armv7m_msp_reg_map;
550
551 armv7m->exception_number = 0;
552 }
553
554 if (armv7m->exception_number)
555 cortex_m_examine_exception_reason(target);
556
557 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
558 arm_mode_name(arm->core_mode),
559 buf_get_u32(arm->pc->value, 0, 32),
560 secure_state ? "Secure" : "Non-Secure",
561 target_state_name(target));
562
563 if (armv7m->post_debug_entry) {
564 retval = armv7m->post_debug_entry(target);
565 if (retval != ERROR_OK)
566 return retval;
567 }
568
569 return ERROR_OK;
570 }
571
572 static int cortex_m_poll(struct target *target)
573 {
574 int detected_failure = ERROR_OK;
575 int retval = ERROR_OK;
576 enum target_state prev_target_state = target->state;
577 struct cortex_m_common *cortex_m = target_to_cm(target);
578 struct armv7m_common *armv7m = &cortex_m->armv7m;
579
580 /* Read from Debug Halting Control and Status Register */
581 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
582 if (retval != ERROR_OK) {
583 target->state = TARGET_UNKNOWN;
584 return retval;
585 }
586
587 /* Recover from lockup. See ARMv7-M architecture spec,
588 * section B1.5.15 "Unrecoverable exception cases".
589 */
590 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
591 LOG_ERROR("%s -- clearing lockup after double fault",
592 target_name(target));
593 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
594 target->debug_reason = DBG_REASON_DBGRQ;
595
596 /* We have to execute the rest (the "finally" equivalent, but
597 * still throw this exception again).
598 */
599 detected_failure = ERROR_FAIL;
600
601 /* refresh status bits */
602 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
603 if (retval != ERROR_OK)
604 return retval;
605 }
606
607 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
608 if (target->state != TARGET_RESET) {
609 target->state = TARGET_RESET;
610 LOG_INFO("%s: external reset detected", target_name(target));
611 }
612 return ERROR_OK;
613 }
614
615 if (target->state == TARGET_RESET) {
616 /* Cannot switch context while running so endreset is
617 * called with target->state == TARGET_RESET
618 */
619 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
620 cortex_m->dcb_dhcsr);
621 retval = cortex_m_endreset_event(target);
622 if (retval != ERROR_OK) {
623 target->state = TARGET_UNKNOWN;
624 return retval;
625 }
626 target->state = TARGET_RUNNING;
627 prev_target_state = TARGET_RUNNING;
628 }
629
630 if (cortex_m->dcb_dhcsr & S_HALT) {
631 target->state = TARGET_HALTED;
632
633 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
634 retval = cortex_m_debug_entry(target);
635 if (retval != ERROR_OK)
636 return retval;
637
638 if (arm_semihosting(target, &retval) != 0)
639 return retval;
640
641 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
642 }
643 if (prev_target_state == TARGET_DEBUG_RUNNING) {
644 LOG_DEBUG(" ");
645 retval = cortex_m_debug_entry(target);
646 if (retval != ERROR_OK)
647 return retval;
648
649 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
650 }
651 }
652
653 if (target->state == TARGET_UNKNOWN) {
654 /* check if processor is retiring instructions or sleeping */
655 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
656 target->state = TARGET_RUNNING;
657 retval = ERROR_OK;
658 }
659 }
660
661 /* Check that target is truly halted, since the target could be resumed externally */
662 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
663 /* registers are now invalid */
664 register_cache_invalidate(armv7m->arm.core_cache);
665
666 target->state = TARGET_RUNNING;
667 LOG_WARNING("%s: external resume detected", target_name(target));
668 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
669 retval = ERROR_OK;
670 }
671
672 /* Did we detect a failure condition that we cleared? */
673 if (detected_failure != ERROR_OK)
674 retval = detected_failure;
675 return retval;
676 }
677
678 static int cortex_m_halt(struct target *target)
679 {
680 LOG_DEBUG("target->state: %s",
681 target_state_name(target));
682
683 if (target->state == TARGET_HALTED) {
684 LOG_DEBUG("target was already halted");
685 return ERROR_OK;
686 }
687
688 if (target->state == TARGET_UNKNOWN)
689 LOG_WARNING("target was in unknown state when halt was requested");
690
691 if (target->state == TARGET_RESET) {
692 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
693 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
694 return ERROR_TARGET_FAILURE;
695 } else {
696 /* we came here in a reset_halt or reset_init sequence
697 * debug entry was already prepared in cortex_m3_assert_reset()
698 */
699 target->debug_reason = DBG_REASON_DBGRQ;
700
701 return ERROR_OK;
702 }
703 }
704
705 /* Write to Debug Halting Control and Status Register */
706 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
707
708 /* Do this really early to minimize the window where the MASKINTS erratum
709 * can pile up pending interrupts. */
710 cortex_m_set_maskints_for_halt(target);
711
712 target->debug_reason = DBG_REASON_DBGRQ;
713
714 return ERROR_OK;
715 }
716
717 static int cortex_m_soft_reset_halt(struct target *target)
718 {
719 struct cortex_m_common *cortex_m = target_to_cm(target);
720 struct armv7m_common *armv7m = &cortex_m->armv7m;
721 uint32_t dcb_dhcsr = 0;
722 int retval, timeout = 0;
723
724 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
725 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
726 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
727 * core, not the peripherals */
728 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
729
730 /* Set C_DEBUGEN */
731 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
732 if (retval != ERROR_OK)
733 return retval;
734
735 /* Enter debug state on reset; restore DEMCR in endreset_event() */
736 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
737 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
738 if (retval != ERROR_OK)
739 return retval;
740
741 /* Request a core-only reset */
742 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
743 AIRCR_VECTKEY | AIRCR_VECTRESET);
744 if (retval != ERROR_OK)
745 return retval;
746 target->state = TARGET_RESET;
747
748 /* registers are now invalid */
749 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
750
751 while (timeout < 100) {
752 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
753 if (retval == ERROR_OK) {
754 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
755 &cortex_m->nvic_dfsr);
756 if (retval != ERROR_OK)
757 return retval;
758 if ((dcb_dhcsr & S_HALT)
759 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
760 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
761 "DFSR 0x%08x",
762 (unsigned) dcb_dhcsr,
763 (unsigned) cortex_m->nvic_dfsr);
764 cortex_m_poll(target);
765 /* FIXME restore user's vector catch config */
766 return ERROR_OK;
767 } else
768 LOG_DEBUG("waiting for system reset-halt, "
769 "DHCSR 0x%08x, %d ms",
770 (unsigned) dcb_dhcsr, timeout);
771 }
772 timeout++;
773 alive_sleep(1);
774 }
775
776 return ERROR_OK;
777 }
778
779 void cortex_m_enable_breakpoints(struct target *target)
780 {
781 struct breakpoint *breakpoint = target->breakpoints;
782
783 /* set any pending breakpoints */
784 while (breakpoint) {
785 if (!breakpoint->set)
786 cortex_m_set_breakpoint(target, breakpoint);
787 breakpoint = breakpoint->next;
788 }
789 }
790
791 static int cortex_m_resume(struct target *target, int current,
792 target_addr_t address, int handle_breakpoints, int debug_execution)
793 {
794 struct armv7m_common *armv7m = target_to_armv7m(target);
795 struct breakpoint *breakpoint = NULL;
796 uint32_t resume_pc;
797 struct reg *r;
798
799 if (target->state != TARGET_HALTED) {
800 LOG_WARNING("target not halted");
801 return ERROR_TARGET_NOT_HALTED;
802 }
803
804 if (!debug_execution) {
805 target_free_all_working_areas(target);
806 cortex_m_enable_breakpoints(target);
807 cortex_m_enable_watchpoints(target);
808 }
809
810 if (debug_execution) {
811 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
812
813 /* Disable interrupts */
814 /* We disable interrupts in the PRIMASK register instead of
815 * masking with C_MASKINTS. This is probably the same issue
816 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
817 * in parallel with disabled interrupts can cause local faults
818 * to not be taken.
819 *
820 * This breaks non-debug (application) execution if not
821 * called from armv7m_start_algorithm() which saves registers.
822 */
823 buf_set_u32(r->value, 0, 1, 1);
824 r->dirty = true;
825 r->valid = true;
826
827 /* Make sure we are in Thumb mode, set xPSR.T bit */
828 /* armv7m_start_algorithm() initializes entire xPSR register.
829 * This duplicity handles the case when cortex_m_resume()
830 * is used with the debug_execution flag directly,
831 * not called through armv7m_start_algorithm().
832 */
833 r = armv7m->arm.cpsr;
834 buf_set_u32(r->value, 24, 1, 1);
835 r->dirty = true;
836 r->valid = true;
837 }
838
839 /* current = 1: continue on current pc, otherwise continue at <address> */
840 r = armv7m->arm.pc;
841 if (!current) {
842 buf_set_u32(r->value, 0, 32, address);
843 r->dirty = true;
844 r->valid = true;
845 }
846
847 /* if we halted last time due to a bkpt instruction
848 * then we have to manually step over it, otherwise
849 * the core will break again */
850
851 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
852 && !debug_execution)
853 armv7m_maybe_skip_bkpt_inst(target, NULL);
854
855 resume_pc = buf_get_u32(r->value, 0, 32);
856
857 armv7m_restore_context(target);
858
859 /* the front-end may request us not to handle breakpoints */
860 if (handle_breakpoints) {
861 /* Single step past breakpoint at current address */
862 breakpoint = breakpoint_find(target, resume_pc);
863 if (breakpoint) {
864 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
865 breakpoint->address,
866 breakpoint->unique_id);
867 cortex_m_unset_breakpoint(target, breakpoint);
868 cortex_m_single_step_core(target);
869 cortex_m_set_breakpoint(target, breakpoint);
870 }
871 }
872
873 /* Restart core */
874 cortex_m_set_maskints_for_run(target);
875 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
876
877 target->debug_reason = DBG_REASON_NOTHALTED;
878
879 /* registers are now invalid */
880 register_cache_invalidate(armv7m->arm.core_cache);
881
882 if (!debug_execution) {
883 target->state = TARGET_RUNNING;
884 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
885 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
886 } else {
887 target->state = TARGET_DEBUG_RUNNING;
888 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
889 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
890 }
891
892 return ERROR_OK;
893 }
894
895 /* int irqstepcount = 0; */
896 static int cortex_m_step(struct target *target, int current,
897 target_addr_t address, int handle_breakpoints)
898 {
899 struct cortex_m_common *cortex_m = target_to_cm(target);
900 struct armv7m_common *armv7m = &cortex_m->armv7m;
901 struct breakpoint *breakpoint = NULL;
902 struct reg *pc = armv7m->arm.pc;
903 bool bkpt_inst_found = false;
904 int retval;
905 bool isr_timed_out = false;
906
907 if (target->state != TARGET_HALTED) {
908 LOG_WARNING("target not halted");
909 return ERROR_TARGET_NOT_HALTED;
910 }
911
912 /* current = 1: continue on current pc, otherwise continue at <address> */
913 if (!current)
914 buf_set_u32(pc->value, 0, 32, address);
915
916 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
917
918 /* the front-end may request us not to handle breakpoints */
919 if (handle_breakpoints) {
920 breakpoint = breakpoint_find(target, pc_value);
921 if (breakpoint)
922 cortex_m_unset_breakpoint(target, breakpoint);
923 }
924
925 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
926
927 target->debug_reason = DBG_REASON_SINGLESTEP;
928
929 armv7m_restore_context(target);
930
931 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
932
933 /* if no bkpt instruction is found at pc then we can perform
934 * a normal step, otherwise we have to manually step over the bkpt
935 * instruction - as such simulate a step */
936 if (bkpt_inst_found == false) {
937 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
938 /* Automatic ISR masking mode off: Just step over the next
939 * instruction, with interrupts on or off as appropriate. */
940 cortex_m_set_maskints_for_step(target);
941 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
942 } else {
943 /* Process interrupts during stepping in a way they don't interfere
944 * debugging.
945 *
946 * Principle:
947 *
948 * Set a temporary break point at the current pc and let the core run
949 * with interrupts enabled. Pending interrupts get served and we run
950 * into the breakpoint again afterwards. Then we step over the next
951 * instruction with interrupts disabled.
952 *
953 * If the pending interrupts don't complete within time, we leave the
954 * core running. This may happen if the interrupts trigger faster
955 * than the core can process them or the handler doesn't return.
956 *
957 * If no more breakpoints are available we simply do a step with
958 * interrupts enabled.
959 *
960 */
961
962 /* 2012-09-29 ph
963 *
964 * If a break point is already set on the lower half word then a break point on
965 * the upper half word will not break again when the core is restarted. So we
966 * just step over the instruction with interrupts disabled.
967 *
968 * The documentation has no information about this, it was found by observation
969 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
970 * suffer from this problem.
971 *
972 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
973 * address has it always cleared. The former is done to indicate thumb mode
974 * to gdb.
975 *
976 */
977 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
978 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
979 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
980 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
981 /* Re-enable interrupts if appropriate */
982 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
983 cortex_m_set_maskints_for_halt(target);
984 } else {
985
986 /* Set a temporary break point */
987 if (breakpoint) {
988 retval = cortex_m_set_breakpoint(target, breakpoint);
989 } else {
990 enum breakpoint_type type = BKPT_HARD;
991 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
992 /* FPB rev.1 cannot handle such addr, try BKPT instr */
993 type = BKPT_SOFT;
994 }
995 retval = breakpoint_add(target, pc_value, 2, type);
996 }
997
998 bool tmp_bp_set = (retval == ERROR_OK);
999
1000 /* No more breakpoints left, just do a step */
1001 if (!tmp_bp_set) {
1002 cortex_m_set_maskints_for_step(target);
1003 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1004 /* Re-enable interrupts if appropriate */
1005 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1006 cortex_m_set_maskints_for_halt(target);
1007 } else {
1008 /* Start the core */
1009 LOG_DEBUG("Starting core to serve pending interrupts");
1010 int64_t t_start = timeval_ms();
1011 cortex_m_set_maskints_for_run(target);
1012 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1013
1014 /* Wait for pending handlers to complete or timeout */
1015 do {
1016 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1017 DCB_DHCSR,
1018 &cortex_m->dcb_dhcsr);
1019 if (retval != ERROR_OK) {
1020 target->state = TARGET_UNKNOWN;
1021 return retval;
1022 }
1023 isr_timed_out = ((timeval_ms() - t_start) > 500);
1024 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1025
1026 /* only remove breakpoint if we created it */
1027 if (breakpoint)
1028 cortex_m_unset_breakpoint(target, breakpoint);
1029 else {
1030 /* Remove the temporary breakpoint */
1031 breakpoint_remove(target, pc_value);
1032 }
1033
1034 if (isr_timed_out) {
1035 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1036 "leaving target running");
1037 } else {
1038 /* Step over next instruction with interrupts disabled */
1039 cortex_m_set_maskints_for_step(target);
1040 cortex_m_write_debug_halt_mask(target,
1041 C_HALT | C_MASKINTS,
1042 0);
1043 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1044 /* Re-enable interrupts if appropriate */
1045 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1046 cortex_m_set_maskints_for_halt(target);
1047 }
1048 }
1049 }
1050 }
1051 }
1052
1053 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1054 if (retval != ERROR_OK)
1055 return retval;
1056
1057 /* registers are now invalid */
1058 register_cache_invalidate(armv7m->arm.core_cache);
1059
1060 if (breakpoint)
1061 cortex_m_set_breakpoint(target, breakpoint);
1062
1063 if (isr_timed_out) {
1064 /* Leave the core running. The user has to stop execution manually. */
1065 target->debug_reason = DBG_REASON_NOTHALTED;
1066 target->state = TARGET_RUNNING;
1067 return ERROR_OK;
1068 }
1069
1070 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1071 " nvic_icsr = 0x%" PRIx32,
1072 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1073
1074 retval = cortex_m_debug_entry(target);
1075 if (retval != ERROR_OK)
1076 return retval;
1077 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1078
1079 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1080 " nvic_icsr = 0x%" PRIx32,
1081 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1082
1083 return ERROR_OK;
1084 }
1085
1086 static int cortex_m_assert_reset(struct target *target)
1087 {
1088 struct cortex_m_common *cortex_m = target_to_cm(target);
1089 struct armv7m_common *armv7m = &cortex_m->armv7m;
1090 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1091
1092 LOG_DEBUG("target->state: %s",
1093 target_state_name(target));
1094
1095 enum reset_types jtag_reset_config = jtag_get_reset_config();
1096
1097 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1098 /* allow scripts to override the reset event */
1099
1100 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1101 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1102 target->state = TARGET_RESET;
1103
1104 return ERROR_OK;
1105 }
1106
1107 /* some cores support connecting while srst is asserted
1108 * use that mode is it has been configured */
1109
1110 bool srst_asserted = false;
1111
1112 if (!target_was_examined(target)) {
1113 if (jtag_reset_config & RESET_HAS_SRST) {
1114 adapter_assert_reset();
1115 if (target->reset_halt)
1116 LOG_ERROR("Target not examined, will not halt after reset!");
1117 return ERROR_OK;
1118 } else {
1119 LOG_ERROR("Target not examined, reset NOT asserted!");
1120 return ERROR_FAIL;
1121 }
1122 }
1123
1124 if ((jtag_reset_config & RESET_HAS_SRST) &&
1125 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1126 adapter_assert_reset();
1127 srst_asserted = true;
1128 }
1129
1130 /* Enable debug requests */
1131 int retval;
1132 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1133 /* Store important errors instead of failing and proceed to reset assert */
1134
1135 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1136 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1137
1138 /* If the processor is sleeping in a WFI or WFE instruction, the
1139 * C_HALT bit must be asserted to regain control */
1140 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1141 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1142
1143 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1144 /* Ignore less important errors */
1145
1146 if (!target->reset_halt) {
1147 /* Set/Clear C_MASKINTS in a separate operation */
1148 cortex_m_set_maskints_for_run(target);
1149
1150 /* clear any debug flags before resuming */
1151 cortex_m_clear_halt(target);
1152
1153 /* clear C_HALT in dhcsr reg */
1154 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1155 } else {
1156 /* Halt in debug on reset; endreset_event() restores DEMCR.
1157 *
1158 * REVISIT catching BUSERR presumably helps to defend against
1159 * bad vector table entries. Should this include MMERR or
1160 * other flags too?
1161 */
1162 int retval2;
1163 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1164 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1165 if (retval != ERROR_OK || retval2 != ERROR_OK)
1166 LOG_INFO("AP write error, reset will not halt");
1167 }
1168
1169 if (jtag_reset_config & RESET_HAS_SRST) {
1170 /* default to asserting srst */
1171 if (!srst_asserted)
1172 adapter_assert_reset();
1173
1174 /* srst is asserted, ignore AP access errors */
1175 retval = ERROR_OK;
1176 } else {
1177 /* Use a standard Cortex-M3 software reset mechanism.
1178 * We default to using VECRESET as it is supported on all current cores
1179 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1180 * This has the disadvantage of not resetting the peripherals, so a
1181 * reset-init event handler is needed to perform any peripheral resets.
1182 */
1183 if (!cortex_m->vectreset_supported
1184 && reset_config == CORTEX_M_RESET_VECTRESET) {
1185 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1186 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1187 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1188 }
1189
1190 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1191 ? "SYSRESETREQ" : "VECTRESET");
1192
1193 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1194 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1195 "handler to reset any peripherals or configure hardware srst support.");
1196 }
1197
1198 int retval3;
1199 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1200 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1201 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1202 if (retval3 != ERROR_OK)
1203 LOG_DEBUG("Ignoring AP write error right after reset");
1204
1205 retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1206 if (retval3 != ERROR_OK) {
1207 LOG_ERROR("DP initialisation failed");
1208 /* The error return value must not be propagated in this case.
1209 * SYSRESETREQ or VECTRESET have been possibly triggered
1210 * so reset processing should continue */
1211 } else {
1212 /* I do not know why this is necessary, but it
1213 * fixes strange effects (step/resume cause NMI
1214 * after reset) on LM3S6918 -- Michael Schwingen
1215 */
1216 uint32_t tmp;
1217 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1218 }
1219 }
1220
1221 target->state = TARGET_RESET;
1222 jtag_sleep(50000);
1223
1224 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1225
1226 /* now return stored error code if any */
1227 if (retval != ERROR_OK)
1228 return retval;
1229
1230 if (target->reset_halt) {
1231 retval = target_halt(target);
1232 if (retval != ERROR_OK)
1233 return retval;
1234 }
1235
1236 return ERROR_OK;
1237 }
1238
1239 static int cortex_m_deassert_reset(struct target *target)
1240 {
1241 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1242
1243 LOG_DEBUG("target->state: %s",
1244 target_state_name(target));
1245
1246 /* deassert reset lines */
1247 adapter_deassert_reset();
1248
1249 enum reset_types jtag_reset_config = jtag_get_reset_config();
1250
1251 if ((jtag_reset_config & RESET_HAS_SRST) &&
1252 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1253 target_was_examined(target)) {
1254
1255 int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1256 if (retval != ERROR_OK) {
1257 LOG_ERROR("DP initialisation failed");
1258 return retval;
1259 }
1260 }
1261
1262 return ERROR_OK;
1263 }
1264
1265 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1266 {
1267 int retval;
1268 int fp_num = 0;
1269 struct cortex_m_common *cortex_m = target_to_cm(target);
1270 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1271
1272 if (breakpoint->set) {
1273 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1274 return ERROR_OK;
1275 }
1276
1277 if (breakpoint->type == BKPT_HARD) {
1278 uint32_t fpcr_value;
1279 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1280 fp_num++;
1281 if (fp_num >= cortex_m->fp_num_code) {
1282 LOG_ERROR("Can not find free FPB Comparator!");
1283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1284 }
1285 breakpoint->set = fp_num + 1;
1286 fpcr_value = breakpoint->address | 1;
1287 if (cortex_m->fp_rev == 0) {
1288 if (breakpoint->address > 0x1FFFFFFF) {
1289 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1290 return ERROR_FAIL;
1291 }
1292 uint32_t hilo;
1293 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1294 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1295 } else if (cortex_m->fp_rev > 1) {
1296 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1297 return ERROR_FAIL;
1298 }
1299 comparator_list[fp_num].used = true;
1300 comparator_list[fp_num].fpcr_value = fpcr_value;
1301 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1302 comparator_list[fp_num].fpcr_value);
1303 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1304 fp_num,
1305 comparator_list[fp_num].fpcr_value);
1306 if (!cortex_m->fpb_enabled) {
1307 LOG_DEBUG("FPB wasn't enabled, do it now");
1308 retval = cortex_m_enable_fpb(target);
1309 if (retval != ERROR_OK) {
1310 LOG_ERROR("Failed to enable the FPB");
1311 return retval;
1312 }
1313
1314 cortex_m->fpb_enabled = true;
1315 }
1316 } else if (breakpoint->type == BKPT_SOFT) {
1317 uint8_t code[4];
1318
1319 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1320 * semihosting; don't use that. Otherwise the BKPT
1321 * parameter is arbitrary.
1322 */
1323 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1324 retval = target_read_memory(target,
1325 breakpoint->address & 0xFFFFFFFE,
1326 breakpoint->length, 1,
1327 breakpoint->orig_instr);
1328 if (retval != ERROR_OK)
1329 return retval;
1330 retval = target_write_memory(target,
1331 breakpoint->address & 0xFFFFFFFE,
1332 breakpoint->length, 1,
1333 code);
1334 if (retval != ERROR_OK)
1335 return retval;
1336 breakpoint->set = true;
1337 }
1338
1339 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1340 breakpoint->unique_id,
1341 (int)(breakpoint->type),
1342 breakpoint->address,
1343 breakpoint->length,
1344 breakpoint->set);
1345
1346 return ERROR_OK;
1347 }
1348
1349 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1350 {
1351 int retval;
1352 struct cortex_m_common *cortex_m = target_to_cm(target);
1353 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1354
1355 if (!breakpoint->set) {
1356 LOG_WARNING("breakpoint not set");
1357 return ERROR_OK;
1358 }
1359
1360 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1361 breakpoint->unique_id,
1362 (int)(breakpoint->type),
1363 breakpoint->address,
1364 breakpoint->length,
1365 breakpoint->set);
1366
1367 if (breakpoint->type == BKPT_HARD) {
1368 int fp_num = breakpoint->set - 1;
1369 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1370 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1371 return ERROR_OK;
1372 }
1373 comparator_list[fp_num].used = false;
1374 comparator_list[fp_num].fpcr_value = 0;
1375 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1376 comparator_list[fp_num].fpcr_value);
1377 } else {
1378 /* restore original instruction (kept in target endianness) */
1379 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1380 breakpoint->length, 1,
1381 breakpoint->orig_instr);
1382 if (retval != ERROR_OK)
1383 return retval;
1384 }
1385 breakpoint->set = false;
1386
1387 return ERROR_OK;
1388 }
1389
1390 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1391 {
1392 if (breakpoint->length == 3) {
1393 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1394 breakpoint->length = 2;
1395 }
1396
1397 if ((breakpoint->length != 2)) {
1398 LOG_INFO("only breakpoints of two bytes length supported");
1399 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1400 }
1401
1402 return cortex_m_set_breakpoint(target, breakpoint);
1403 }
1404
1405 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1406 {
1407 if (!breakpoint->set)
1408 return ERROR_OK;
1409
1410 return cortex_m_unset_breakpoint(target, breakpoint);
1411 }
1412
1413 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1414 {
1415 int dwt_num = 0;
1416 struct cortex_m_common *cortex_m = target_to_cm(target);
1417
1418 /* REVISIT Don't fully trust these "not used" records ... users
1419 * may set up breakpoints by hand, e.g. dual-address data value
1420 * watchpoint using comparator #1; comparator #0 matching cycle
1421 * count; send data trace info through ITM and TPIU; etc
1422 */
1423 struct cortex_m_dwt_comparator *comparator;
1424
1425 for (comparator = cortex_m->dwt_comparator_list;
1426 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1427 comparator++, dwt_num++)
1428 continue;
1429 if (dwt_num >= cortex_m->dwt_num_comp) {
1430 LOG_ERROR("Can not find free DWT Comparator");
1431 return ERROR_FAIL;
1432 }
1433 comparator->used = true;
1434 watchpoint->set = dwt_num + 1;
1435
1436 comparator->comp = watchpoint->address;
1437 target_write_u32(target, comparator->dwt_comparator_address + 0,
1438 comparator->comp);
1439
1440 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1441 uint32_t mask = 0, temp;
1442
1443 /* watchpoint params were validated earlier */
1444 temp = watchpoint->length;
1445 while (temp) {
1446 temp >>= 1;
1447 mask++;
1448 }
1449 mask--;
1450
1451 comparator->mask = mask;
1452 target_write_u32(target, comparator->dwt_comparator_address + 4,
1453 comparator->mask);
1454
1455 switch (watchpoint->rw) {
1456 case WPT_READ:
1457 comparator->function = 5;
1458 break;
1459 case WPT_WRITE:
1460 comparator->function = 6;
1461 break;
1462 case WPT_ACCESS:
1463 comparator->function = 7;
1464 break;
1465 }
1466 } else {
1467 uint32_t data_size = watchpoint->length >> 1;
1468 comparator->mask = (watchpoint->length >> 1) | 1;
1469
1470 switch (watchpoint->rw) {
1471 case WPT_ACCESS:
1472 comparator->function = 4;
1473 break;
1474 case WPT_WRITE:
1475 comparator->function = 5;
1476 break;
1477 case WPT_READ:
1478 comparator->function = 6;
1479 break;
1480 }
1481 comparator->function = comparator->function | (1 << 4) |
1482 (data_size << 10);
1483 }
1484
1485 target_write_u32(target, comparator->dwt_comparator_address + 8,
1486 comparator->function);
1487
1488 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1489 watchpoint->unique_id, dwt_num,
1490 (unsigned) comparator->comp,
1491 (unsigned) comparator->mask,
1492 (unsigned) comparator->function);
1493 return ERROR_OK;
1494 }
1495
1496 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1497 {
1498 struct cortex_m_common *cortex_m = target_to_cm(target);
1499 struct cortex_m_dwt_comparator *comparator;
1500 int dwt_num;
1501
1502 if (!watchpoint->set) {
1503 LOG_WARNING("watchpoint (wpid: %d) not set",
1504 watchpoint->unique_id);
1505 return ERROR_OK;
1506 }
1507
1508 dwt_num = watchpoint->set - 1;
1509
1510 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1511 watchpoint->unique_id, dwt_num,
1512 (unsigned) watchpoint->address);
1513
1514 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1515 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1516 return ERROR_OK;
1517 }
1518
1519 comparator = cortex_m->dwt_comparator_list + dwt_num;
1520 comparator->used = false;
1521 comparator->function = 0;
1522 target_write_u32(target, comparator->dwt_comparator_address + 8,
1523 comparator->function);
1524
1525 watchpoint->set = false;
1526
1527 return ERROR_OK;
1528 }
1529
1530 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1531 {
1532 struct cortex_m_common *cortex_m = target_to_cm(target);
1533
1534 if (cortex_m->dwt_comp_available < 1) {
1535 LOG_DEBUG("no comparators?");
1536 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1537 }
1538
1539 /* hardware doesn't support data value masking */
1540 if (watchpoint->mask != ~(uint32_t)0) {
1541 LOG_DEBUG("watchpoint value masks not supported");
1542 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1543 }
1544
1545 /* hardware allows address masks of up to 32K */
1546 unsigned mask;
1547
1548 for (mask = 0; mask < 16; mask++) {
1549 if ((1u << mask) == watchpoint->length)
1550 break;
1551 }
1552 if (mask == 16) {
1553 LOG_DEBUG("unsupported watchpoint length");
1554 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1555 }
1556 if (watchpoint->address & ((1 << mask) - 1)) {
1557 LOG_DEBUG("watchpoint address is unaligned");
1558 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1559 }
1560
1561 /* Caller doesn't seem to be able to describe watching for data
1562 * values of zero; that flags "no value".
1563 *
1564 * REVISIT This DWT may well be able to watch for specific data
1565 * values. Requires comparator #1 to set DATAVMATCH and match
1566 * the data, and another comparator (DATAVADDR0) matching addr.
1567 */
1568 if (watchpoint->value) {
1569 LOG_DEBUG("data value watchpoint not YET supported");
1570 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1571 }
1572
1573 cortex_m->dwt_comp_available--;
1574 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1575
1576 return ERROR_OK;
1577 }
1578
1579 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1580 {
1581 struct cortex_m_common *cortex_m = target_to_cm(target);
1582
1583 /* REVISIT why check? DWT can be updated with core running ... */
1584 if (target->state != TARGET_HALTED) {
1585 LOG_WARNING("target not halted");
1586 return ERROR_TARGET_NOT_HALTED;
1587 }
1588
1589 if (watchpoint->set)
1590 cortex_m_unset_watchpoint(target, watchpoint);
1591
1592 cortex_m->dwt_comp_available++;
1593 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1594
1595 return ERROR_OK;
1596 }
1597
1598 void cortex_m_enable_watchpoints(struct target *target)
1599 {
1600 struct watchpoint *watchpoint = target->watchpoints;
1601
1602 /* set any pending watchpoints */
1603 while (watchpoint) {
1604 if (!watchpoint->set)
1605 cortex_m_set_watchpoint(target, watchpoint);
1606 watchpoint = watchpoint->next;
1607 }
1608 }
1609
1610 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1611 uint32_t size, uint32_t count, uint8_t *buffer)
1612 {
1613 struct armv7m_common *armv7m = target_to_armv7m(target);
1614
1615 if (armv7m->arm.is_armv6m) {
1616 /* armv6m does not handle unaligned memory access */
1617 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1618 return ERROR_TARGET_UNALIGNED_ACCESS;
1619 }
1620
1621 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1622 }
1623
1624 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1625 uint32_t size, uint32_t count, const uint8_t *buffer)
1626 {
1627 struct armv7m_common *armv7m = target_to_armv7m(target);
1628
1629 if (armv7m->arm.is_armv6m) {
1630 /* armv6m does not handle unaligned memory access */
1631 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1632 return ERROR_TARGET_UNALIGNED_ACCESS;
1633 }
1634
1635 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1636 }
1637
1638 static int cortex_m_init_target(struct command_context *cmd_ctx,
1639 struct target *target)
1640 {
1641 armv7m_build_reg_cache(target);
1642 arm_semihosting_init(target);
1643 return ERROR_OK;
1644 }
1645
1646 void cortex_m_deinit_target(struct target *target)
1647 {
1648 struct cortex_m_common *cortex_m = target_to_cm(target);
1649
1650 free(cortex_m->fp_comparator_list);
1651
1652 cortex_m_dwt_free(target);
1653 armv7m_free_reg_cache(target);
1654
1655 free(target->private_config);
1656 free(cortex_m);
1657 }
1658
1659 int cortex_m_profiling(struct target *target, uint32_t *samples,
1660 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1661 {
1662 struct timeval timeout, now;
1663 struct armv7m_common *armv7m = target_to_armv7m(target);
1664 uint32_t reg_value;
1665 int retval;
1666
1667 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1668 if (retval != ERROR_OK) {
1669 LOG_ERROR("Error while reading PCSR");
1670 return retval;
1671 }
1672 if (reg_value == 0) {
1673 LOG_INFO("PCSR sampling not supported on this processor.");
1674 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1675 }
1676
1677 gettimeofday(&timeout, NULL);
1678 timeval_add_time(&timeout, seconds, 0);
1679
1680 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1681
1682 /* Make sure the target is running */
1683 target_poll(target);
1684 if (target->state == TARGET_HALTED)
1685 retval = target_resume(target, 1, 0, 0, 0);
1686
1687 if (retval != ERROR_OK) {
1688 LOG_ERROR("Error while resuming target");
1689 return retval;
1690 }
1691
1692 uint32_t sample_count = 0;
1693
1694 for (;;) {
1695 if (armv7m && armv7m->debug_ap) {
1696 uint32_t read_count = max_num_samples - sample_count;
1697 if (read_count > 1024)
1698 read_count = 1024;
1699
1700 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1701 (void *)&samples[sample_count],
1702 4, read_count, DWT_PCSR);
1703 sample_count += read_count;
1704 } else {
1705 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1706 }
1707
1708 if (retval != ERROR_OK) {
1709 LOG_ERROR("Error while reading PCSR");
1710 return retval;
1711 }
1712
1713
1714 gettimeofday(&now, NULL);
1715 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1716 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1717 break;
1718 }
1719 }
1720
1721 *num_samples = sample_count;
1722 return retval;
1723 }
1724
1725
1726 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1727 * on r/w if the core is not running, and clear on resume or reset ... or
1728 * at least, in a post_restore_context() method.
1729 */
1730
1731 struct dwt_reg_state {
1732 struct target *target;
1733 uint32_t addr;
1734 uint8_t value[4]; /* scratch/cache */
1735 };
1736
1737 static int cortex_m_dwt_get_reg(struct reg *reg)
1738 {
1739 struct dwt_reg_state *state = reg->arch_info;
1740
1741 uint32_t tmp;
1742 int retval = target_read_u32(state->target, state->addr, &tmp);
1743 if (retval != ERROR_OK)
1744 return retval;
1745
1746 buf_set_u32(state->value, 0, 32, tmp);
1747 return ERROR_OK;
1748 }
1749
1750 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1751 {
1752 struct dwt_reg_state *state = reg->arch_info;
1753
1754 return target_write_u32(state->target, state->addr,
1755 buf_get_u32(buf, 0, reg->size));
1756 }
1757
1758 struct dwt_reg {
1759 uint32_t addr;
1760 const char *name;
1761 unsigned size;
1762 };
1763
1764 static const struct dwt_reg dwt_base_regs[] = {
1765 { DWT_CTRL, "dwt_ctrl", 32, },
1766 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1767 * increments while the core is asleep.
1768 */
1769 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1770 /* plus some 8 bit counters, useful for profiling with TPIU */
1771 };
1772
1773 static const struct dwt_reg dwt_comp[] = {
1774 #define DWT_COMPARATOR(i) \
1775 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1776 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1777 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1778 DWT_COMPARATOR(0),
1779 DWT_COMPARATOR(1),
1780 DWT_COMPARATOR(2),
1781 DWT_COMPARATOR(3),
1782 DWT_COMPARATOR(4),
1783 DWT_COMPARATOR(5),
1784 DWT_COMPARATOR(6),
1785 DWT_COMPARATOR(7),
1786 DWT_COMPARATOR(8),
1787 DWT_COMPARATOR(9),
1788 DWT_COMPARATOR(10),
1789 DWT_COMPARATOR(11),
1790 DWT_COMPARATOR(12),
1791 DWT_COMPARATOR(13),
1792 DWT_COMPARATOR(14),
1793 DWT_COMPARATOR(15),
1794 #undef DWT_COMPARATOR
1795 };
1796
1797 static const struct reg_arch_type dwt_reg_type = {
1798 .get = cortex_m_dwt_get_reg,
1799 .set = cortex_m_dwt_set_reg,
1800 };
1801
1802 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1803 {
1804 struct dwt_reg_state *state;
1805
1806 state = calloc(1, sizeof(*state));
1807 if (!state)
1808 return;
1809 state->addr = d->addr;
1810 state->target = t;
1811
1812 r->name = d->name;
1813 r->size = d->size;
1814 r->value = state->value;
1815 r->arch_info = state;
1816 r->type = &dwt_reg_type;
1817 }
1818
1819 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1820 {
1821 uint32_t dwtcr;
1822 struct reg_cache *cache;
1823 struct cortex_m_dwt_comparator *comparator;
1824 int reg, i;
1825
1826 target_read_u32(target, DWT_CTRL, &dwtcr);
1827 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1828 if (!dwtcr) {
1829 LOG_DEBUG("no DWT");
1830 return;
1831 }
1832
1833 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
1834 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
1835
1836 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1837 cm->dwt_comp_available = cm->dwt_num_comp;
1838 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1839 sizeof(struct cortex_m_dwt_comparator));
1840 if (!cm->dwt_comparator_list) {
1841 fail0:
1842 cm->dwt_num_comp = 0;
1843 LOG_ERROR("out of mem");
1844 return;
1845 }
1846
1847 cache = calloc(1, sizeof(*cache));
1848 if (!cache) {
1849 fail1:
1850 free(cm->dwt_comparator_list);
1851 goto fail0;
1852 }
1853 cache->name = "Cortex-M DWT registers";
1854 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1855 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
1856 if (!cache->reg_list) {
1857 free(cache);
1858 goto fail1;
1859 }
1860
1861 for (reg = 0; reg < 2; reg++)
1862 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1863 dwt_base_regs + reg);
1864
1865 comparator = cm->dwt_comparator_list;
1866 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1867 int j;
1868
1869 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1870 for (j = 0; j < 3; j++, reg++)
1871 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1872 dwt_comp + 3 * i + j);
1873
1874 /* make sure we clear any watchpoints enabled on the target */
1875 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1876 }
1877
1878 *register_get_last_cache_p(&target->reg_cache) = cache;
1879 cm->dwt_cache = cache;
1880
1881 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1882 dwtcr, cm->dwt_num_comp,
1883 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1884
1885 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1886 * implement single-address data value watchpoints ... so we
1887 * won't need to check it later, when asked to set one up.
1888 */
1889 }
1890
1891 static void cortex_m_dwt_free(struct target *target)
1892 {
1893 struct cortex_m_common *cm = target_to_cm(target);
1894 struct reg_cache *cache = cm->dwt_cache;
1895
1896 free(cm->dwt_comparator_list);
1897 cm->dwt_comparator_list = NULL;
1898 cm->dwt_num_comp = 0;
1899
1900 if (cache) {
1901 register_unlink_cache(&target->reg_cache, cache);
1902
1903 if (cache->reg_list) {
1904 for (size_t i = 0; i < cache->num_regs; i++)
1905 free(cache->reg_list[i].arch_info);
1906 free(cache->reg_list);
1907 }
1908 free(cache);
1909 }
1910 cm->dwt_cache = NULL;
1911 }
1912
1913 #define MVFR0 0xe000ef40
1914 #define MVFR1 0xe000ef44
1915
1916 #define MVFR0_DEFAULT_M4 0x10110021
1917 #define MVFR1_DEFAULT_M4 0x11000011
1918
1919 #define MVFR0_DEFAULT_M7_SP 0x10110021
1920 #define MVFR0_DEFAULT_M7_DP 0x10110221
1921 #define MVFR1_DEFAULT_M7_SP 0x11000011
1922 #define MVFR1_DEFAULT_M7_DP 0x12000011
1923
1924 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
1925 struct adiv5_ap **debug_ap)
1926 {
1927 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
1928 return ERROR_OK;
1929
1930 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
1931 }
1932
1933 int cortex_m_examine(struct target *target)
1934 {
1935 int retval;
1936 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1937 int i;
1938 struct cortex_m_common *cortex_m = target_to_cm(target);
1939 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1940 struct armv7m_common *armv7m = target_to_armv7m(target);
1941
1942 /* stlink shares the examine handler but does not support
1943 * all its calls */
1944 if (!armv7m->stlink) {
1945 if (cortex_m->apsel == DP_APSEL_INVALID) {
1946 /* Search for the MEM-AP */
1947 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
1948 if (retval != ERROR_OK) {
1949 LOG_ERROR("Could not find MEM-AP to control the core");
1950 return retval;
1951 }
1952 } else {
1953 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1954 }
1955
1956 /* Leave (only) generic DAP stuff for debugport_init(); */
1957 armv7m->debug_ap->memaccess_tck = 8;
1958
1959 retval = mem_ap_init(armv7m->debug_ap);
1960 if (retval != ERROR_OK)
1961 return retval;
1962 }
1963
1964 if (!target_was_examined(target)) {
1965 target_set_examined(target);
1966
1967 /* Read from Device Identification Registers */
1968 retval = target_read_u32(target, CPUID, &cpuid);
1969 if (retval != ERROR_OK)
1970 return retval;
1971
1972 /* Get CPU Type */
1973 i = (cpuid >> 4) & 0xf;
1974
1975 /* Check if it is an ARMv8-M core */
1976 armv7m->arm.is_armv8m = true;
1977
1978 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
1979 case CORTEX_M23_PARTNO:
1980 i = 23;
1981 break;
1982 case CORTEX_M33_PARTNO:
1983 i = 33;
1984 break;
1985 case CORTEX_M35P_PARTNO:
1986 i = 35;
1987 break;
1988 case CORTEX_M55_PARTNO:
1989 i = 55;
1990 break;
1991 default:
1992 armv7m->arm.is_armv8m = false;
1993 break;
1994 }
1995
1996
1997 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1998 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1999 cortex_m->maskints_erratum = false;
2000 if (i == 7) {
2001 uint8_t rev, patch;
2002 rev = (cpuid >> 20) & 0xf;
2003 patch = (cpuid >> 0) & 0xf;
2004 if ((rev == 0) && (patch < 2)) {
2005 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2006 cortex_m->maskints_erratum = true;
2007 }
2008 }
2009 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2010
2011 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2012 cortex_m->vectreset_supported = i > 1;
2013
2014 if (i == 4) {
2015 target_read_u32(target, MVFR0, &mvfr0);
2016 target_read_u32(target, MVFR1, &mvfr1);
2017
2018 /* test for floating point feature on Cortex-M4 */
2019 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2020 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2021 armv7m->fp_feature = FPv4_SP;
2022 }
2023 } else if (i == 7 || i == 33 || i == 35 || i == 55) {
2024 target_read_u32(target, MVFR0, &mvfr0);
2025 target_read_u32(target, MVFR1, &mvfr1);
2026
2027 /* test for floating point features on Cortex-M7 */
2028 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2029 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2030 armv7m->fp_feature = FPv5_SP;
2031 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2032 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2033 armv7m->fp_feature = FPv5_DP;
2034 }
2035 } else if (i == 0) {
2036 /* Cortex-M0 does not support unaligned memory access */
2037 armv7m->arm.is_armv6m = true;
2038 }
2039
2040 if (armv7m->fp_feature == FP_NONE &&
2041 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2042 /* free unavailable FPU registers */
2043 size_t idx;
2044
2045 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2046 idx < armv7m->arm.core_cache->num_regs;
2047 idx++) {
2048 free(armv7m->arm.core_cache->reg_list[idx].feature);
2049 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2050 }
2051 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2052 }
2053
2054 if (!armv7m->stlink) {
2055 if (i == 3 || i == 4)
2056 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2057 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2058 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2059 else if (i == 7)
2060 /* Cortex-M7 has only 1024 bytes autoincrement range */
2061 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2062 }
2063
2064 /* Enable debug requests */
2065 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2066 if (retval != ERROR_OK)
2067 return retval;
2068 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2069 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2070
2071 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2072 if (retval != ERROR_OK)
2073 return retval;
2074 cortex_m->dcb_dhcsr = dhcsr;
2075 }
2076
2077 /* Configure trace modules */
2078 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2079 if (retval != ERROR_OK)
2080 return retval;
2081
2082 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2083 armv7m_trace_tpiu_config(target);
2084 armv7m_trace_itm_config(target);
2085 }
2086
2087 /* NOTE: FPB and DWT are both optional. */
2088
2089 /* Setup FPB */
2090 target_read_u32(target, FP_CTRL, &fpcr);
2091 /* bits [14:12] and [7:4] */
2092 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2093 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2094 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2095 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2096 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2097 free(cortex_m->fp_comparator_list);
2098 cortex_m->fp_comparator_list = calloc(
2099 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2100 sizeof(struct cortex_m_fp_comparator));
2101 cortex_m->fpb_enabled = fpcr & 1;
2102 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2103 cortex_m->fp_comparator_list[i].type =
2104 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2105 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2106
2107 /* make sure we clear any breakpoints enabled on the target */
2108 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2109 }
2110 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2111 fpcr,
2112 cortex_m->fp_num_code,
2113 cortex_m->fp_num_lit);
2114
2115 /* Setup DWT */
2116 cortex_m_dwt_free(target);
2117 cortex_m_dwt_setup(cortex_m, target);
2118
2119 /* These hardware breakpoints only work for code in flash! */
2120 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2121 target_name(target),
2122 cortex_m->fp_num_code,
2123 cortex_m->dwt_num_comp);
2124 }
2125
2126 return ERROR_OK;
2127 }
2128
2129 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2130 {
2131 struct armv7m_common *armv7m = target_to_armv7m(target);
2132 uint16_t dcrdr;
2133 uint8_t buf[2];
2134 int retval;
2135
2136 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2137 if (retval != ERROR_OK)
2138 return retval;
2139
2140 dcrdr = target_buffer_get_u16(target, buf);
2141 *ctrl = (uint8_t)dcrdr;
2142 *value = (uint8_t)(dcrdr >> 8);
2143
2144 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2145
2146 /* write ack back to software dcc register
2147 * signify we have read data */
2148 if (dcrdr & (1 << 0)) {
2149 target_buffer_set_u16(target, buf, 0);
2150 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2151 if (retval != ERROR_OK)
2152 return retval;
2153 }
2154
2155 return ERROR_OK;
2156 }
2157
2158 static int cortex_m_target_request_data(struct target *target,
2159 uint32_t size, uint8_t *buffer)
2160 {
2161 uint8_t data;
2162 uint8_t ctrl;
2163 uint32_t i;
2164
2165 for (i = 0; i < (size * 4); i++) {
2166 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2167 if (retval != ERROR_OK)
2168 return retval;
2169 buffer[i] = data;
2170 }
2171
2172 return ERROR_OK;
2173 }
2174
2175 static int cortex_m_handle_target_request(void *priv)
2176 {
2177 struct target *target = priv;
2178 if (!target_was_examined(target))
2179 return ERROR_OK;
2180
2181 if (!target->dbg_msg_enabled)
2182 return ERROR_OK;
2183
2184 if (target->state == TARGET_RUNNING) {
2185 uint8_t data;
2186 uint8_t ctrl;
2187 int retval;
2188
2189 retval = cortex_m_dcc_read(target, &data, &ctrl);
2190 if (retval != ERROR_OK)
2191 return retval;
2192
2193 /* check if we have data */
2194 if (ctrl & (1 << 0)) {
2195 uint32_t request;
2196
2197 /* we assume target is quick enough */
2198 request = data;
2199 for (int i = 1; i <= 3; i++) {
2200 retval = cortex_m_dcc_read(target, &data, &ctrl);
2201 if (retval != ERROR_OK)
2202 return retval;
2203 request |= ((uint32_t)data << (i * 8));
2204 }
2205 target_request(target, request);
2206 }
2207 }
2208
2209 return ERROR_OK;
2210 }
2211
2212 static int cortex_m_init_arch_info(struct target *target,
2213 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2214 {
2215 struct armv7m_common *armv7m = &cortex_m->armv7m;
2216
2217 armv7m_init_arch_info(target, armv7m);
2218
2219 /* default reset mode is to use srst if fitted
2220 * if not it will use CORTEX_M3_RESET_VECTRESET */
2221 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2222
2223 armv7m->arm.dap = dap;
2224
2225 /* register arch-specific functions */
2226 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2227
2228 armv7m->post_debug_entry = NULL;
2229
2230 armv7m->pre_restore_context = NULL;
2231
2232 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2233 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2234
2235 target_register_timer_callback(cortex_m_handle_target_request, 1,
2236 TARGET_TIMER_TYPE_PERIODIC, target);
2237
2238 return ERROR_OK;
2239 }
2240
2241 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2242 {
2243 struct adiv5_private_config *pc;
2244
2245 pc = (struct adiv5_private_config *)target->private_config;
2246 if (adiv5_verify_config(pc) != ERROR_OK)
2247 return ERROR_FAIL;
2248
2249 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2250 if (cortex_m == NULL) {
2251 LOG_ERROR("No memory creating target");
2252 return ERROR_FAIL;
2253 }
2254
2255 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2256 cortex_m->apsel = pc->ap_num;
2257
2258 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2259
2260 return ERROR_OK;
2261 }
2262
2263 /*--------------------------------------------------------------------------*/
2264
2265 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2266 struct cortex_m_common *cm)
2267 {
2268 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2269 command_print(cmd, "target is not a Cortex-M");
2270 return ERROR_TARGET_INVALID;
2271 }
2272 return ERROR_OK;
2273 }
2274
2275 /*
2276 * Only stuff below this line should need to verify that its target
2277 * is a Cortex-M3. Everything else should have indirected through the
2278 * cortexm3_target structure, which is only used with CM3 targets.
2279 */
2280
2281 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2282 {
2283 struct target *target = get_current_target(CMD_CTX);
2284 struct cortex_m_common *cortex_m = target_to_cm(target);
2285 struct armv7m_common *armv7m = &cortex_m->armv7m;
2286 uint32_t demcr = 0;
2287 int retval;
2288
2289 static const struct {
2290 char name[10];
2291 unsigned mask;
2292 } vec_ids[] = {
2293 { "hard_err", VC_HARDERR, },
2294 { "int_err", VC_INTERR, },
2295 { "bus_err", VC_BUSERR, },
2296 { "state_err", VC_STATERR, },
2297 { "chk_err", VC_CHKERR, },
2298 { "nocp_err", VC_NOCPERR, },
2299 { "mm_err", VC_MMERR, },
2300 { "reset", VC_CORERESET, },
2301 };
2302
2303 retval = cortex_m_verify_pointer(CMD, cortex_m);
2304 if (retval != ERROR_OK)
2305 return retval;
2306
2307 if (!target_was_examined(target)) {
2308 LOG_ERROR("Target not examined yet");
2309 return ERROR_FAIL;
2310 }
2311
2312 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2313 if (retval != ERROR_OK)
2314 return retval;
2315
2316 if (CMD_ARGC > 0) {
2317 unsigned catch = 0;
2318
2319 if (CMD_ARGC == 1) {
2320 if (strcmp(CMD_ARGV[0], "all") == 0) {
2321 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2322 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2323 | VC_MMERR | VC_CORERESET;
2324 goto write;
2325 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2326 goto write;
2327 }
2328 while (CMD_ARGC-- > 0) {
2329 unsigned i;
2330 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2331 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2332 continue;
2333 catch |= vec_ids[i].mask;
2334 break;
2335 }
2336 if (i == ARRAY_SIZE(vec_ids)) {
2337 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2338 return ERROR_COMMAND_SYNTAX_ERROR;
2339 }
2340 }
2341 write:
2342 /* For now, armv7m->demcr only stores vector catch flags. */
2343 armv7m->demcr = catch;
2344
2345 demcr &= ~0xffff;
2346 demcr |= catch;
2347
2348 /* write, but don't assume it stuck (why not??) */
2349 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2350 if (retval != ERROR_OK)
2351 return retval;
2352 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2353 if (retval != ERROR_OK)
2354 return retval;
2355
2356 /* FIXME be sure to clear DEMCR on clean server shutdown.
2357 * Otherwise the vector catch hardware could fire when there's
2358 * no debugger hooked up, causing much confusion...
2359 */
2360 }
2361
2362 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2363 command_print(CMD, "%9s: %s", vec_ids[i].name,
2364 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2365 }
2366
2367 return ERROR_OK;
2368 }
2369
2370 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2371 {
2372 struct target *target = get_current_target(CMD_CTX);
2373 struct cortex_m_common *cortex_m = target_to_cm(target);
2374 int retval;
2375
2376 static const Jim_Nvp nvp_maskisr_modes[] = {
2377 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2378 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2379 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2380 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2381 { .name = NULL, .value = -1 },
2382 };
2383 const Jim_Nvp *n;
2384
2385
2386 retval = cortex_m_verify_pointer(CMD, cortex_m);
2387 if (retval != ERROR_OK)
2388 return retval;
2389
2390 if (target->state != TARGET_HALTED) {
2391 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2392 return ERROR_OK;
2393 }
2394
2395 if (CMD_ARGC > 0) {
2396 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2397 if (n->name == NULL)
2398 return ERROR_COMMAND_SYNTAX_ERROR;
2399 cortex_m->isrmasking_mode = n->value;
2400 cortex_m_set_maskints_for_halt(target);
2401 }
2402
2403 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2404 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2405
2406 return ERROR_OK;
2407 }
2408
2409 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2410 {
2411 struct target *target = get_current_target(CMD_CTX);
2412 struct cortex_m_common *cortex_m = target_to_cm(target);
2413 int retval;
2414 char *reset_config;
2415
2416 retval = cortex_m_verify_pointer(CMD, cortex_m);
2417 if (retval != ERROR_OK)
2418 return retval;
2419
2420 if (CMD_ARGC > 0) {
2421 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2422 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2423
2424 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2425 if (target_was_examined(target)
2426 && !cortex_m->vectreset_supported)
2427 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2428 else
2429 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2430
2431 } else
2432 return ERROR_COMMAND_SYNTAX_ERROR;
2433 }
2434
2435 switch (cortex_m->soft_reset_config) {
2436 case CORTEX_M_RESET_SYSRESETREQ:
2437 reset_config = "sysresetreq";
2438 break;
2439
2440 case CORTEX_M_RESET_VECTRESET:
2441 reset_config = "vectreset";
2442 break;
2443
2444 default:
2445 reset_config = "unknown";
2446 break;
2447 }
2448
2449 command_print(CMD, "cortex_m reset_config %s", reset_config);
2450
2451 return ERROR_OK;
2452 }
2453
2454 static const struct command_registration cortex_m_exec_command_handlers[] = {
2455 {
2456 .name = "maskisr",
2457 .handler = handle_cortex_m_mask_interrupts_command,
2458 .mode = COMMAND_EXEC,
2459 .help = "mask cortex_m interrupts",
2460 .usage = "['auto'|'on'|'off'|'steponly']",
2461 },
2462 {
2463 .name = "vector_catch",
2464 .handler = handle_cortex_m_vector_catch_command,
2465 .mode = COMMAND_EXEC,
2466 .help = "configure hardware vectors to trigger debug entry",
2467 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2468 },
2469 {
2470 .name = "reset_config",
2471 .handler = handle_cortex_m_reset_config_command,
2472 .mode = COMMAND_ANY,
2473 .help = "configure software reset handling",
2474 .usage = "['sysresetreq'|'vectreset']",
2475 },
2476 COMMAND_REGISTRATION_DONE
2477 };
2478 static const struct command_registration cortex_m_command_handlers[] = {
2479 {
2480 .chain = armv7m_command_handlers,
2481 },
2482 {
2483 .chain = armv7m_trace_command_handlers,
2484 },
2485 {
2486 .name = "cortex_m",
2487 .mode = COMMAND_EXEC,
2488 .help = "Cortex-M command group",
2489 .usage = "",
2490 .chain = cortex_m_exec_command_handlers,
2491 },
2492 COMMAND_REGISTRATION_DONE
2493 };
2494
2495 struct target_type cortexm_target = {
2496 .name = "cortex_m",
2497 .deprecated_name = "cortex_m3",
2498
2499 .poll = cortex_m_poll,
2500 .arch_state = armv7m_arch_state,
2501
2502 .target_request_data = cortex_m_target_request_data,
2503
2504 .halt = cortex_m_halt,
2505 .resume = cortex_m_resume,
2506 .step = cortex_m_step,
2507
2508 .assert_reset = cortex_m_assert_reset,
2509 .deassert_reset = cortex_m_deassert_reset,
2510 .soft_reset_halt = cortex_m_soft_reset_halt,
2511
2512 .get_gdb_arch = arm_get_gdb_arch,
2513 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2514
2515 .read_memory = cortex_m_read_memory,
2516 .write_memory = cortex_m_write_memory,
2517 .checksum_memory = armv7m_checksum_memory,
2518 .blank_check_memory = armv7m_blank_check_memory,
2519
2520 .run_algorithm = armv7m_run_algorithm,
2521 .start_algorithm = armv7m_start_algorithm,
2522 .wait_algorithm = armv7m_wait_algorithm,
2523
2524 .add_breakpoint = cortex_m_add_breakpoint,
2525 .remove_breakpoint = cortex_m_remove_breakpoint,
2526 .add_watchpoint = cortex_m_add_watchpoint,
2527 .remove_watchpoint = cortex_m_remove_watchpoint,
2528
2529 .commands = cortex_m_command_handlers,
2530 .target_create = cortex_m_target_create,
2531 .target_jim_configure = adiv5_jim_configure,
2532 .init_target = cortex_m_init_target,
2533 .examine = cortex_m_examine,
2534 .deinit_target = cortex_m_deinit_target,
2535
2536 .profiling = cortex_m_profiling,
2537 };
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